Memory device and write-in frequency detection method thereof

Abstract

The invention provides a memory device and a write-in frequency detection method thereof, the memory device comprises a nonvolatile memory and a memory controller coupled with the nonvolatile memory, and the nonvolatile memory comprises a plurality of memory blocks. The memory controller detects a total write-in frequency of each memory block. And when the total write-in frequency is greater than or equal to 1, the memory controller progressively increases the block count value or sets the block count value as the maximum count value. And when the total write-in frequency is not greater than or equal to 1, the memory controller progressively decreases the block count value or sets the block count value as the minimum count value. When the newest block count value is greater than or equal to a pre-designed value, the memory controller generates a warning signal and returns the total write-in frequency to zero.

Description

Technical Field

[0001] The present invention relates to a technology for detecting the number of write operations, and particularly to a memory device and a method for detecting the number of write operations thereof. Background Art

[0002] Today, with the development of computer information products, Electrically Erasable Programmable Read Only Memory (EEPROM) is widely used in electronic products because it has the function of electrically programming and erasing data, which is a non-volatile memory, and the data will not be lost after the power is turned off.

[0003] However, the number of write operations for each storage address is limited, usually about 1 million times. If a write operation is performed once per second, within about two weeks, the Electrically Erasable Programmable Read Only Memory will reach its write operation limit and may be damaged. In recent years, the user's demand for remote real-time control has increased, and it is necessary to frequently adjust voltage and current parameters through communication. For example, applications such as lithium battery charging control and water electrolysis are involved, and the adjustment frequency is as high as once every 1 to 2 seconds. Since the existing power product design stores set data locally, if the storage integrated circuit (IC) is written frequently, its lifespan will be affected. In addition, the program memory has an unpredictable abnormal operation mode, which may cause the Electrically Erasable Programmable Read Only Memory to prematurely exhaust its lifespan and cannot be detected early.

[0004] Therefore, in view of the above problems, the present invention provides a memory device and a method for detecting the number of write operations thereof to solve the problems caused by the prior art. Summary of the Invention

[0005] The present invention provides a memory device and a method for detecting the number of write operations thereof, which reduce the write inefficiency and extend the service life.

[0006] In an embodiment of the present invention, a method for detecting the number of write operations is provided, which is applied to a non-volatile memory. The non-volatile memory includes a plurality of storage blocks. The method for detecting the number of write operations includes the following steps:

[0007] Set a block count value corresponding to each storage block, where the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value;

[0008] Perform a plurality of detection processes at a fixed frequency. Each detection process includes the following steps:

[0009] Detect the total number of write operations of each storage block;

[0010] Judge whether the total number of write operations is greater than or equal to 1:

[0011] If so, determine whether the block count value corresponding to the total write count is equal to the maximum count value:

[0012] If so, maintain the block count value corresponding to the total write count; and

[0013] If not, increment the block count value corresponding to the total write count; and

[0014] If not, determine whether the block count value corresponding to the total write count is equal to the minimum count value:

[0015] If so, maintain the block count value corresponding to the total write count; and

[0016] If not, decrement the block count value corresponding to the total write count; and

[0017] Determine whether the latest block count value corresponding to the total write count is greater than or equal to a preset value:

[0018] If so, generate a warning signal and reset the total write count to zero; and

[0019] If not, determine whether a warning signal has already been generated:

[0020] If so, stop generating the warning signal and reset the total write count to zero; and

[0021] If not, reset the total write count to zero.

[0022] In an embodiment of the present invention, the minimum count value is 0 and the maximum count value is 255.

[0023] In an embodiment of the present invention, when the warning signal is generated, the write delay is increased.

[0024] In an embodiment of the present invention, when the generation of the warning signal is stopped, the write delay is decreased.

[0025] In an embodiment of the present invention, the non-volatile memory is an electrically erasable programmable read-only memory.

[0026] In an embodiment of the present invention, a memory device includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of storage blocks. The memory controller is coupled to the non-volatile memory and is configured to set a block count value corresponding to each storage block. The block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value. The memory controller is configured to detect the total number of write operations of each storage block. When the total number of write operations is greater than or equal to 1, the memory controller increments the block count value corresponding to the total number of write operations, or sets it to the maximum count value. When the total number of write operations is not greater than or equal to 1, the memory controller decrements the block count value corresponding to the total number of write operations, or sets it to the minimum count value. When the latest block count value corresponding to the total number of write operations is greater than or equal to a preset value, the memory controller generates a warning signal and resets the total number of write operations to zero.

[0027] In an embodiment of the present invention, the memory controller includes a plurality of block counters, a plurality of write counters, a row decoder, a column decoder, and a processor. The block counters are configured to count the block count values corresponding to the storage blocks respectively. The write counters are configured to count the total number of write operations corresponding to the storage blocks respectively. The row decoder and the column decoder are coupled to the storage blocks. The processor is coupled to the block counters, the write counters, the row decoder, and the column decoder, and is configured to set and detect the block count values and the total number of write operations, drive the row decoder and the column decoder to perform write operations on the storage blocks, and generate a warning signal.

[0028] In an embodiment of the present invention, the minimum count value is 0 and the maximum count value is 255.

[0029] In an embodiment of the present invention, when the warning signal is generated, the memory controller increases the write latency.

[0030] In an embodiment of the present invention, the non-volatile memory is an electrically erasable programmable read-only memory.

[0031] Based on the above, the memory device and its write count detection method set the block count value corresponding to each storage block, adjust the block count value according to the total number of write operations of the storage block, and generate a warning signal when the block count value is greater than the preset value, so as to reduce the write inefficiency and extend the service life. Description of the Drawings

[0032] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0033] Figure 1 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention;

[0034] Figure 2Schematic diagram of the non-volatile memory according to another embodiment of the present invention;

[0035] Figure 3 Schematic diagram of the memory device according to an embodiment of the present invention;

[0036] Figure 4 Flowchart of the write count detection method according to an embodiment of the present invention;

[0037] Figure 5 Flowchart of the detection process according to an embodiment of the present invention;

[0038] Figure 6 Schematic diagram of the total write count, block count value, and storage value corresponding to each storage block according to an embodiment of the present invention;

[0039] Figure 7 Schematic diagram of the total write count, block count value, and storage value corresponding to each storage block according to another embodiment of the present invention;

[0040] Figure 8 Schematic diagram of the total write count, block count value, and storage value corresponding to each storage block according to still another embodiment of the present invention.

[0041] Reference numerals:

[0042] 1: Memory device

[0043] 10: Non-volatile memory

[0044] 11: Memory controller

[0045] 110: Row decoder

[0046] 111: Column decoder

[0047] 112: Processor

[0048] B1: First block

[0049] B2: Second block

[0050] B3: Third block

[0051] B4: Fourth block

[0052] M: Main area

[0053] B: Backup area

[0054] MB1, MB2: Storage blocks

[0055] BC1, BC2: Block counters

[0056] WC1, WC2: Write counters

[0057] K: Write instruction

[0058] W: Warning signal

[0059] C1: Total write count

[0060] C2: Block count value

[0061] S: Stored value

[0062] S10, S12, S14, S16, S18, S20, S24, S26, S28, S30, S32, S34, S36, S38: Steps Detailed implementation manner

[0063] Embodiments of the present invention will be further explained below in conjunction with relevant drawings. As much as possible, in the drawings and the specification, the same reference numerals represent the same or similar components. In the drawings, for the sake of simplicity and convenience of marking, the shapes and thicknesses may be exaggerated. It can be understood that the elements not specifically shown in the drawings or described in the specification are in the forms known to those skilled in the art. Those skilled in the art can make various changes and modifications according to the content of the present invention.

[0064] Unless otherwise specified, some conditional sentences or words, such as "can", "may", "perhaps", or "could", usually attempt to express that the embodiments of the present case have, but can also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may not be required.

[0065] The description of "an embodiment" or "one embodiment" hereinafter refers to a specific element, structure, or feature related to at least one embodiment. Therefore, the multiple descriptions of "an embodiment" or "one embodiment" that appear in multiple places hereinafter do not refer to the same embodiment. Furthermore, the specific components, structures, and features in one or more embodiments can be combined in an appropriate manner.

[0066] In the specification and the scope of the claims, certain terms are used to refer to specific elements. However, those skilled in the art should understand that the same element may be referred to by different names. The specification and the scope of the claims do not use the difference in names as a way to distinguish elements, but use the difference in the functions of elements as the basis for distinction. The term "comprising" mentioned in the specification and the scope of the claims is an open term and should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if the main element is described as being coupled to the secondary element in the text, it means that the main element can be directly connected to the secondary element through electrical connection or signal connection means such as wireless transmission and optical transmission, or can be indirectly electrically or signal-connected to the secondary element through other elements or connection means.

[0067] The present invention will be specifically described by the following examples which are only for illustrative purposes. For those skilled in the art, various modifications and refinements can be made without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be determined by the scope of the appended claims. Throughout the specification and the scope of the claims, unless clearly specified otherwise, the meanings of "a" and "the" include such descriptions including "one or at least one" of the described elements or components. In addition, as used in the present application, unless it is clearly visible from a specific context to exclude the plural, the singular article also includes the description of plural elements or components. Moreover, when applied in the description herein and the entire scope of the following claims, unless clearly specified otherwise, the meaning of "in which" may include "in which" and "on which". The terms used throughout the specification and the scope of the claims, unless otherwise noted, generally have their ordinary meanings as used in this field, in the context of this application, and in the specific context. Some of the terms used to describe the present application will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of the present application. Any examples anywhere in the specification, including the use of any examples of the terms discussed herein, are only for illustrative purposes and do not limit the scope and meaning of the present application or any of the illustrative terms. Similarly, the present application is not limited to the various embodiments presented in this specification.

[0068] Figure 1 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. Please refer to Figure 1 , the non-volatile memory 10 includes a plurality of blocks, such as a first block B1, a second block B2, a third block B3, and a fourth block B4. A common method to extend the lifespan of the non-volatile memory 10 is through the backup technology of wear leveling, which disperses data to different blocks to avoid repeatedly writing to the same block, thereby balancing the wear of the memory cells and extending their service life. Figure 2 is a schematic diagram of a non-volatile memory according to another embodiment of the present invention. When considering the capacity of the non-volatile memory, it can also be divided into two areas, as Figure 2 shown, that is, the backup mechanism of the main area M and the backup area B. When starting up, if it is found that the data in the main area M is incorrect, the data in the backup area B is used to update the data in the main area M. If it is found that the data in the main area M is correct and inconsistent with the data in the backup area B, the data in the main area M is used to update the data in the backup area B to ensure the correctness of the data.

[0069] Based on the above backup mechanism, a memory device of the present invention and its write count detection method will be proposed below. It adjusts the block count value, and when the block count value is greater than a preset value, that is, when a write anomaly event occurs, it generates a warning signal to reduce the write failure rate and increases the write latency to extend the service life.

[0070] Figure 3 is a schematic diagram of a memory device according to an embodiment of the present invention. Please refer to Figure 3 , the memory device 1 includes a non-volatile memory 10 and a memory controller 11. The non-volatile memory 10 is coupled to the memory controller 11. The non-volatile memory 10 can be, but is not limited to, an electrically erasable programmable read-only memory (EEPROM). The non-volatile memory 10 includes a plurality of storage blocks MB1 and MB2. The memory controller 11 sets a block count value corresponding to each storage block MB1 and MB2, where the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value. For example, the minimum count value is 0 and the maximum count value is 255. The memory controller 11 detects the total write count of each storage block MB1 and MB2. When the total write count is greater than or equal to 1, the memory controller 11 increments the block count value corresponding to the total write count or sets it to the maximum count value. When the total write count is not greater than or equal to 1, the memory controller 11 decrements the block count value corresponding to the total write count or sets it to the minimum count value. When the latest block count value corresponding to the total write count is greater than or equal to a preset value, the memory controller 11 generates a warning signal W and resets the total write count to zero to reduce the write failure rate. In some embodiments of the present invention, when the warning signal W is generated, the memory controller 11 increases the write latency to reduce the total write count within a fixed period, thereby extending the service life of the memory device 1. Write latency refers to the time difference between when the data is ready and when it is actually written.

[0071] In some embodiments of the present invention, the memory controller 11 may include a plurality of block counters BC1 and BC2, a plurality of write counters WC1 and WC2, a row decoder 110, a column decoder 111, and a processor 112. The block counters BC1 and BC2 respectively count block count values corresponding to the storage blocks MB1 and MB2, and the write counters WC1 and WC2 respectively count the total number of writes corresponding to the storage blocks MB1 and MB2. The row decoder 110 and the column decoder 111 are coupled to the storage blocks MB1 and MB2. The processor 112 is coupled to the block counters BC1 and BC2, the write counters WC1 and WC2, the row decoder 110, and the column decoder 111. The processor 112 receives a write instruction K, and accordingly sets and detects the block count values and the total number of writes, and drives the row decoder 110 and the column decoder 111 to perform a write operation on the storage blocks MB1 and MB2, and generates a warning signal W. The write instruction K may be a background write instruction or a user write instruction.

[0072] Figure 4 is a flowchart of a write count detection method according to an embodiment of the present invention. Please refer to Figure 3 and Figure 4 , the write count detection method is applied to a non-volatile memory 10, and the non-volatile memory includes a plurality of storage blocks MB1 and MB2. In the write count detection method, first, as shown in step S10, the processor 112 controls the block counters BC1 and BC2 to set a block count value corresponding to each of the storage blocks MB1 and MB2. Next, as shown in step S12, the processor 112 performs a plurality of detection processes at a fixed frequency. For example, a detection process is performed every five seconds.

[0073] Figure 5 is a flowchart of a detection process according to an embodiment of the present invention. Please refer to Figure 3 and Figure 5, first, as shown in step S14, the processor 112 detects the total write count of each storage block MB1 and MB2. Next, as shown in step S16, the processor 112 determines whether the total write count is greater than or equal to 1. If so, step S18 is performed; if not, step S20 is performed. In step S18, the processor 112 determines whether the block count value corresponding to the total write count is equal to the maximum count value. If so, step S22 is performed; if not, step S24 is performed. In step S20, the processor 112 determines whether the block count value corresponding to the total write count is equal to the minimum count value. If so, step S26 is performed; if not, step S28 is performed. In step S22, the processor 112 maintains the block count value corresponding to the total write count. In step S24, the processor 112 increments the block count value corresponding to the total write count, for example, by 1 each time. In step S26, the processor 112 maintains the block count value corresponding to the total write count. In step S28, the processor 112 decrements the block count value corresponding to the total write count, for example, by 1 each time. After step S22, S24, S26, or S28, step S30 is performed. In step S30, the processor 112 determines whether the latest block count value corresponding to the total write count is greater than or equal to a preset value. For example, the preset value is 4. If so, step S32 is performed; if not, step S34 is performed. In step S32, the processor 112 generates a warning signal W and resets the total write count to zero. In step S34, the processor 112 determines whether a warning signal W has already been generated. If so, the processor 112 stops generating the warning signal W and resets the total write count to zero, as shown in step S36. If not, the processor 112 resets the total write count to zero, as shown in step S38. If substantially the same result can be obtained, these steps do not necessarily have to be performed Figure 5 in the order of execution shown. When the warning signal W is generated, the processor 112 can further increase the write latency. When the warning signal W stops being generated, the processor 112 can further reduce the write latency. In addition, in steps S16, S18, S20, S22, S24, S26, S28, S30, S32, S36, and S38, the processor 112 determines or controls the total write count or the block count value corresponding to the same storage block MB1 or MB2.

[0074] Figure 6 is a schematic diagram of the total write count, the block count value, and the stored value corresponding to each storage block in an embodiment of the present invention. Please refer to Figure 6, in this embodiment, it is assumed that there are 16 storage blocks, which are arranged in a 4×4 array. C1 represents the total write count of each storage block, C2 represents the block count value of each storage block, and S represents the stored value of each storage block. The non-volatile memory 10 includes the stored value S of each storage block, and the memory controller 11 includes the total write count C1 and the block count value C2 of each storage block. The total write count C1, the block count value C2, and the stored value S corresponding to each storage block change sequentially from top to bottom, and the detection process is performed once every 5 seconds. The preset value is 4. First, the total write count C1, the block count value C2, and the stored value S corresponding to each storage block in the initial state of the detection process are located at Figure 6 the topmost. Then, a write request is initiated to write 0x64 to the storage block at the 4th column of the 2nd row. Therefore, 0xDD is immediately written as 0x64, and its corresponding total write count increases from 0 to 1. Next, another write request is initiated to write 0x87 to the storage block at the 4th column of the 2nd row. Therefore, 0x64 is immediately written as 0x87, and its corresponding total write count increases from 1 to 2. Then, another write request is initiated to write 0xF2 to the storage block at the 4th column of the 2nd row. Therefore, 0x87 is immediately written as 0xF2, and its corresponding total write count increases from 2 to 3. Finally, when 5 seconds arrive, since the block count value of the storage block at the 4th column of the 2nd row is not equal to the maximum count value, the block count value of the storage block at the 4th column of the 2nd row is incremented from 0 to 1, and the total write count is reset to 0.

[0075] Figure 7 is a schematic diagram of the total write count, the block count value, and the stored value corresponding to each storage block in another embodiment of the present invention. Please refer to Figure 7 , in this embodiment, it is assumed that there are 16 storage blocks, which are arranged in a 4×4 array. C1 represents the total write count of each storage block, C2 represents the block count value of each storage block, and S represents the stored value of each storage block. The non-volatile memory 10 includes the stored value S of each storage block, and the memory controller 11 includes the total write count C1 and the block count value C2 of each storage block. The total write count C1, the block count value C2, and the stored value S corresponding to each storage block change sequentially from top to bottom, and the detection process is performed once every 5 seconds. The preset value is 4. First, the total write count C1, the block count value C2, and the stored value S corresponding to each storage block in the initial state of the detection process are located at Figure 7At the top. Then, a write request is initiated to write 0x64 to the storage block at the 4th column of the 2nd row. Therefore, 0xF2 is immediately written as 0x64, and the corresponding total write count increases from 0 to 1. Finally, when the 5th second arrives, since the block count value of the block at the 4th column of the 2nd row does not equal the maximum count value, the block count value of the block at the 4th column of the 2nd row is incremented from 3 to 4, the total write count is reset to 0, and at the same time, the memory controller 11 generates a warning signal.

[0076] Figure 8 is a schematic diagram of the total write count, block count value, and stored value corresponding to each storage block in another embodiment of the present invention. Please refer to Figure 8 , in this embodiment, it is assumed that there are 16 storage blocks, which are arranged in a 4×4 array. C1 represents the total write count of each storage block, C2 represents the block count value of each storage block, and S represents the stored value of each storage block. The non-volatile memory 10 includes the stored value S of each storage block, and the memory controller 11 includes the total write count C1 and the block count value C2 of each storage block. The total write count C1, block count value C2, and stored value S corresponding to each storage block change sequentially from top to bottom, and the detection process is performed once every 5 seconds, and the preset count value is 4. First, the total write count C1, block count value C2, and stored value S corresponding to each storage block in the initial state of the detection process are located at Figure 8 at the top, where the total write count of the storage block at the 4th column of the 2nd row is 1 and the block count value is 4. Since the block count value equals the preset count value, the write delay is increased. At this time, if it is desired to write 0x87 to the storage block at the 4th column of the 2nd row, the storage block at the 4th column of the 2nd row cannot be immediately written with 0x87. Then, within i seconds, if no other write requests are initiated, then after i seconds, as shown Figure 8 below, the write request for 0x87 is executed. At this time, if i is greater than or equal to 5, the total write count C1 in the lower right figure will be cleared to 0, and the block count value C2 of the storage block at the 4th column of the 2nd row is incremented to 5. On the contrary, if other write requests are initiated within i seconds, the count of the delay time will be reset. Therefore, if write requests are initiated every i seconds, the actual write will be infinitely delayed, thereby protecting the non-volatile memory. Since the timing of i seconds and the timing of the detection process at a fixed frequency are independent of each other, this situation will also cause the total write count C1 and the block count value C2 to keep increasing.

[0077] According to the above embodiments, for the memory device and its write count detection method, it adjusts the block count value, and when the block count value is greater than the preset count value, a warning signal is generated to reduce the write failure rate and extend the service life.

[0078] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications made in accordance with the shape, structure, features and spirit described in the scope of the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A write count detection method is applied to a non-volatile memory, and the non-volatile memory includes a plurality of storage blocks, characterized in that, The write count detection method includes the following steps: Set a block count value corresponding to each of the storage blocks, where the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value; Perform multiple detection processes at a fixed frequency, and each of the detection processes includes the following steps: Detect the total write count of each of the storage blocks; Determine whether the total write count is greater than or equal to 1: If so, determine whether the block count value corresponding to the total write count is equal to the maximum count value: If so, maintain the block count value corresponding to the total write count; And If not, increment the block count value corresponding to the total write count; And If not, determine whether the block count value corresponding to the total write count is equal to the minimum count value: If so, maintain the block count value corresponding to the total write count; And If not, decrement the block count value corresponding to the total write count; And Determine whether the latest block count value corresponding to the total write count is greater than or equal to a preset value: If so, generate a warning signal and reset the total write count to zero; And If not, determine whether a warning signal has been generated: If so, stop generating the warning signal and reset the total write count to zero; and If not, reset the total write count to zero.

2. The write count detection method according to claim 1, wherein The minimum count value is 0 and the maximum count value is 255.

3. The write count detection method according to claim 1, wherein When the warning signal is generated, increase the write delay.

4. The write count detection method according to claim 3, wherein When the warning signal stops being generated, reduce the write delay.

5. The write count detection method according to claim 1, wherein The non-volatile memory is an electrically erasable programmable read-only memory.

6. A memory device, characterized in that, The memory device includes: A non-volatile memory including a plurality of storage blocks; and A memory controller coupled to the non-volatile memory and configured to set a block count value corresponding to each of the storage blocks, where the block count value is greater than or equal to a minimum count value and less than or equal to a maximum count value, the memory controller is configured to detect the total write count of each of the storage blocks, when the total write count is greater than or equal to 1, the memory controller increments the block count value corresponding to the total write count or sets it to the maximum count value, when the total write count is not greater than or equal to 1, the memory controller decrements the block count value corresponding to the total write count or sets it to the minimum count value, when the latest block count value corresponding to the total write count is greater than or equal to a preset value, the memory controller generates a warning signal and resets the total write count to zero.

7. The memory device according to claim 6, wherein The memory controller includes: A plurality of block counters for respectively counting the block count values corresponding to the plurality of storage blocks; A plurality of write counters for respectively counting the total write counts corresponding to the plurality of storage blocks; A row decoder and a column decoder coupled to the plurality of storage blocks; and A processor, coupled to the plurality of block counters, the plurality of write counters, the row decoder, and the column decoder, and configured to set and detect the block count value and the total number of writes, and drive the row decoder and the column decoder to perform a write operation on the storage block, and generate the warning signal.

8. The memory device according to claim 6, wherein The minimum count value is 0, and the maximum count value is 255.

9. The memory device according to claim 6, wherein When the warning signal is generated, the memory controller increases the write latency.

10. The memory device according to claim 6, wherein The non-volatile memory is an electrically erasable programmable read-only memory.

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