Data storage system and method based on RISCV and integrated circuit

Abstract

The invention provides a data storage system and method based on RISCV and an integrated circuit. The method comprises the steps that a local module generates local data; the user module is a hardcore module of the RISCV and generates user data; the asynchronous module converts the clock domain of the user data into the clock domain of the local data; the arbitration module receives local data by using the APP interface, receives the user data after clock domain conversion by using the AHB interface, and converts the received local data and user data into APP data; the control module converts the APP data into a time sequence signal of the DDR particles; and the DDR particles receive and store data carried by the time sequence signal. The DDR particles are used as the storage medium, the AHB interface corresponding to the user module of the RISCV is used as the data transmission interface, the AHB interface and the APP interface of the DDR protocol are converted through the arbitration module, the high-speed and high-performance characteristics of the DDR and the AHB can be fully utilized, high-speed data interaction between the RISCV and the DDR is achieved, and the data transmission efficiency is improved. The problem of how to realize high-speed data storage based on the RISCV microcontroller is solved.

Description

Technical Field

[0001] The present invention relates to the technical fields of integrated circuits and data storage, and particularly relates to a RISC-V based data storage system and method, and an integrated circuit. Background Art

[0002] Today, with the rapid growth of the Internet of Things industry, there is an increasing number of devices that require microcontrollers. As a mainstream microcontroller manufacturer, ARM controls the vast majority of the market. Since ARM's controllers are supplied to the market in the form of IP licenses, high licensing fees need to be paid, resulting in high controller costs.

[0003] To solve the problem of high costs caused by using ARM controllers, a reduced instruction set of the RISC-V core was proposed by the University of California, Berkeley. Compared with ARM, RISC-V has a more compact design, which is conducive to the rapid iteration of products in Internet of Things design and is suitable for the application of more small-scale controllers.

[0004] With the development of RISC-V, the performance of RISC-V based microcontrollers is getting stronger and the frequency is getting higher. However, in the prior art, Flash memory chips are usually used for data storage, and the rate of Flash memory chips is usually low, which cannot meet the high-speed data interaction with RISC-V microcontrollers, restricting the application of RISC-V microcontrollers in data storage. Summary of the Invention

[0005] The purpose of the present invention is to provide a RISC-V based data storage system and method, and an integrated circuit, so as to solve the problem of how to achieve high-speed data storage based on RISC-V microcontrollers.

[0006] To solve the above technical problems, the present invention provides a RISC-V based data storage system, including: A local module, used to generate local data; A user module, which is a hard core module of RISC-V, used to generate user data; An asynchronous module, used to convert the clock domain of the user data to the clock domain of the local data; An arbitration module, used to receive the local data generated by the local module through the APP interface, and is also used to receive the user data after clock domain conversion output by the asynchronous module through the AHB interface, and is used to convert the received local data and user data into APP data; A control module, used to convert the APP data output by the arbitration module into a timing signal of DDR particles; DDR particles, used to receive the timing signal output by the control module and store the data carried by the timing signal.

[0007] Optionally, in the described RISC-V based data storage system, the arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit, and a data selection unit; The data pre-judgment unit is used to determine whether the user data contains user instructions from RISC-V according to a preset detection rule, and generate a flag signal and a write enable signal; The channel state machine is used to switch to the write state according to the write enable signal, and in the write state, send the user data to the data conversion unit; The data conversion unit is used to convert the user data into APP data; The data selection unit is used to switch the connected channel according to the flag signal, so as to convey the user data or local data in the APP data format to the control module.

[0008] Optionally, in the described RISC-V based data storage system, the user data includes a clock signal, an address signal, a data signal, a burst signal, a data selection signal, a data preparation signal, a transmission status signal, a transmission bit width signal, and a data read / write signal; the preset detection rule includes: when the data selection signal is valid, the data read / write signal is a write signal, the transmission status signal is in the idle state, and the data preparation signal is valid, it is determined that the user module has generated user data to be cached.

[0009] Optionally, in the described RISC-V based data storage system, the channel state machine has a judgment state, a write state, and a read state, and the channel state machine defaults to the judgment state; in the judgment state, the channel state machine judges whether a write enable signal is received, and when it judges that a write enable signal is received, it switches the state to the write state.

[0010] Optionally, in the described RISC-V based data storage system, the data conversion unit includes a command parsing subunit, an address caching subunit, and a data caching subunit; The command parsing subunit is used to parse the user data to extract a write storage address signal, a write data signal, and a write control signal; it is also used to send the write storage address signal, the write data signal, and the write control signal to the data selection unit in the APP data format; The address caching subunit is used to cache the write storage address signal; The data caching subunit is used to cache the write data signal.

[0011] Optionally, in the described RISC-V based data storage system, the data pre-judgment unit is further used to generate a read enable signal and a read control signal; The channel state machine is further configured to switch to a read state according to a read enable signal, and in the read state, send a read control signal to the data conversion unit; The data conversion unit is further configured to receive an interface ready signal generated by the control module, and parse the read control signal and the interface ready signal to generate a read instruction; The data selection unit is further configured to send the read instruction to the control module to read corresponding data stored in the DDR particle; and is further configured to switch the connected channel according to a flag signal to transmit the read data to the data conversion unit; The data conversion unit is further configured to convert the data read by the data selection unit into AHB data, and output it to the user module through the channel state machine and the data prediction unit.

[0012] To solve the above technical problems, the present invention further provides a data storage method based on RISC-V, which is applied to the data storage system based on RISC-V described in any one of the above, and the data storage method includes: Judge whether a flag signal is generated; If a flag signal is generated, obtain user data generated by the user module according to a write enable signal, and convert the user data into APP data, otherwise, obtain local data generated by the local module; Convert the user data or local data in the APP data format into a timing signal of the DDR particle; The DDR particle receives the timing signal and stores the data carried by the timing signal.

[0013] Optionally, in the data storage method based on RISC-V, the data storage method further includes: If a flag signal is generated, parse the read control signal and the interface ready signal according to a read enable signal to generate a read instruction; Read corresponding data stored in the DDR particle according to the read instruction; Convert the read data into AHB data and output it to the user module.

[0014] Optionally, in the data storage method based on RISC-V, the data storage method further includes: By default, transmit local data generated by the local module to the DDR particle.

[0015] Optionally, in the data storage method based on RISC-V, the user data generated by the user module performs burst data transmission using a burst signal; the user data includes a write storage address signal and a write data signal; the method for converting the user data into APP data includes: After receiving the write enable signal, receive and cache the write storage address signal; After waiting for one clock cycle, receive the write data signal corresponding to the write storage address signal and cache it; wherein, after continuously obtaining all the data under the burst signal, splice all the data into a parallel data and cache the parallel data.

[0016] To solve the above technical problems, the present invention also provides an integrated circuit, including the RISC-V based data storage system described in any one of the above.

[0017] Optionally, in the integrated circuit, the integrated circuit is implemented based on FPGA.

[0018] The RISC-V based data storage system, method and integrated circuit provided by the present invention include: a local module for generating local data; a user module, which is a hardcore module of RISC-V, for generating user data; an asynchronous module for converting the clock domain of the user data to the clock domain of the local data; an arbitration module for receiving the local data generated by the local module through the APP interface, and also for receiving the user data after clock domain conversion output by the asynchronous module through the AHB interface, and for converting the received local data and user data into APP data; a control module for converting the APP data output by the arbitration module into the timing signal of the DDR particles; the DDR particles for receiving the timing signal output by the control module and storing the data carried by the timing signal. By using the DDR particles as the storage medium, using the AHB interface corresponding to the user module of RISC-V as the data transmission interface, and converting the AHB interface and the APP interface of the DDR protocol through the arbitration module, the high-speed and high-performance characteristics of DDR and AHB can be fully utilized, realizing the high-speed data interaction between RISC-V and DDR; at the same time, through the arbitration module, the original APP interface can be retained, thus being compatible with different data transmission methods, and solving the problem of how to achieve high-speed data storage based on the RISC-V microcontroller. Description of the Drawings

[0019] Figure 1 It is the structural block diagram of the RISC-V based data storage system provided in this embodiment; Figure 2 It is the structural schematic diagram of the arbitration module provided in this embodiment; Figure 3 It is the flowchart of the RISC-V based data storage method in the write direction provided in this embodiment; Figure 4 It is the flowchart of the RISC-V based data storage method in the read direction provided in this embodiment. Detailed Embodiments

[0020] The following further elaborates on the RISC-V based data storage system, method, and integrated circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses and sometimes use different scales.

[0021] It should be noted that the "first", "second", etc. in the description, claims, and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0022] To clearly illustrate the implementation scheme of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows: FPGA: Field Programmable Gate Array, field programmable gate array; DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, abbreviated as DDR; MC: Memory Controller, memory controller; PHY: Physical Layer, physical layer; FIFO: First Input First Output, first in first out; RAM: Random Access Memory, random access memory; CMD: Command, command; ARM processor: Advanced RISC Machine, a low-power and low-cost RISC microprocessor designed by Acorn Limited in the UK. The ARM processor itself is a 32-bit design, but also equipped with a 16-bit instruction set. Generally speaking, it can save up to 35% compared to equivalent 32-bit code while retaining all the advantages of a 32-bit system; RISC-V: RISC-V instruction set architecture, is an open instruction set architecture (ISA), based on the principles of Reduced Instruction Set Computing (RISC). As an open-source standard, RISC-V allows any individual or organization to freely use, modify, and extend it without paying patent fees. Its design goal is to provide a simple, scalable, and flexible instruction set suitable for a wide range of application fields, from microcontrollers to high-performance computing; AMBA: Advanced Micro-controller Bus Architecture, the advanced microcontroller bus architecture; AXI: Advanced eXtensible Interface, the advanced extensible interface; APB: Advanced Peripheral Bus, the advanced peripheral bus; AHB: Advanced High Performance Bus, the advanced high-performance bus; APP interface: Also known as API (Application Programming Interface), the application programming interface.

[0023] This embodiment provides a RISC-V-based data storage system, as Figure 1 shown, including: A local module, used to generate local data; A user module, which is a hardcore module of RISC-V and is used to generate user data; An asynchronous module, used to convert the clock domain of the user data to the clock domain of the local data; An arbitration module, used to receive the local data generated by the local module through the APP interface, and is also used to receive the user data after clock domain conversion output by the asynchronous module through the AHB interface, and is used to convert the received local data and user data into APP data; A control module, used to convert the APP data output by the arbitration module into the timing signal of the DDR particles; DDR particles, used to receive the timing signal output by the control module and store the data carried by the timing signal.

[0024] The RISC-V based data storage system provided in this embodiment can make full use of the high-speed and high-performance characteristics of DDR and AHB by using DDR particles as the storage medium, using the AHB interface corresponding to the user module of RISC-V as the data transmission interface, and converting the AHB interface and the APP interface of the DDR protocol through an arbitration module, thus realizing high-speed data interaction between RISC-V and DDR. At the same time, through the arbitration module, the original APP interface can be retained, so as to be compatible with different data transmission methods, and the problem of how to achieve high-speed data storage based on a RISC-V microcontroller is solved.

[0025] Specifically, in this embodiment, the local module adopts a data source generation module with a NATIVE interface, and the data format output by it is defined as the app name. In practical applications, the local module can be developed based on FPGA.

[0026] Moreover, in this embodiment, the user module is a hard core module of RISC-V. In practical applications, the user module can also be developed based on FPGA. Generally, RISC-V is implemented by using the register and wiring resources inside the FPGA, but this solution has a low frequency and a slow data transmission speed. Preferably, in this embodiment, the user module can be implemented by integrating a hard core RISC-V, so as to ensure that the core frequency and external interface frequency of RISC-V can reach 300 MHz, thereby effectively improving the data transmission efficiency.

[0027] In this embodiment, considering that the core frequency and external interface frequency of the user module are relatively high, an AHB module can be used as the data interaction interface, so as to effectively utilize the high bandwidth and data burst function of AHB, which is not only more suitable for the DDR storage interface, but also makes the resources used lower than those of the AXI interface.

[0028] In practical applications, since AHB adopts a burst data transmission mode and the data before the control module is parallel data, the characteristics of the AHB and APP buses can be utilized, and the burst data transmission of AHB can be used to form a group of DDR storage data, so as to realize efficient data transmission.

[0029] For example, when the bit width of the DDR particle is 16 and the control module adopts a clock ratio of 1:4 (4 data are transmitted in one clock rising edge), considering the double-edge sampling function of DDR, actually 8 data can be transmitted in one clock, that is, 128 bit. At this time, the AHB can be set to a data channel bit width of 16 bit, and the number of burst data at one time is 8. In this way, the bandwidths of the two different buses are completely matched, making the use efficiency the highest.

[0030] Also, in this embodiment, the asynchronous module can also be developed based on the FPGA. Specifically, the input and output interfaces of the asynchronous module both adopt AHB, and the asynchronous module uses a First-In-First-Out (FIFO) to perform clock domain conversion on the input and output data, so that the frequency of the user data is the same as that of the arbitration module, ensuring the reliability of the data arbitration result.

[0031] Also, in this embodiment, the control module can also be developed based on the FPGA, or can be directly implemented using the internal resources of the FPGA. For example, the control module can be a DDR physical layer (DDR PHY). The main function of the control module is to convert the APP data signal output by the arbitration module into the timing signal of the DDR chip.

[0032] Also, in this embodiment, the arbitration module is a key module for realizing the data channel switching between the local module and the user module and the interface conversion between the local data and the user data. Specifically, in this embodiment, as Figure 2 shown, the arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit, and a data selection unit. Also, the signals in the AHB write data direction of the user module include a clock signal HCLK, an address signal HADDR, a data signal HWDATA, a burst signal HBURST, a data selection signal HSEL, a data ready signal HREADY, a transfer status signal HTRANS, a transfer bit width signal HSIZE, and a data read / write signal HWRITE. Among them, the data read / write signal HWRITE is high level for writing and low level for reading.

[0033] Among them, the data pre-judgment unit is used to judge whether the user data contains user instructions from RISCV according to a preset detection rule, and generate a flag signal and a write enable signal.

[0034] Specifically, in this embodiment, the preset detection rule includes: when the data selection signal HSEL is valid, the data read / write signal HWRITE is a write signal (high level), the transfer status signal HTRANS is in an idle state, and the data ready signal HREADY is valid (high level), it is judged that the user module has generated user data to be cached, and a write enable signal wen is generated. Among them, both the data selection signal HSEL and the data read / write signal HWRITE being high level represent a write command, and the data ready signal HREADY being high level means that the storage end allows writing data. If the data ready signal HREADY is low level, it is necessary to wait for the storage space to be idle before continuing to write data. In practical applications, when generating the write enable signal wen, a write storage address signal waddr and a write data signal wdata will also be generated correspondingly.

[0035] Meanwhile, after the data prediction unit determines that the user module has generated user data to be cached, it also generates a flag signal flag, which is used to activate the data selection unit, enabling the data selection unit to give the channel priority to the data channel after the user module's AHB conversion.

[0036] Moreover, the channel state machine is used to switch to the write state according to the write enable signal, and in the write state, it sends the user data to the data conversion unit.

[0037] Specifically, user data such as the write enable signal wen, write storage address signal waddr, and write data signal wdata generated by the data prediction unit are input into the channel state machine, and the channel state machine then outputs user data such as the write storage address signal waddr and write data signal wdata to the data conversion unit.

[0038] In practical applications, the channel state machine has a judgment state, a write state, and a read state, and the channel state machine defaults to the judgment state. In the judgment state, the channel state machine determines whether it has received the write enable signal wen, and when it determines that it has received the write enable signal, it switches the state to the write state, thereby realizing the transmission of user data in the write direction. Similarly, when it determines that it has received the read enable signal ren, it switches the state to the read state, thereby reading the data in the data conversion unit to the data prediction unit in the read direction.

[0039] Moreover, the data conversion unit is used to convert user data into APP data.

[0040] Specifically, as Figure 2 shown, the data conversion unit includes a command parsing subunit, an address caching subunit, and a data caching subunit. Among them, the command parsing subunit is used to parse the user data to extract the write storage address signal, write data signal, and write control signal; it is also used to send the write storage address signal, write data signal, and write control signal to the data selection unit in the APP data format; the address caching subunit is used to cache the write storage address signal; and the data caching subunit is used to cache the write data signal.

[0041] In this embodiment, after the data conversion unit converts the AHB user data, it outputs an instruction signal cmd, an address signal addr, and a data signal data to the data selection unit. Among them, since AHB uses a method of delaying the read / write command and the address by one beat for burst data transmission, after the data conversion unit receives the user data, it is necessary to write the address information in the write storage address signal into the address cache sub-unit and wait for one beat, then obtain the corresponding write data signal. After continuously obtaining 8 data of the burst signal HBURST, the 8 groups of data are spliced into a parallel data with a length of 128 bits and written into the data cache sub-unit, realizing that the data bit widths of AHB and the DDR interface are the same and can be directly connected. The command parsing sub-unit sends the read / write instructions generated by the channel state machine to the data selection module after parsing. In this way, the complete connection between the AHB interface and the local APP interface is realized.

[0042] In addition, due to the read / write latency of DDR itself, it is impossible to obtain all the read / write data of the user at one time. In this embodiment, in the APP interface of the control module, there is also a signal app_ready indicating whether the data is idle. This signal has the same function as the HREADY signal of AHB and can be directly connected, thus realizing the interconnection of the read / write data idle information.

[0043] Moreover, the data selection unit is used to switch the connected channel according to the flag signal to deliver the user data or local data in the APP data format to the control module.

[0044] Specifically, when the flag signal flag is valid (high level), it indicates that the RISCV user module is ready to perform the read / write operation on the DDR. At this time, after the data selection unit waits for the previous instruction to be executed, it switches the channel to the AHB channel to perform the read / write of user data. If the flag signal flag is invalid (low level), it indicates that the read / write of user data stops. At this time, the data selection unit switches the data channel to the channel of the local data module.

[0045] The data storage system based on RISCV provided in this embodiment can not only write the user data of the user module into the DDR particles at high speed, but also read the data in the DDR particles out to the user module at high speed.

[0046] Specifically, the data prediction unit is further configured to generate a read enable signal and a read control signal; the channel state machine is further configured to switch to a read state according to the read enable signal, and in the read state, send the read control signal to the data conversion unit; the data conversion unit is further configured to receive the interface ready signal generated by the control module, and parse the read control signal and the interface ready signal to generate a read instruction; the data selection unit is further configured to send the read instruction to the control module to read the corresponding data stored in the DDR particles; and is further configured to switch the connected channel according to the flag signal to transmit the read data to the data conversion unit; the data conversion unit is further configured to convert the data read by the data selection unit into AHB data, and output it to the user module through the channel state machine and the data prediction unit.

[0047] The data storage system based on RISC-V provided in this embodiment uses the AHB interface as the DDR storage conversion interface. It not only uses fewer resources and has better performance, but also can utilize the backpressure function (HREADY) of the AHB to communicate with the app_ready signal of the local interface to implement the read / write waiting function and ensure the coherence of data transmission; it can also utilize the burst function of the AHB to perform burst storage of data in advance and then transmit it after stitching into a group of DDR data widths, thereby effectively utilizing the bit width of the entire transmission channel and improving the working bandwidth and efficiency.

[0048] The data storage system based on RISC-V provided in this embodiment uses an arbitration module that can adapt to external interfaces such as the RISC-V user module while retaining the original local direct control interface, realizing the switching of different interfaces, and thus being compatible with different data transmission methods.

[0049] This embodiment also provides a data storage method based on RISC-V, which is applied to the data storage system based on RISC-V as described above. As Figure 3 shown, the data storage method includes: S11, determine whether to generate a flag signal flag.

[0050] Specifically, in this embodiment, the data selection unit in the arbitration module determines whether the data prediction unit generates a flag signal flag.

[0051] S12, if the flag signal is generated, obtain the user data generated by the user module according to the write enable signal, and convert the user data into APP data; otherwise, obtain the local data generated by the local module.

[0052] During the write operation, when the flag signal flag is generated, it indicates that the user module needs to write data into the DDR particles at this time. Therefore, the user module will send the generated user data to the arbitration module. The data pre-judgment unit in the arbitration module generates a write enable signal wen according to the preset detection rules, and inputs user data such as the write storage address signal waddr and the write data signal wdata into the channel state machine. The channel state machine outputs the user data such as the write storage address signal waddr and the write data signal wdata to the data conversion unit again, and the data conversion unit completes the data conversion to obtain APP data. At this time, the APP data includes an instruction signal cmd, an address signal addr, and a data signal data.

[0053] Among them, since AHB uses the method of delaying the read / write command and the address by one clock cycle for burst data transmission, after receiving the write enable signal wen, it receives and caches the write storage address signal waddr; after waiting for one clock cycle, it receives the write data signal wdata corresponding to the write storage address signal and caches it. Among them, after continuously obtaining all the data under the burst signal HBURST, all the data is spliced into a parallel data, and the parallel data is cached.

[0054] If the flag signal flag is not generated, it indicates that the user module does not need to write data into the DDR particles at this time, and the default channel state is maintained at this time, that is, the local data generated by the local module is defaultly transmitted to the DDR particles.

[0055] S13, convert the user data or local data in the APP data format into the timing signal of the DDR particles.

[0056] Specifically, after the data conversion unit converts the AHB user data, it outputs the instruction signal cmd, the address signal addr, and the data signal data to the data selection unit. The data selection unit sends these signals to the control module through the APP interface, and the control module generates a timing signal according to these signals.

[0057] S14, the DDR particles receive the timing signal and store the data carried by the timing signal.

[0058] The above method is the data storage method when the user module performs a write operation on the DDR particles. Next, the data storage method when the user module performs a read operation on the DDR particles will be described. As Figure 4 shown, the data storage method further includes: S21, determine whether a flag signal is generated.

[0059] Specifically, in this embodiment, the data selection unit in the arbitration module determines whether the data pre-judgment unit generates the flag signal flag.

[0060] S22, if a flag signal is generated, the read control signal and the interface ready signal are parsed according to the read enable signal to generate a read instruction.

[0061] During the read operation, when the flag signal flag is generated, it indicates that the user module needs to read data from the DDR particle at this time. The user module in the sludge layer will send the corresponding read operation instruction to the arbitration module in the form of user data. The data pre-judgment unit in the arbitration module generates a read enable signal ren according to the preset detection rule, and inputs user data such as the read control signal and the interface ready signal to the channel state machine. The channel state machine outputs user data such as the read control signal and the interface ready signal to the data conversion unit again, and the data conversion unit completes the data conversion to obtain the APP data, that is, the read instruction. At this time, the APP data mainly includes an instruction signal cmd and an address signal addr.

[0062] If the flag signal flag is not generated, it indicates that the user module does not need to read data from the DDR particle at this time, and the default channel state is maintained, that is, the default local module reads data from the DDR particle.

[0063] S23, read the corresponding data stored in the DDR particle according to the read instruction.

[0064] Specifically, the data conversion unit outputs the read instruction to the data selection unit, and the data selection unit sends the read instruction to the control module through the APP interface. The control module reads the corresponding data from the DDR particle according to the read instruction.

[0065] S24, convert the read data into AHB data and output it to the user module.

[0066] Specifically, the control module sends the read data (APP data) to the data selection unit through the APP interface. The data selection unit further sends the read data data to the data conversion unit, and the data conversion unit converts the APP data again to obtain the AHB user data. Since the channel state machine receives the read enable signal ren, its state switches to the read state, so as to receive the AHB user data output by the data conversion unit and transmit the AHB user data to the data pre-judgment unit. Finally, the data pre-judgment unit outputs the AHB data to the user module.

[0067] The data storage method based on RISC-V provided in this embodiment uses the AHB interface as the DDR storage conversion interface, which not only consumes fewer resources and has better performance, but also can utilize the backpressure function (HREADY) of the AHB to communicate with the app_ready signal of the local interface to implement the read / write waiting function and ensure the coherence of data transmission. It can also utilize the burst function of the AHB to perform burst storage of data in advance and then transmit it after stitching into a group of DDR data widths, thereby effectively utilizing the bit width of the entire transmission channel and improving the working bandwidth and efficiency.

[0068] The data storage method based on RISC-V provided in this embodiment uses an arbitration module that can adapt to external interfaces such as RISC-V user modules while retaining the original local direct control interface, realizing the switching of different interfaces, thus being compatible with different data transmission methods, enabling both data writing and reading to adapt to different channels and interfaces, and achieving high-speed data storage and reading based on the RISC-V microcontroller.

[0069] Moreover, this embodiment also provides an integrated circuit including the RISC-V-based data storage system described above.

[0070] Specifically, in this embodiment, the integrated circuit is implemented based on an FPGA, that is, the local module, user module, asynchronous module, arbitration module, control module, and DDR particles can all be implemented based on the FPGA, thereby being able to utilize the internal resources of the FPGA to achieve a flexible design of the RISC-V-based data storage system.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. In addition, the different parts among the various embodiments can also be combined and used, and the present invention does not limit this.

[0072] The RISC-V based data storage system, method and integrated circuit provided by this embodiment include: a local module for generating local data; a user module, which is a hard core module of RISC-V, for generating user data; an asynchronous module for converting the clock domain of the user data to the clock domain of the local data; an arbitration module for receiving the local data generated by the local module through the APP interface, and also for receiving the user data after clock domain conversion output by the asynchronous module through the AHB interface, and for converting the received local data and user data into APP data; a control module for converting the APP data output by the arbitration module into the timing signals of the DDR particles; and the DDR particles for receiving the timing signals output by the control module and storing the data carried by the timing signals. By using the DDR particles as the storage medium, using the AHB interface corresponding to the user module of RISC-V as the data transmission interface, and converting the AHB interface and the APP interface of the DDR protocol through the arbitration module, the high-speed and high-performance characteristics of the DDR and AHB can be fully utilized, realizing the high-speed data interaction between RISC-V and DDR; at the same time, through the arbitration module, the original APP interface can be retained, thus being compatible with different data transmission methods, and solving the problem of how to achieve high-speed data storage based on the RISC-V microcontroller.

[0073] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A data storage system based on RISC-V, characterized in that, Including: A local module for generating local data; A user module, which is a hardcore module of RISCV, for generating user data; An asynchronous module for converting the clock domain of the user data to the clock domain of the local data; An arbitration module for receiving the local data generated by the local module through an APP interface, and also for receiving the user data after clock domain conversion output by the asynchronous module through an AHB interface, and for converting the received local data and user data into APP data; A control module for converting the APP data output by the arbitration module into a timing signal of a DDR particle; A DDR particle for receiving the timing signal output by the control module and storing the data carried by the timing signal.

2. The data storage system based on RISC-V according to claim 1, wherein The arbitration module includes a data pre-judgment unit, a channel state machine, a data conversion unit, and a data selection unit; The data pre-judgment unit is used to judge whether the user data contains user instructions from RISCV according to a preset detection rule, and generate a flag signal and a write enable signal; The channel state machine is used to switch to a write state according to the write enable signal, and in the write state, send the user data to the data conversion unit; The data conversion unit is used to convert the user data into APP data; The data selection unit is used to switch the connected channel according to the flag signal to convey the user data or local data in the APP data format to the control module.

3. The data storage system based on RISC-V according to claim 2, wherein The user data includes a clock signal, an address signal, a data signal, a burst signal, a data selection signal, a data preparation signal, a transmission status signal, a transmission bit width signal, and a data read / write signal; the preset detection rule includes: when the data selection signal is valid, the data read / write signal is a write signal, the transmission status signal is in an idle state, and the data preparation signal is valid, it is judged that the user module has generated user data to be cached.

4. The data storage system based on RISC-V according to claim 2, characterized in that The channel state machine has a judgment state, a write state, and a read state, and the channel state machine defaults to the judgment state; in the judgment state, the channel state machine judges whether a write enable signal is received, and when it judges that a write enable signal is received, it switches the state to the write state.

5. The data storage system based on RISC-V according to claim 2, wherein The data conversion unit includes a command parsing sub-unit, an address caching sub-unit, and a data caching sub-unit; The command parsing sub-unit is used to parse the user data to extract a write storage address signal, a write data signal, and a write control signal; and is also used to send the write storage address signal, the write data signal, and the write control signal to the data selection unit in the APP data format; The address caching sub-unit is used to cache the write storage address signal; The data caching sub-unit is used to cache the write data signal.

6. The RISCV-based data storage system according to claim 2, wherein, The data pre-judgment unit is also used to generate a read enable signal and a read control signal; The channel state machine is also used to switch to a read state according to the read enable signal, and in the read state, send the read control signal to the data conversion unit; The data conversion unit is also used to receive an interface preparation signal generated by the control module, and parse the read control signal and the interface preparation signal to generate a read instruction; The data selection unit is further configured to send a read instruction to the control module to read corresponding data stored in the DDR particles; and is further configured to switch the connected channel according to a flag signal to transmit the read data to the data conversion unit; The data conversion unit is further configured to convert the data read by the data selection unit into AHB data and output the AHB data to the user module through the channel state machine and the data prediction unit.

7. A data storage method based on RISC-V, applied to the RISC-V-based data storage system according to any one of claims 1 to 6, characterized in that, The data storage method includes: Determining whether a flag signal is generated; If a flag signal is generated, obtaining user data generated by the user module according to a write enable signal and converting the user data into APP data; otherwise, obtaining local data generated by the local module; Converting the user data or local data in APP data format into a timing signal of the DDR particles; The DDR particles receive the timing signal and store the data carried by the timing signal.

8. The RISCV-based data storage method according to claim 7, wherein The data storage method further includes: If a flag signal is generated, parsing a read control signal and an interface ready signal according to a read enable signal to generate a read instruction; Reading corresponding data stored in the DDR particles according to the read instruction; Converting the read data into AHB data and outputting the AHB data to the user module.

9. The data storage method based on RISC-V according to claim 7, characterized in that The data storage method further includes: By default, transmitting local data generated by the local module to the DDR particles.

10. The data storage method based on RISC-V according to claim 7, wherein The user data generated by the user module is subjected to burst data transmission by using a burst signal; the user data includes a write storage address signal and a write data signal; the method for converting the user data into APP data includes: After receiving the write enable signal, receiving and caching the write storage address signal; After waiting for one clock cycle, receiving the write data signal corresponding to the write storage address signal and caching the write data signal; wherein, after continuously obtaining all data under the burst signal, splicing all the data into a parallel data and caching the parallel data.

11. An integrated circuit, characterized in that, Including the RISC-V based data storage system according to any one of claims 1 to 6.

12. The integrated circuit according to claim 11, wherein The integrated circuit is implemented based on an FPGA.

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