Single event effect sensitivity evaluation method based on cross-scale coupling mechanism

Abstract

The invention provides a single event effect sensitivity evaluation method based on a cross-scale coupling mechanism, belongs to the technical field of electrical digital processing, and solves the problems that a traditional single event effect evaluation method cannot evaluate the function failure risk of an algorithm level and cannot position a key weight bit and a key network layer. The method comprises the following steps: acquiring key parameter information of a semiconductor device of an in-memory computing array, constructing a three-dimensional semiconductor device model, carrying out parameter calibration and inspection, and establishing a three-dimensional in-memory computing unit model; and establishing a single-particle fault injection model, performing single-particle effect fault injection transient simulation, mapping the single-particle multi-bit upset error pattern into the neural network to track a propagation path of an error in the neural network according to a mapping relation between the in-memory calculation array and the neural network, and identifying a key layer and a key weight bit in the neural network.

Description

Technical Field

[0001] The present invention relates to a method for evaluating the sensitivity of single event effects based on a cross-scale coupling mechanism, belonging to the technical field of electronic digital processing. Background Art

[0002] Deploying advanced artificial intelligence applications in space and integrating edge computing into tasks such as on-orbit distributed decision-making, on-board data analysis, and autonomous operation is of great significance for the disruptive development of national defense technology and space exploration. The in-memory computing architecture, due to its high energy efficiency characteristic of integrating memory and computing, is used to process space artificial intelligence tasks. However, high-energy particles in the space radiation environment can trigger single event effects (SEE), resulting in single event upsets (SEU) in the in-memory computing array. Under nanometer processes, the single particle charge sharing effect causes SEU in multiple adjacent cells in the in-memory computing array, leading to the situation of multiple bit upsets (MBU), which poses a severe challenge to the in-memory computing system that relies on fixed weight storage. Evaluating the sensitivity of single event effects in in-memory computing circuits can help guide the design of radiation hardening. The sensitivity of single event effects in in-memory computing circuits is not only related to its physical implementation but also affected by the characteristics of the neural network model. Traditional single event effect evaluation methods only statistically calculate the MBU occurrence rate through circuit-level simulation, without establishing the correlation between weight errors and neural network output deviations, unable to evaluate the functional failure risk at the algorithm level and unable to locate critical weight bits and critical network layers. Due to the isolated analysis of hardware and algorithms, lacking a systematic analysis of single particle multiple bit upsets and charge sharing effects in in-memory computing circuits in the space radiation environment, the cross-scale coupling mechanism between single event effects and neural network error propagation in the in-memory computing architecture has not been revealed. Therefore, there is an urgent need for a cross-scale evaluation method that integrates device physical simulation and neural network error propagation analysis to reveal the cascade failure mechanism of single event effects in the in-memory computing architecture and provide accurate guidance for the radiation hardening design of space artificial intelligence chips. Summary of the Invention

[0003] In order to solve the problem that traditional single event effect evaluation methods cannot evaluate the functional failure risk at the algorithm level and cannot locate critical weight bits and critical network layers, resulting in the inability to reveal the cross-scale coupling mechanism between single event effects and neural network error propagation in the in-memory computing architecture, the present invention further provides a method for evaluating the sensitivity of single event effects based on a cross-scale coupling mechanism.

[0004] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention includes the following steps:

[0005] Step 1: Obtain the specific structure, layout, and process information of the in-memory computing circuit to be evaluated, and determine the key parameter information of the semiconductor devices that make up the in-memory computing array;

[0006] Step 2: Based on the key parameter information of the semiconductor devices, use computer-aided design tools or other professional software to establish a three-dimensional semiconductor device model;

[0007] Step 3: According to the actual manufacturing process document of the in-memory computing circuit to be evaluated, calibrate the doping concentration parameters of the established three-dimensional semiconductor device model;

[0008] Step 4: Simulate the electrical characteristics of the three-dimensional device based on the calibrated three-dimensional semiconductor device model, and check the consistency of the electrical parameters between the simulation results and the SPICE model under the same size. If the electrical characteristics match, proceed to Step 5; if not, repeat Step 3 until the electrical characteristics match;

[0009] Step 5: Adopt the inspected three-dimensional semiconductor device model and combine it with the actual in-memory computing layout to establish a three-dimensional in-memory computing unit model;

[0010] Step 6: Establish a single-event fault injection model and define the parameters of the single-event fault injection model;

[0011] Step 7: Conduct single-event effect fault injection transient simulation to simulate the impact of single-event effects on the in-memory computing array;

[0012] Step 8: Determine whether all single-event incidence scenarios have been executed. If all have been executed, proceed to Step 9; if not, change the incidence state of the particle and re-execute Steps 6 - 7 until all single-event incidence scenarios have been executed;

[0013] Step 9: Under the condition that all single-event incidence scenarios have been executed, analyze the sensitive areas of the single-event charge sharing effect in the in-memory computing array, and summarize the distribution of single-event multiple-bit flip error patterns;

[0014] Step 10: According to the mapping relationship between the in-memory computing array and the neural network, map the single-event multiple-bit flip error patterns to the corresponding weight parameters of one layer in the neural network to complete the mapping from the hardware-level error to the software-level;

[0015] Step 11: According to the mapped single-event multiple-bit flip error patterns, inject faults into the weight parameters in the neural network by modifying the values of the neural network weight parameters to regenerate the weight parameter matrix;

[0016] Step 12: Use the mapping layer as the starting injection layer. Starting from the starting injection layer, trace the propagation path of the injected error in the neural network, record the impact of the error on the output of each layer of neurons and the final output result, and identify the key layers and key weight bits in the neural network to complete the sensitivity assessment of the circuit single-event effect.

[0017] Further, the key parameter information of the semiconductor device in Step 1 includes the type, shape, region, material, contact position, process constraints of the semiconductor device, as well as the impurity doping type and doping concentration of each region.

[0018] Further, the actual manufacturing process file of the in-memory computing circuit to be evaluated in Step 3 is a process design kit file using a specific process node, and the process design kit file contains files describing the details of the semiconductor process.

[0019] Further, the electrical parameter in Step 4 is the I-V characteristic curve under electrical characteristic simulation, and the I-V characteristic curve includes the output characteristic curve and the transfer characteristic curve.

[0020] Further, in Step 5, model the three-dimensional in-memory computing unit model according to the actual in-memory computing layout, and use the checked three-dimensional semiconductor device model to set the parameters of the three-dimensional in-memory computing unit model.

[0021] Further, the single-event fault injection model in Step 6 is a heavy ion model provided by CAD tools or other professional software, which is used to simulate the impact of single-event effects on semiconductor devices;

[0022] The parameters of the single-event fault injection model include the incident time, incident position, incident direction, incident depth, incident radius of the heavy particle, and the LET value of the particle, and different single-event radiation environments are simulated through the input parameters.

[0023] Further, in Step 9, the sensitive area is the area in the in-memory computing array where single-event upsets occur due to the impact of single-event effects, resulting in the destruction of stored data. The single-event multiple-bit flip error pattern distribution is used for the single-event multiple-bit flip error pattern distribution, where MBU refers to the simultaneous flipping of multiple physically adjacent bit cells caused by single-event effects.

[0024] Further, the mapping relationship between the in-memory computing array and the neural network in Step 10 is the corresponding relationship between the weights of the neural network stored in the in-memory computing array and the in-memory computing units.

[0025] The beneficial effects of the present invention are:

[0026] (1) The present invention breaks through the limitation of traditional single-event effect evaluation that only focuses on the hardware circuit level, and establishes a full-link analysis framework from device charge collection, multiple-bit flips in the storage array to error propagation in the neural network. Through the collaboration of physical simulation and algorithm-level fault injection, the cascade failure mechanism of single-event effect in the in-memory computing architecture is revealed, providing theoretical support for system-level reliability design.

[0027] (2) By identifying the critical layers and critical weight bits, the present invention provides important guidance for the radiation-hardening design of in-memory computing circuits. Designers can selectively strengthen based on this information, avoiding resource waste caused by blind redundancy, and facilitating the collaborative optimization of the radiation resistance and computing energy efficiency of in-memory computing circuits.

[0028] (3) The present invention studies the transmission characteristics of radiation errors between neural network layers, which helps to optimize the structure and parameter configuration of the neural network. By understanding the error propagation mechanism, a more robust neural network architecture can be designed, providing a key theoretical basis for designing fault-tolerant algorithms.

[0029] (4) The present invention provides a method for evaluating the radiation resistance of in-memory computing circuits at the design stage, which helps to reduce the costs of later testing and modification, and improve the design efficiency and reliability. By considering single-event effects at the design stage, expensive rework and redesign problems that may occur in the later stage of product development can be effectively avoided, reducing the product R & D time and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flowchart of a method for evaluating single-event effect sensitivity based on a cross-scale coupling mechanism provided by the present invention;

[0031] Figure 2 is a schematic structural diagram of a three-dimensional semiconductor device model established by the present invention;

[0032] Figure 3 is a schematic diagram of single-event fault injection provided by the present invention;

[0033] Figure 4 is a schematic diagram of MBU error patterns provided by the present invention;

[0034] Figure 5 is a schematic diagram of the mapping relationship between neural network weights and in-memory computing units provided by the present invention;

[0035] Figure 6 is a schematic diagram of error cross-layer propagation in a neural network provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] Combined with Figures 1-6 to illustrate this embodiment, as Figure 1As shown in the figure, the steps of a single-event effect sensitivity evaluation method based on a cross-scale coupling mechanism described in this embodiment include:

[0037] S1: Determine the key parameter information such as the type, geometric dimensions (such as channel width W and gate length L), physical arrangement, and process constraints of the semiconductor devices that make up the in-memory computing array according to the specific structure and layout information of the actual in-memory computing circuit, as well as information such as the process used.

[0038] S2: According to the type and geometric dimension information of the semiconductor devices, use semiconductor process files and device simulation software TCAD or other professional software to establish a three-dimensional semiconductor device model. The geometric information and metal contact information of each part of the semiconductor model are consistent with those provided in the PDK file, as Figure 2 shown.

[0039] The semiconductor process file is a process design kit (PDK) file using a specific process node, and this file contains files such as device model cards and design rule files (DRC) that describe the details of semiconductor processes.

[0040] S3: According to the process used, set the doping information of each part of the three-dimensional device, including substrate doping, well doping, source / drain doping, source / drain light doping, channel doping, Halo doping, etc. Simulate the electrical characteristics of the three-dimensional device to obtain the output characteristics (I ds -V ds ) and transfer characteristics (I ds -V gs ) curves.

[0041] S4: Compare the I-V curves of the TCAD simulation and the SPICE model, including the I-V curves of the output characteristics and transfer characteristics. If the electrical characteristics match, execute S5; if not, adjust the doping concentration and re-execute S3 until the electrical characteristics match.

[0042] S5: Adopt the established three-dimensional device model to establish a three-dimensional in-memory computing unit model according to the physical implementation of the actual in-memory computing array.

[0043] S6: Single-event fault injection is realized through the heavy ion model provided in the TCAD tool, as Figure 3 shown, to simulate the impact of single-event effects on the in-memory computing array.

[0044] Set parameters such as the incident time, incident position, incident depth, incident radius, incident angle of the particle, and the LET value of the particle to simulate different single-event radiation environments. The spatio-temporal distribution of charges around the ion track is modeled using a Gaussian radial profile.

[0045] S7: Conduct a transient simulation of single-event effect fault injection to analyze the charge collection process. When a radiation particle enters a semiconductor device, the reaction between the particle and the material generates a large number of carriers. Under the influence of factors such as concentration gradient and electric field, these carriers are collected by the nodes in the in-memory computing unit, affecting the storage state of the in-memory computing unit.

[0046] S8: Determine whether all expected cases have been executed. If all preset cases have been executed, then execute S9; if there are unexecuted preset cases (such as particles with a specific LET value incident on the in-memory computing unit at a specific angle), the incident state of the particle needs to be modified, the relevant parameters of the heavy ion model are updated, and S6 - S7 are executed until all expected cases have been executed.

[0047] S9: Summarize the single-event multiple-bit flip error pattern distribution under all preset particle incidence cases. Mark the bit cells that have flipped, as Figure 4 shown. Statistically analyze the MBU error patterns and their distributions in all cases.

[0048] S10: According to the mapping relationship between the neural network weights and the in-memory computing unit, map the statistically analyzed MBU error patterns to the corresponding weight parameters of a certain layer of the neural network.

[0049] The mapping relationship between the neural network weights and the in-memory computing unit is as Figure 5 shown. The mapping relationship refers to the correspondence between the weights of the neural network stored in the in-memory computing array and the in-memory computing unit, which involves how to store the weight parameters of the neural network into the in-memory computing array according to certain rules.

[0050] Through the above steps, the present invention completes the mapping from the hardware-level error to the software-level, overcoming the problem that traditional single-event effect evaluation only statistically analyzes the MBU incidence rate through circuit-level simulation, without establishing the correlation between weight errors and neural network output deviation, and being unable to evaluate the functional failure risk at the algorithm level. The present invention establishes a full-link analysis framework from device charge collection, multiple-bit flips in the storage array to neural network error propagation. Through the collaboration of physical simulation and algorithm-level fault injection, it reveals the cascading failure mechanism of single-event effects in the in-memory computing architecture, providing theoretical support for system-level reliability design.

[0051] S11: According to the information of the flipped cells marked in the MBU error pattern, inject faults into the weight parameters in the neural network by modifying the values of the neural network weight parameters, and regenerate the weight parameter matrix.

[0052] S12: Starting from the injected layer, trace as Figure 6The propagation path of the injected errors shown, records the changes in the outputs of neurons in each layer, as well as the changes in the final output result, and determines the critical layers and critical weight bits in the neural network. Errors at these positions will lead to a significant decline in performance. By identifying the critical layers and critical weight bits, the present invention provides important guidance for the radiation-hardening design of in-memory computing circuits. Designers can selectively reinforce based on this information, avoid waste of resources caused by blind redundancy, and facilitate the collaborative optimization of the radiation resistance and computing energy efficiency of in-memory computing circuits.

[0053] In summary, the present invention studies the transmission characteristics of radiation errors between neural network layers, which helps to optimize the structure and parameter configuration of the neural network. By understanding the error propagation mechanism, a more robust neural network architecture can be designed, providing a key theoretical basis for designing fault-tolerant algorithms. At the same time, the present invention can evaluate the radiation resistance of in-memory computing circuits at the design stage, which helps to reduce the costs of later testing and modification, and improve the design efficiency and reliability. By considering the single-event effect at the design stage, expensive rework and redesign problems that may occur in the later stage of product development can be effectively avoided, and the product R & D time and cost can be reduced.

[0054] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications into equivalent embodiments with equivalent changes by using the technical content disclosed above within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiments according to the technical essence of the present invention within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for evaluating the sensitivity of single event effects based on a cross-scale coupling mechanism, characterized in that The steps of the method for evaluating the sensitivity of single-event effects based on a cross-scale coupling mechanism include: Step 1: Obtain the specific structure, layout, and process information of the in-memory computing circuit to be evaluated, and determine the key parameter information of the semiconductor devices constituting the in-memory computing array; Step 2: Based on the key parameter information of the semiconductor devices, use computer-aided design tools or other professional software to establish a three-dimensional semiconductor device model; Step 3: Calibrate the doping concentration parameters of the established three-dimensional semiconductor device model according to the actual manufacturing process file of the in-memory computing circuit to be evaluated; Step 4: Simulate the electrical characteristics of the three-dimensional device based on the calibrated three-dimensional semiconductor device model, and check the consistency of the electrical parameters between the simulation results and the SPICE model under the same size. If the electrical characteristics match, proceed to Step 5; if not, repeat Step 3 until the electrical characteristics match; Step 5: Use the inspected three-dimensional semiconductor device model and combine it with the actual in-memory computing layout to establish a three-dimensional in-memory computing unit model; Step 6: Establish a single-event fault injection model and define the parameters of the single-event fault injection model; Step 7: Perform single-event effect fault injection transient simulation to simulate the impact of single-event effects on the in-memory computing array; Step 8: Determine whether all single-event incidence scenarios have been executed. If all have been executed, proceed to Step 9; if not, change the incidence state of the particle and re-execute Steps 6 - 7 until all single-event incidence scenarios have been executed; Step 9: Under the condition that all single-event incidence scenarios have been executed, analyze the sensitive regions of the single-event charge sharing effect in the in-memory computing array, and summarize the distribution of single-event multiple-bit flip error patterns; Step 10: According to the mapping relationship between the in-memory computing array and the neural network, map the single-event multiple-bit flip error patterns to the corresponding weight parameters of one layer in the neural network to complete the mapping from the hardware level error to the software level; Step 11: According to the mapped single-event multiple-bit flip error patterns, inject faults into the weight parameters in the neural network by modifying the values of the weight parameters in the neural network to regenerate the weight parameter matrix; Step 12: Take the mapped layer as the starting injection layer, start from the starting injection layer, trace the propagation path of the error in the neural network, record the impact of the error on the output of each layer of neurons and the final output result, and identify the key layers and key weight bits in the neural network to complete the sensitivity evaluation of the circuit single-event effects.

2. The single-event effect sensitivity evaluation method based on a cross-scale coupling mechanism according to claim 1, wherein The key parameter information of the semiconductor devices in Step 1 includes the type, shape, region, material, contact position, process constraints, and impurity doping type and doping concentration of each region of the semiconductor devices.

3. The single-event effect sensitivity evaluation method based on a cross-scale coupling mechanism according to claim 1, wherein The actual manufacturing process file of the in-memory computing circuit to be evaluated in Step 3 is a process design kit file using a specific process node, and the process design kit file contains files describing the details of the semiconductor process.

4. A single-particle effect sensitivity evaluation method based on a cross-scale coupling mechanism according to claim 1, characterized in that The electrical parameters in Step 4 are the I-V characteristic curves under electrical characteristic simulation, and the I-V characteristic curves include output characteristic curves and transfer characteristic curves.

5. The single-event effect sensitivity evaluation method based on a cross-scale coupling mechanism according to claim 1, wherein In step 5, a three-dimensional in-memory computing unit model is built according to the actual in-memory computing layout, and the parameters of the three-dimensional in-memory computing unit model are set using the checked three-dimensional semiconductor device model.

6. The single-event effect sensitivity evaluation method based on a cross-scale coupling mechanism according to claim 1, characterized in that In step 6, the single-event fault injection model is the heavy ion model provided by CAD tools or other professional software, which is used to simulate the impact of single-event effects on semiconductor devices; The parameters of the single-event fault injection model include the incident time, incident position, incident direction, incident depth, incident radius of the heavy particle, and the LET value of the particle, and different single-event radiation environments are simulated through the input parameters.

7. A method for evaluating the sensitivity of single event effects based on a cross-scale coupling mechanism according to claim 1, characterized in that In step 9, the sensitive area is the area in the in-memory computing array where single-event upsets occur due to the impact of single-event effects, resulting in the corruption of stored data. The single-event multiple-bit flip error pattern distribution is used for the single-event multiple-bit flip error pattern distribution, where MBU refers to the simultaneous flipping of multiple physically adjacent bit cells caused by single-event effects.

8. A method for evaluating the sensitivity of single event effects based on a cross-scale coupling mechanism according to claim 1, characterized in that In step 10, the mapping relationship between the in-memory computing array and the neural network is the correspondence between the weights of the neural network stored in the in-memory computing array and the in-memory computing units.

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