Driving method of display panel and electronic equipment

Abstract

The invention provides a driving method of a display panel and electronic equipment, and relates to the technical field of display driving. The driving method of the display panel comprises the steps that driving scanning is carried out on pixel circuit lines based on the image display periods so as to control the display panel to carry out picture display, and the bias pulse interval between the first bias sub-stage and the second bias sub-stage of at least one image display period is larger than the bias pulse interval between the first bias sub-stage and the second bias sub-stage of the first bias sub-stage and the second bias sub-stage of the second bias sub-stage. The time length of the bias pulse interval is different from the time length of the bias pulse interval of the other image display periods, so that by optimizing the time length, the re-etching problem when a low-brightness low-order picture is displayed in a set area of the display panel is solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and more specifically, to a driving method for a display panel and an electronic device. Background Art

[0002] The display panel includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. During the operation of the display panel, a driving transistor in the pixel circuit is controlled to provide a driving current to the light-emitting element to cause the light-emitting element to emit light, and a stable driving current needs to be provided to the light-emitting element to ensure a high display effect during the operation of the panel. However, the driving transistor in the pixel circuit will have a problem of threshold voltage drift after long-term operation, which affects the display effect. To solve this problem, currently, a biasing operation is proposed for the source and / or drain of the driving transistor to balance the change in the threshold voltage of the driving transistor, thereby improving the display effect of the display panel. However, with the demand for high-precision frequency conversion, multiple biasing operations need to be performed on the driving transistor within one image display cycle of the full-surface scanning of the display panel to ensure the biasing effect, which will cause a replication phenomenon in the display panel. Especially when a low-brightness and low-order picture is displayed in a set area of the display panel, a replicated low-brightness and low-order picture will appear in a fixed other area, thereby affecting the display effect of the display panel. Summary of the Invention

[0003] In view of this, this application provides a driving method for a display panel and an electronic device, effectively solving the technical problems existing in the prior art and improving the display effect of the display panel.

[0004] To achieve the above object, the technical solutions provided by this application are as follows:

[0005] A driving method for a display panel, the display panel includes M pixel circuit rows, each pixel circuit row includes a plurality of pixel circuits, each pixel circuit includes a light-emitting control module, an anode reset module, and a biasing module, the light-emitting control module is electrically connected to a light-emitting control signal line, and both the anode reset module and the biasing module are electrically connected to a biasing control signal line, where M is a positive integer greater than 1;

[0006] One image display cycle of the pixel circuit row includes at least two scanning frames, the at least two scanning frames include a data writing scanning frame and at least one holding scanning frame in sequence, and the at least one holding scanning frame includes a first biasing holding scanning frame to an Nth biasing holding scanning frame in sequence, where N is a positive integer;

[0007] The scanning frame includes a pre-stage and a light-emitting stage that are carried out in sequence. The pre-stage of writing data into the scanning frame includes a data-writing sub-stage, and the pre-stage of writing data into the scanning frame includes a first biasing sub-stage. The pre-stage of the i-th biasing holding scanning frame includes a second biasing sub-stage, where i is a positive integer not greater than N.

[0008] The light-emitting control signal line transmits an invalid level during the pre-stage, and the light-emitting control signal line transmits a valid level during the light-emitting stage. The biasing control signal line transmits a valid level during both the first biasing sub-stage and the second biasing sub-stage.

[0009] The driving method includes:

[0010] Based on the image display period, driving and scanning the pixel circuit rows to control the display panel to perform screen display. Among them, the bias pulse interval between the first biasing sub-stage and the second biasing sub-stage in at least one image display period is different from the duration of the bias pulse intervals in the remaining image display periods.

[0011] Based on the same inventive concept, the present application also provides an electronic device, which includes a display panel, and the display panel includes M pixel circuit rows;

[0012] And a driving circuit electrically connected to the pixel circuit rows, where the driving circuit is used to execute the driving method of the above-mentioned display panel.

[0013] Compared with the prior art, the technical solution provided by the present application has at least the following advantages:

[0014] The present application provides a driving method for a display panel and an electronic device. The driving method for the display panel includes: based on the image display period, driving and scanning the pixel circuit rows to control the display panel to perform screen display. Among them, the bias pulse interval between the first biasing sub-stage and the second biasing sub-stage in at least one image display period is different from the duration of the bias pulse intervals in the remaining image display periods, so as to optimize the duration and improve the reproduction problem when the display panel displays a low-brightness and low-order picture in a set area, and improve the display effect of the display panel. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0016] Figure 1 It is a schematic diagram of part of the circuit of a display panel;

[0017] Figure 2 It is a schematic diagram of a structure where a data line overlaps with the anode of a light-emitting element;

[0018] Figure 3 It is a circuit diagram of a pixel circuit;

[0019] Figure 4 It is a timing diagram of an image display cycle;

[0020] Figure 5 It is a driving timing diagram of an existing display panel;

[0021] Figure 6 It is a display effect diagram of an existing display panel;

[0022] Figure 7 It is a driving timing diagram of a display panel provided by an embodiment of the present application;

[0023] Figure 8 It is a display effect diagram of a display panel provided by an embodiment of the present application;

[0024] Figure 9 It is a driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0025] Figure 10 It is another driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0026] Figure 11 It is yet another driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0027] Figure 12 It is yet another driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0028] Figure 13 It is yet another driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0029] Figure 14 It is yet another driving timing diagram of a pixel circuit provided by an embodiment of the present application;

[0030] Figure 15 It is another timing diagram of an image display cycle;

[0031] Figure 16 It is another driving timing diagram of a display panel provided by an embodiment of the present application;

[0032] Figure 17 It is another display effect diagram of a display panel provided by an embodiment of the present application;

[0033] Figure 18 This is another driving timing diagram of the display panel provided by the embodiment of the present application;

[0034] Figure 19 This is a schematic structural diagram of an electronic device provided by the embodiment of the present application;

[0035] Figure 20 This is a schematic structural diagram of another electronic device provided by the embodiment of the present application.

[0036] Reference numerals:

[0037] 100 - Display panel; 10 - Pixel circuit; 11 - Driving module; 12 - Data writing module; 13 - Light emission control module; 14 - Anode reset module; 15 - Threshold compensation module; 16 - Initial reset module; 17 - Bias module; 20 - Light emitting element; 21 - Anode; 30 - Data line; 40 - Driving circuit; 200 - Control main board; 1000 - Electronic device; X - First direction; Y - Second direction; Z1 - Data writing scan frame; Z21, Z22, Z23 - Holding scan frame; Z3 - Bias holding scan frame; M1 - Pre-stage; M2 - Light emission stage; M11 - Pre-bias sub-stage before reset; M12 - Reset sub-stage; M13 - Data writing sub-stage; M14 - Post-data writing bias sub-stage; M15 - Second bias sub-stage; Cst - Storage capacitor; Vdata - Data voltage; DVH - Bias voltage; Vref1 - Initial reset voltage; Vref2 - Anode reset voltage; PVDD - Power supply voltage; PVEE - Cathode voltage; Emit - Light emission control signal line; S1 - Reset control signal line; S2 - Data writing control signal line; SPX - Bias control signal line; T1 - First light emission control transistor; T2 - Data writing transistor; T3 - Driving transistor; T4 - Threshold compensation transistor; T5 - Initial reset transistor; T6 - Second light emission control transistor; T7 - Anode reset transistor; T8 - Bias transistor; A1 - Set area; A1' - Replica area; b1, b2, b3, b4, b5 - Bias pulse intervals; C - Repeated display period; Ph - Porch stage; Y3, Y31, Y32 - Brightness stripe areas; FPC - Flexible printed circuit. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0039] As described in the background art, a display panel includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. During the operation of the display panel, a driving transistor in the pixel circuit is controlled to provide a driving current to the light-emitting element so that the light-emitting element emits light, and a stable driving current needs to be provided to the light-emitting element to ensure a high display effect during the operation of the panel. However, the driving transistor in the pixel circuit will have a problem of threshold voltage drift after long-term operation, which affects the display effect. To solve this problem, currently, a biasing operation is proposed for the source and / or drain of the driving transistor to balance the change in the threshold voltage of the driving transistor, thereby improving the display effect of the display panel. However, with the demand for high-precision frequency conversion, during an image display cycle of full-surface scanning of the display panel, the driving transistor needs to be biased multiple times to ensure the biasing effect, which will cause a replication phenomenon in the display panel. Especially when a low-brightness and low-order image is displayed in a set area of the display panel, a replicated low-brightness and low-order image will appear in a fixed other area, thereby affecting the display effect of the display panel.

[0040] As Figure 1 shown in the partial circuit schematic diagram of a display panel, the display panel 100 includes a pixel circuit array. The pixel circuit array includes M pixel circuit rows, where the pixel circuit rows are arranged along the second direction Y, and M is a positive integer greater than 1; each pixel circuit row includes a plurality of pixel circuits 10, and all the pixel circuits 10 in the pixel circuit row are arranged along the first direction X. Each pixel circuit 10 is electrically connected to at least one light-emitting element 20, and the pixel circuit 10 is used to provide a driving current to the light-emitting element 20 to drive the light-emitting element 20 to emit light. Generally, the light-emitting element 20 can be an organic light-emitting diode, and the organic light-emitting diode includes an anode 21, a light-emitting layer, and a cathode stacked in the direction perpendicular to the plane of the display panel 100. In addition, the display panel 100 further includes a plurality of data lines 30 extending along the second direction Y, and one data line 30 is electrically connected to at least some of the pixel circuits 10 in the same column of pixel circuits 10. Due to the limited wiring space of the display panel 100, on the extending line of the data line 30, the data line 30 also has an overlapping area with the anodes of at least some of the light-emitting elements 20 in the direction perpendicular to the plane of the display panel 100, specifically as Figure 2 shown in the partial structural layout diagram of the overlapping portion of the data line 30 and the anode 21 of the light-emitting element 20.

[0041] Continue to refer to Figure 1, during the operation of the display panel 100, it is necessary to scan M pixel circuit rows row by row. The first scanning method can be to scan row by row in the direction from the first pixel circuit row to the Mth pixel circuit row; the second scanning method can be to scan row by row in the direction from the Mth pixel circuit row to the first pixel circuit row; the third scanning method can be to first scan row by row in the direction from the first pixel circuit row to the Mth pixel circuit row, and then scan row by row in the direction from the Mth pixel circuit row to the first pixel circuit row; the fourth scanning method can be to first scan row by row in the direction from the Mth pixel circuit row to the first pixel circuit row, and then scan row by row in the direction from the first pixel circuit row to the Mth pixel circuit row; the fifth scanning method can be a combination of at least two of the above four row-by-row scanning methods, that is, during different time periods when the display panel 100 is operating, one of the above four row-by-row scanning methods is used to scan the M pixel circuit rows row by row at any time period. At the same time, during the scanning of the current pixel circuit row, the data line 30 transmits the data voltage Vdata of the required display image to the pixel circuit 10 in this pixel circuit row, so that the pixel circuit 10 outputs a corresponding driving current to the light-emitting element 20, and finally drives the light-emitting element 20 to emit light.

[0042] For the scanning of a single pixel circuit row, the scanning of the pixel circuit row needs to be driven and scanned according to the image display cycle; that is, the scanning of the pixel circuit 10 needs to be driven and scanned according to the image display cycle. As Figure 4 shown in the timing diagram of the image display cycle, an image display cycle includes at least two scanning frames, and each scanning frame includes a pre-stage M1 and a light-emitting stage M2 that are sequentially performed in time order. All scanning frames include a data writing scanning frame Z1 and at least one holding scanning frame that are sequentially performed in time order. The data writing scanning frame Z1 includes a data writing sub-stage M13, and in the data writing sub-stage M13, the data line 30 needs to provide the data voltage Vdata to the pixel circuit 10; while in the holding frame scanning frame, the pixel circuit 10 does not need to be connected to the data voltage Vdata again, but the pixel circuit 10 in the holding frame maintains the data voltage Vdata connected during the data writing scanning frame until a new data voltage Vdata transmitted by the data line 30 is connected in the next data writing scanning frame Z1. Continuing as Figure 4Schematic illustration of an image display period, which includes a data writing scan frame Z1 and three holding scan frames sequentially performed in chronological order. The three holding scan frames are, in chronological order, holding scan frame Z21, holding scan frame Z22, and holding scan frame Z23. The data writing scan frame Z1 includes a data writing sub-stage M13, and in the data writing sub-stage M13, the pixel circuit 10 needs to access the data voltage Vdata. In the holding scan frames Z21, Z22, and Z23, the pixel circuit 10 maintains the data voltage Vdata accessed during the data writing scan frame Z1.

[0043] With the demand for high-precision variable-frequency driving, during an image display period of a full-surface scan of the display panel 100, the driving transistor T3 in the pixel circuit 10 needs to be biased multiple times to ensure the biasing effect, thereby improving the display effect of the display panel 100. That is to say, multiple biasing sub-stages need to be set within an image display period. In the biasing sub-stage, the driving transistor T3 needs to be biased to improve the problem of threshold voltage drift of the driving transistor T3 after long-term operation. Generally, the number of biasing sub-stages in an image display period needs to be set to at least twice that of the data writing sub-stage M13. For example, when the frequency of the control signal corresponding to the data writing sub-stage M13 is 120 Hz, the frequency of the control signal of the biasing sub-stage can be 240 Hz, 360 Hz, 480 Hz, etc. For the convenience of describing the technical solution, hereinafter, the frequency of the control signal corresponding to the data writing sub-stage M13 is 120 Hz, and the frequency of the control signal of the biasing sub-stage is 240 Hz as an example, that is, the number of biasing sub-stages in an image display period is twice that of the data writing sub-stage M13, will be used for illustration.

[0044] To more clearly describe the working process of the pixel circuit 10 during the image display period, the following combines Figure 3A description is given of a specific circuit diagram of a pixel circuit 10 as shown. The pixel circuit 10 includes a driving module 11, a data writing module 12, a light emitting control module 13, an anode reset module 14, a threshold compensation module 15, an initial reset module 16, a bias module 17, and a storage capacitor Cst. The driving module 11 is configured to generate a driving current for driving the light emitting element 20 to emit light during the light emitting stage M2. The data writing module 12 is configured to transmit a data voltage Vdata to the driving module 11 during the data writing sub-stage M13. The light emitting control module 13 is configured to transmit the driving current to the light emitting element 20 during the light emitting stage M2. The anode reset module 14 is configured to transmit an anode reset voltage Vref2 to the anode 21 of the light emitting element 20 for resetting during the bias sub-stage. The threshold compensation module 15 is configured to capture the threshold voltage of the driving transistor T3 and store it in the storage capacitor Cst during the data writing sub-stage M13. The initial reset module 16 is configured to transmit an initial reset voltage Vref1 to the gate of the driving transistor T3 for resetting during the reset sub-stage M12. The bias module 17 is configured to transmit a bias voltage DVH to the driving transistor T3 for bias adjustment during the bias sub-stage.

[0045] Continue as Figure 3As shown, the driving module 11 includes a driving transistor T3, the data writing module 12 includes a data writing transistor T2, the light emission control module 13 includes a first light emission control transistor T1 and a second light emission control transistor T6, the anode reset module 14 includes an anode reset transistor T7, the threshold compensation module 15 includes a threshold compensation transistor T4, the initial reset module 16 includes an initial reset transistor T5, and the bias module 17 includes a bias transistor T8. The first end of the first light emission control transistor T1 is connected to the power supply voltage PVDD, the first end of the data writing transistor T2 is electrically connected to the data line 30 to access the data voltage Vdata, the first end of the bias transistor T8 is connected to the bias voltage DVH, the second ends of the first light emission control transistor T1, the data writing transistor T2, and the bias transistor T8 are all electrically connected to the first end of the driving transistor T3, the gate of the first light emission control transistor T1 is electrically connected to the light emission control signal line Emit, the gate of the data writing transistor T2 is electrically connected to the data writing control signal line S2, and the gate of the bias transistor T8 is electrically connected to the bias control signal line SPX. The first end of the initial reset transistor T5 is connected to the initial reset voltage Vref1, the first end of the threshold compensation transistor T4 is electrically connected to the second end of the driving transistor T3, the second ends of the initial reset transistor T5 and the threshold compensation transistor T4 are both electrically connected to the gate of the driving transistor T3, the gate of the initial reset transistor T5 is electrically connected to the reset control signal line S1, and the gate of the threshold compensation transistor T4 is electrically connected to the data writing control signal line S2. The first end of the second light emission control transistor T6 is electrically connected to the second end of the driving transistor T3, the first end of the anode reset transistor T7 is connected to the anode reset voltage Vref2, the second ends of the second light emission control transistor T6 and the anode reset transistor T7 are both electrically connected to the anode 21 of the light emitting element 20, the gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line Emit, the gate of the anode reset transistor T7 is electrically connected to the bias control signal line SPX, the cathode of the light emitting element 20 is connected to the cathode voltage PVEE, and the first plate of the storage capacitor Cst is connected to the power supply voltage PVDD, and the second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3.

[0046] It should be noted that the pixel circuit 10 is not limited to Figure 3The circuit structure shown may also be a variation of other circuit components and connections; for example, one variation may be that the bias transistor T8 in the pixel circuit 10 can be electrically connected to the second end of the driving transistor T3, and no specific limitation is imposed thereon. The first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initial reset transistor T5, the second light-emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8 can be N-type transistors or P-type transistors, and no specific limitation is imposed thereon. To reduce the influence of leakage current, the threshold compensation transistor T4 and the initial reset transistor T5 can be double-gate transistors. Combining Figure 3 and Figure 4 , the working process of one image display cycle of the pixel circuit 10 will be described below with the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initial reset transistor T5, the second light-emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8 all being P-type transistors. The image display cycle includes a data writing scan frame Z1, a holding scan frame Z21, a holding scan frame Z22, and a holding scan frame Z23 that are sequentially performed in chronological order. The data writing scan frame Z1 includes a first bias sub-phase (where the pre-reset bias sub-phase M11 and the post-data writing bias sub-phase M14 are collectively referred to as the first bias sub-phase), and the holding scan frame Z22 (the holding scan frame Z22 can be defined as the bias holding scan frame Z3) includes a second bias sub-phase M15. The data writing scan frame Z1 includes a pre-stage M1 and a light-emitting stage M2 that are sequentially performed in chronological order. The pre-stage M1 of the data writing scan frame Z1 includes a pre-reset bias sub-phase M11, a reset sub-phase M12, a data writing sub-phase M13, and a post-data writing bias sub-phase M14 that are sequentially performed in chronological order, where:

[0047] In the pre-reset bias sub-phase M11, the bias control signal line SPX transmits a low-level effective level, controlling the anode reset transistor T7 and the bias transistor T8 to conduct. The anode reset transistor T7 transmits the anode reset voltage Vref2 to the anode 21 of the light-emitting element 20 for reset, and the bias transistor T8 transmits the bias voltage DVH to the first end of the driving transistor T3 for bias adjustment.

[0048] In the reset sub-phase M12, the reset control signal line S1 transmits a low-level effective level, thereby controlling the initial reset transistor T5 to conduct. The initial reset transistor T5 transmits the initial reset voltage Vref1 to the gate of the driving transistor T3 for reset.

[0049] During the data writing sub-phase M13, the data writing control signal line S2 transmits an active low level, controlling the data writing transistor T2 and the threshold compensation transistor T4 to conduct. The data writing transistor T2 transmits the data voltage Vdata to the first end of the driving transistor T3, and the data voltage Vdata is transmitted to the gate of the driving transistor T3 through the driving transistor T3 and the threshold compensation transistor T4. At the same time, the threshold voltage of the driving transistor T3 is captured and stored in the storage capacitor Cst.

[0050] During the post-data writing bias sub-phase M14, the bias control signal line SPX transmits an active low level, controlling the anode reset transistor T7 and the bias transistor T8 to conduct. The anode reset transistor T7 transmits the anode reset voltage Vref2 to the anode 21 of the light-emitting element 20 for reset, and the bias transistor T8 transmits the bias voltage DVH to the first end of the driving transistor T3 for bias adjustment. It should be noted that the data writing scan frame Z1 may only include the pre-reset bias sub-phase M11. In this case, the pre-reset bias sub-phase M11 is the first bias sub-phase of the data writing scan frame Z1; or the data writing scan frame Z1 may only include the post-data writing bias sub-phase M14. In this case, the post-data writing bias sub-phase M14 is the first bias sub-phase of the data writing scan frame Z1; or the data writing scan frame Z1 may include both the pre-reset bias sub-phase M11 and the post-data writing bias sub-phase M14. In this case, the combination of the pre-reset bias sub-phase M11 and the post-data writing bias sub-phase M14 is called the first bias sub-phase of the data writing scan frame Z1, denoted as a bias sub-phase in the image display cycle.

[0051] Finally, during the light-emitting phase M2, the light-emitting control signal line Emit transmits an active low level, controlling the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to conduct. The first light-emitting control transistor T1, the driving transistor T3, and the second light-emitting control transistor T6 form a path from the power supply voltage PVDD to the cathode voltage PVEE. The driving transistor T3 generates a driving current with a value of Id = (PVDD - Vdata) 2 to drive the light-emitting element 20 to emit light.

[0052] After completing the driving of the data writing scan frame Z1 of the pixel circuit 10, the driving of the pixel circuit 10 enters the holding scan frame Z21. During the pre-stage M1 of the holding scan frame Z21, the reset control signal line S1, the data writing control signal line S2, the bias control signal line SPX, and the light emission control signal line Emit all transmit invalid high-level voltages. At this time, no new data voltage Vdata is written into the pixel circuit 10; until during the light emission stage M2 of the holding scan frame Z21, the light emission control signal line Emit transmits a valid low-level voltage, and the first light emission control transistor T1, the driving transistor T3, and the second light emission control transistor T6 form a path from the power supply voltage PVDD to the cathode voltage PVEE again, and the driving transistor T3 generates a driving current with a value of Id = (PVDD - Vdata) 2 to drive the light-emitting element 20 to emit light. In the driving current formula, the data voltage Vdata remains the data voltage Vdata accessed in the data writing scan frame Z1.

[0053] After completing the driving of the holding scan frame Z21 of the pixel circuit 10, the driving of the pixel circuit 10 enters the holding scan frame Z22, where the holding scan frame Z22 is the bias holding scan frame Z3. During the pre-stage M1 of the bias holding scan frame Z3, the bias control signal line SPX transmits a valid low-level voltage during a set period, thereby completing the bias adjustment of the driving transistor T3 and improving the characteristic offset problem of the driving transistor T3 during long-term operation; then during the light emission stage of the bias holding scan frame Z3, the light emission control signal line Emit transmits a valid low-level voltage, and the first light emission control transistor T1, the driving transistor T3, and the second light emission control transistor T6 form a path from the power supply voltage PVDD to the cathode voltage PVEE again, and the driving transistor T3 generates a driving current with a value of Id = (PVDD - Vdata) 2 to drive the light-emitting element 20 to emit light. In the driving current formula, the data voltage Vdata remains the data voltage Vdata accessed in the data writing scan frame Z1.

[0054] After driving the hold scan frame Z22 of the pixel circuit 10 is completed, the driving of the pixel circuit 10 enters the hold scan frame Z23. The driving of the hold scan frame Z23 is the same as that of the hold scan frame Z21. At the pre-stage M1 of the hold scan frame Z23, the reset control signal line S1, the data write control signal line S2, the bias control signal line SPX, and the emission control signal line Emit all transmit the invalid high level. At this time, no new data voltage Vdata is written into the pixel circuit 10; until at the emission stage M2 of the hold scan frame Z23, the emission control signal line Emit transmits the valid low level, and the first emission control transistor T1, the driving transistor T3, and the second emission control transistor T6 form a path from the power supply voltage PVDD to the cathode voltage PVEE again, and the driving transistor T3 generates a drive current with a value of Id = (PVDD - Vdata) 2 to drive the light-emitting element 20 to emit light. In the drive current formula, the data voltage Vdata is maintained as the data voltage Vdata accessed by the data write scan frame Z1, thus completing the driving process of one image display cycle of the pixel circuit 10.

[0055] When scanning M pixel circuit rows row by row, the image display cycles of the previously scanned pixel circuit row and the subsequently scanned pixel circuit row differ by a pre-stage. That is to say, when the pre-stage M1 of the data write scan frame Z1 of the previously scanned pixel circuit row is at the end of the stage, the pre-stage M1 of the data write scan frame Z1 of the subsequently scanned pixel circuit row is at the start of the stage. Combining Figure 5 with the drive timing diagram of the display panel shown in Figure 6 and the display effect diagram of the display panel shown in 2According to the formula, the data voltage A1-Vdata transmitted by the data line 30 electrically connected to the pixel circuit 10 corresponding to the set area A1 is a voltage with a higher value. At the same time, according to Figure 2 it is known that the data line 30 corresponding to the set area A1 overlaps with the anodes 21 of some light-emitting elements 20 corresponding to the replicated area A1'. Due to the coupling effect, the reset of the anodes 21 of some light-emitting elements 20 corresponding to the replicated area A1' is incomplete, resulting in a lower brightness of the light-emitting elements 20 corresponding to the replicated area A1' during the light-emitting stage M2, and causing the replicated area A1' to replicate the low gray-scale and low-brightness image of the set area A1, ultimately affecting the display effect of the display panel 100. Specifically, as Figure 5 shown by the schematic drive currents A1'-I at stages M31 and M32 corresponding to the replicated area A1' Anode decrease in value, and the display brightness at the replicated area A1' decreases. It should be noted that A1-Vdata is the data voltage Vdata transmitted by the corresponding data line 30 in the set area A1, A1-Emit is the timing of the light-emitting control signal line Emit connected to the pixel circuit 10 in the set area A1, A1-SPX is the timing of the bias control signal line SPX connected to the pixel circuit 10 in the set area A1, and A1-I Anode is the drive current generated by the pixel circuit 10 in the set area A1, A1'-Emit is the timing of the light-emitting control signal line Emit connected to the pixel circuit 10 in the replicated area A1', A1'-SPX is the timing of the bias control signal line SPX connected to the pixel circuit 10 in the replicated area A1', and A1'-I Anode is the drive current generated by the pixel circuit 10 in the replicated area A1'.

[0056] Based on this, the embodiments of the present application provide a driving method for a display panel 100 and an electronic device, effectively solving the technical problems existing in the prior art and improving the display effect of the display panel 100. The circuit of the display panel 100, as well as the circuit diagram and drive timing of the pixel circuit 10, can be combined with Figures 1 to 4As shown. Among them, the display panel 100 includes M pixel circuit rows, the pixel circuit rows include a plurality of pixel circuits 10, the pixel circuit 10 includes a light emission control module 13, an anode reset module 14 and a bias module 17, the light emission control module 13 is electrically connected to a light emission control signal line Emit, and both the anode reset module 14 and the bias module 17 are electrically connected to a bias control signal line SPX, and M is a positive integer greater than 1. One image display cycle of the pixel circuit row includes at least two scan frames, the at least two scan frames include a data writing scan frame Z1 and at least one holding scan frame in sequence, and the at least one holding scan frame includes a first bias holding scan frame to an Nth bias holding scan frame in sequence, and N is a positive integer. The scan frame includes a pre-stage M1 and a light emission stage M2 in sequence, the pre-stage M1 of the data writing scan frame Z1 includes a data writing sub-stage M13, and the pre-stage M1 of the data writing scan frame Z1 includes a first bias sub-stage (where the first bias sub-stage can be a combination of a pre-reset bias sub-stage M11 and a post-data writing bias sub-stage M14), and the pre-stage M1 of the ith bias holding scan frame includes a second bias sub-stage M15, and i is a positive integer not greater than N. The light emission control signal line Emit transmits an invalid level in the pre-stage M1, the light emission control signal line Emit transmits a valid level in the light emission stage M2, and the bias control signal line SPX transmits a valid level in both the first bias sub-stage and the second bias sub-stage M15. Based on the above circuit structure and image display cycle of the display panel 100, the driving method provided by the embodiments of the present application includes:

[0057] Drive and scan the pixel circuit rows based on the image display period to control the display panel 100 to perform screen display. Among them, the bias pulse interval between the first bias sub-phase and the second bias sub-phase M15 in at least one of the image display periods is different from the duration of the bias pulse intervals in the remaining image display periods. The bias pulse is the time when the bias signal line SPX transmits an effective level, and the bias pulse interval is the time interval between the effective level of the bias control signal line SPX in the first bias sub-phase and the effective level of the bias control signal line SPX in the second bias sub-phase M15. Among them, when the first bias sub-phase is a combination of the pre-reset bias sub-phase M11 and the post-data-write bias sub-phase M14, the bias pulse interval can be the time interval between the start time of the second bias sub-phase M15 and the end time of the pre-reset bias sub-phase M11; or, the bias pulse interval can be the time interval between the start time of the second bias sub-phase M15 and the end time of the post-data-write bias sub-phase M14, and the present application does not make specific limitations on this. For the convenience of description, the bias pulse intervals described below are all illustrated by the time interval between the start time of the second bias sub-phase M15 and the end time of the post-data-write bias sub-phase M14.

[0058] Combined with Figure 7 the drive timing diagram of the display panel provided by the embodiment of the present application shown in the figure and Figure 8 the display effect diagram of the display panel provided by the embodiment of the present application shown in the figure, the bias pulse interval b1 between the first bias sub-phase and the second bias sub-phase M15 in at least one of the image display periods provided by the embodiment of the present application is different from the duration of the bias pulse interval b2 in the remaining image display periods, thereby disrupting the timing with a fixed duration of the bias pulse intervals in all image display periods, that is, disrupting the time interval between the second bias sub-phase M15 and the data write sub-phase M13 in all image display periods. By optimizing the duration difference between different bias pulse intervals, it is possible to change the overlapping situation in time between the data write sub-phase M13 of the pixel circuit 10 scanned first and the second bias sub-phase M15 of the pixel circuit 10 scanned later, that is, it is possible to change the overlapping situation in time between the data write sub-phase M13 in the set area A1 and the second bias sub-phase M15 in the replicated area A1', so that the overlapping time between the second bias sub-phase M15 in the replicated area A1' and the stage where the data voltage A1-Vdata is transmitted on the corresponding data line 30 in the set area A1 is reduced, and even there is no overlap in timing, thereby improving the replication problem in the replicated area A1' when the set area A1 of the display panel 100 displays a low-brightness and low-order picture, and improving the display effect of the display panel 100. Compare Figure 5 and Figure 7 , Figure 7The driving current A1'-I at stages M31 and M32 corresponding to the schematic reproduction area A1' Anode has a value higher than Figure 5 the driving current A1'-I at stages M31 and M32 corresponding to the reproduction area A1' in Anode such that as Figure 8 schematically shown, the reproduction area A1' no longer reproduces the low-brightness and low-order images displayed in the set area A1, but maintains its normal display brightness, improving the display effect of the display panel 100.

[0059] It can be seen that the more the number of image display cycles with different durations of the bias pulse intervals is designed, the greater the impact on improving the overlap situation in time between the data writing sub-stage M13 at the set area A1 and the second bias sub-stage M15 at the reproduction area A1'. Therefore, in some embodiments, as Figure 9 shown in the driving timing diagram of the pixel circuit 10, the embodiments of the present application can use at least two consecutive said image display cycles as a repeated display cycle C. Any one image display cycle includes a data writing scan frame Z1, a holding scan frame Z21, a bias holding scan frame Z3, and a holding scan frame Z23, and two consecutive image display cycles form a repeated display cycle C. At this time, in the driving method of the display panel 100 provided by the embodiments of the present application, driving and scanning the pixel circuit rows based on the image display cycle includes: driving and scanning the pixel circuit rows based on the repeated display cycle, wherein, in the repeated display cycle C, the bias pulse interval b1 of at least one of the image display cycles is different in duration from the bias pulse interval b2 of the remaining image display cycles. Thus, during the operation of the display panel 100, the number of image display cycles with different durations of the bias pulse interval and the bias pulse intervals of the remaining image display cycles is increased, so as to further improve the reproduction problem in the reproduction area A1' when the set area A1 of the display panel 100 displays low-brightness and low-order images, and further improve the display effect of the display panel 100. Considering that the more the number of image display cycles with different durations of the bias pulse intervals is designed, the greater the design difficulty of the relevant driving circuits for providing the corresponding bias control signals, therefore, the embodiments of the present application can limit the number of image display cycles in the repeated display cycle C; optionally, the number range of the image display cycles included in the repeated display cycle C provided by the embodiments of the present application is [2, 10].

[0060] Figure 9 Schematic illustration taking the repeated display cycle C including two image display cycles as an example. When the repeated display cycle C includes a greater number of image display cycles, in the repeated display cycle C, the durations of the bias pulse intervals of any two adjacent image display cycles can be set to be different. Specifically, as Figure 10The driving timing diagram of the pixel circuit 10 shown schematically. The repeated display period C may include four consecutive image display periods. Any one image display period includes a data writing scan frame Z1, a holding scan frame Z21, a bias holding scan frame Z3, and a holding scan frame Z23. The bias pulse interval of the first image display period is b1, the bias pulse interval of the second image display period is b2, the bias pulse interval of the third image display period is b3, and the bias pulse interval of the fourth image display period is b4. Among them, the duration of the bias pulse interval b1 is different from that of the adjacent bias pulse interval b2, the duration of the bias pulse interval b2 is different from that of the adjacent bias pulse interval b3, and the duration of the bias pulse interval b3 is different from that of the adjacent bias pulse interval b4. Thus, the more the number of image display periods with different durations of the bias pulse interval is designed, the greater the impact on improving the overlap situation in time between the data writing sub-stage M13 at the set area A1 and the second bias sub-stage M15 at the replication area A1'. Therefore, the replication problem at the replication area A1' when the set area A1 of the display panel 100 displays a low-brightness and low-order picture can be further improved, and the display effect of the display panel 100 can be enhanced.

[0061] Further, in the repeated display period C, the duration difference between the bias pulse intervals of two adjacent image display periods is the same. Taking Figure 10 the shown bias pulse intervals b1, b2, b3, and b4 as an example, the duration difference between the bias pulse interval b1 and the adjacent bias pulse interval b2, the duration difference between the bias pulse interval b2 and the adjacent bias pulse interval b3, and the duration difference between the bias pulse interval b3 and the adjacent bias pulse interval b4 are all the same. Thus, the timing of the bias control signal is designed regularly, so that the design difficulty of the relevant driving circuit providing the corresponding bias control signal can be reduced. At the same time, in order to improve the display flicker problem of the display panel 100 caused by the timing change of the bias control signal, the embodiment of the present application also optimizes the duration difference between the bias pulse intervals of two adjacent image display periods. Specifically, in the repeated display period, the durations of the bias pulse intervals of two adjacent image display periods are respectively set to b11 and b22, where b11 and b22 satisfy the following conditions:

[0062]

[0063] Wherein, Δb is the absolute value of the difference between b11 and b22, Flicker is the flicker value of the display panel 100, α is the Flicker coefficient of the display panel 100, and Line is the resolution of the display panel 100 in the arrangement direction of the pixel circuits along the rows (i.e., the second direction Y). On the basis of restricting the flicker value of the parameter Flicker, the Flicker coefficient α, and the resolution Line of the display panel 100 in the arrangement direction of the pixel circuits along the rows, the time difference Δb of the bias pulse intervals between two adjacent image display periods can be optimized through calculation. On the basis of improving the replication problem in the replication area A1' when the display panel 100 displays a low-brightness and low-order picture in the set area A1, the flicker problem of the display panel 100 is reduced, and the display effect of the display panel 100 is further improved.

[0064] As can be seen from the above, the durations of the bias pulse intervals of all the image display periods in the repeated display period C can be designed regularly to achieve the purpose of regularly designing the timing of the bias control signal, thereby reducing the design difficulty of the relevant driving circuits that provide the corresponding bias control signal. For example, in some embodiments, in the repeated display period C, the durations of the bias pulse intervals of at least two consecutive image display periods can show an increasing trend; that is, in the time sequence, the durations of the bias pulse intervals of all the image display periods in the repeated display period C show an increasing trend. Specifically, as Figure 11 shown in the driving timing diagram of the pixel circuit 10, the repeated display period C is schematically shown by taking the example of including four consecutive image display periods. Any one image display period includes a data writing scan frame Z1, a holding scan frame Z21, a bias holding scan frame Z3, and a holding scan frame Z23. The bias pulse interval of the first image display period is b1, the bias pulse interval of the second image display period is b2, the bias pulse interval of the third image display period is b3, and the bias pulse interval of the fourth image display period is b4. Among them, in the time sequence, the durations of the bias pulse interval b1, the bias pulse interval b2, the bias pulse interval b3, and the bias pulse interval b4 show an increasing trend. Optionally, the durations of the bias pulse interval b1, the bias pulse interval b2, the bias pulse interval b3, and the bias pulse interval b4 increase in a step-by-step manner; that is to say, the time difference between the bias pulse interval b1 and the adjacent bias pulse interval b2, the time difference between the bias pulse interval b2 and the adjacent bias pulse interval b3, and the time difference between the bias pulse interval b3 and the adjacent bias pulse interval b4 are all the same, and the time difference can be obtained by combining the above-mentioned calculation formula of Δb. On the basis of improving the replication problem in the display panel 100, the flicker problem of the display panel 100 can also be reduced.

[0065] Alternatively, in some embodiments, in the repeated display period C, the duration of the bias pulse intervals of at least two consecutive image display periods shows a decreasing trend; that is, in chronological order, the duration of the bias pulse intervals of all image display periods in the repeated display period C shows a decreasing trend. Specifically, as Figure 12 shown in the driving timing diagram of the pixel circuit 10, the repeated display period C is exemplified by including four consecutive image display periods. Any one image display period includes a data write scan frame Z1, a hold scan frame Z21, a bias hold scan frame Z3, and a hold scan frame Z23. The bias pulse interval of the first image display period is b1, the bias pulse interval of the second image display period is b2, the bias pulse interval of the third image display period is b3, and the bias pulse interval of the fourth image display period is b4. Among them, in chronological order, the durations of the bias pulse intervals b1, b2, b3, and b4 show a decreasing trend. Optionally, the durations of the bias pulse intervals b1, b2, b3, and b4 decrease in a stepwise manner; that is, the difference in duration between the bias pulse interval b1 and the adjacent bias pulse interval b2, the difference in duration between the bias pulse interval b2 and the adjacent bias pulse interval b3, and the difference in duration between the bias pulse interval b3 and the adjacent bias pulse interval b4 are all the same. The duration difference can be obtained by combining the calculation formula of Δb shown above. On the basis of improving the replication problem in the display panel 100, it can also reduce the flicker problem of the display panel 100.

[0066] Alternatively, in some embodiments, in the repeated display period C, the duration of the bias pulse intervals of at least two consecutive image display periods shows a trend of increasing first and then decreasing; that is, in chronological order, the duration of the bias pulse intervals of all image display periods in the repeated display period C shows a trend of increasing first and then decreasing. Specifically, as Figure 13The driving timing diagram of the pixel circuit 10 shown is exemplified by repeating the display period C to include five consecutive image display periods. Any one image display period includes a data writing scan frame Z1, a holding scan frame Z21, a bias holding scan frame Z3, and a holding scan frame Z23. The bias pulse interval of the first image display period is b1, the bias pulse interval of the second image display period is b2, the bias pulse interval of the third image display period is b3, the bias pulse interval of the fourth image display period is b4, and the bias pulse interval of the fifth image display period is b5. Among them, in chronological order, the durations of the bias pulse intervals b1, b2, b3, b4, and b5 first increase and then decrease, so as to avoid the problem of excessive difference in duration between the last bias pulse interval of the previous repeated display period C and the first bias pulse interval of the next repeated display period C, and improve the flicker problem of the display panel 100 caused by the sudden change in the timing of the bias control signal. Optionally, the durations of the bias pulse intervals b1, b2, b3, b4, and b5 decrease and decrease in a stepwise manner; that is, the duration difference between the bias pulse interval b1 and the adjacent bias pulse interval b2, the duration difference between the bias pulse interval b2 and the adjacent bias pulse interval b3, the duration difference between the bias pulse interval b3 and the adjacent bias pulse interval b4, and the duration difference between the bias pulse interval b4 and the adjacent bias pulse interval b5 are all the same, and the duration of the bias pulse interval b1 is the same as the duration of the bias pulse interval b5, the duration of the bias pulse interval b2 is the same as the duration of the bias pulse interval b4, and the duration of the bias pulse interval b3 is the largest. The duration difference can be obtained by combining the calculation formula of Δb shown above. On the basis of improving the replication problem in the display panel 100, the flicker problem of the display panel 100 can also be reduced.

[0067] Or in some embodiments, in the repeated display period C, the durations of the bias pulse intervals of at least two consecutive image display periods first decrease and then increase; that is, in chronological order, the durations of the bias pulse intervals of all image display periods in the repeated display period C first decrease and then increase. Specifically, as Figure 14The driving timing diagram of the pixel circuit 10 shown is schematically illustrated by taking the repeated display period C including five consecutive image display periods as an example. Any one image display period includes a data writing scan frame Z1, a holding scan frame Z21, a bias holding scan frame Z3, and a holding scan frame Z23. The bias pulse interval of the first image display period is b1, the bias pulse interval of the second image display period is b2, the bias pulse interval of the third image display period is b3, the bias pulse interval of the fourth image display period is b4, and the bias pulse interval of the fifth image display period is b5. Among them, in chronological order, the durations of the bias pulse intervals b1, b2, b3, b4, and b5 show a trend of decreasing first and then increasing, so as to avoid the problem of too large a difference in duration between the last bias pulse interval of the previous repeated display period C and the first bias pulse interval of the next repeated display period C, and improve the flicker problem of the display panel 100 caused by the sudden change in the timing of the bias control signal. Optionally, the durations of the bias pulse intervals b1, b2, b3, b4, and b5 decrease and increase in a stepwise manner; that is, the difference in duration between the bias pulse interval b1 and the adjacent bias pulse interval b2, the difference in duration between the bias pulse interval b2 and the adjacent bias pulse interval b3, the difference in duration between the bias pulse interval b3 and the adjacent bias pulse interval b4, and the difference in duration between the bias pulse interval b4 and the adjacent bias pulse interval b5 are all the same, and the duration of the bias pulse interval b1 is the same as the duration of the bias pulse interval b5, the duration of the bias pulse interval b2 is the same as the duration of the bias pulse interval b4, and the duration of the bias pulse interval b3 is the smallest. The duration difference can be obtained by combining the above-mentioned schematic calculation formula of Δb. On the basis of improving the replication problem in the display panel 100, it can also reduce the flicker problem of the display panel 100.

[0068] On the basis of any of the above embodiments, the present application can also set a timing adjustment stage between adjacent image display periods. As Figure 15Timing diagram of an image display cycle of the schematic pixel circuit 10. During at least part of the image display cycle, a porch stage Ph is further included between two adjacent image display cycles. After driving the pixel circuit 10 according to the timing of the image display cycle, it enters the porch stage Ph. Among them, in the porch stage Ph, all control signal lines transmit invalid levels, that is, the light emission control signal line Emit, the reset control signal line S1, the data write control signal line S2, and the bias control signal line SPX all transmit no levels in the porch stage Ph, so as to briefly adjust the corresponding driving lines in the porch stage Ph, thereby avoiding the problem of chaotic output signal timing of the corresponding driving lines after long-term operation. In some embodiments, during the entire operation of the display panel 100, a porch stage Ph can be set between any two adjacent image display cycles; or, during the entire operation of the display panel 100, a porch stage Ph is set after every set number of image display cycles. The present application does not make specific limitations on this, and it needs to be designed according to actual applications.

[0069] Combined with Figure 16 and Figure 17 as shown, Figure 16 It schematically shows a driving timing diagram of the display panel 100, which is schematically shown by taking the display panel 100 including 8 pixel circuit rows as an example. Emit1 is the light emission control signal line electrically connected to the first pixel circuit row, Emit2 is the light emission control signal line electrically connected to the second pixel circuit row, and so on. Emit8 is the light emission control signal line electrically connected to the eighth pixel circuit row; and, SPX1 is the bias control signal line electrically connected to the first pixel circuit row, SPX2 is the bias control signal line electrically connected to the second pixel circuit row, and so on. SPX8 is the bias control signal line electrically connected to the eighth pixel circuit row; In addition, the relevant timing of the prior art for comparison is also schematically shown, that is, SPX1' is the bias control signal line electrically connected to the first pixel circuit row of the prior art, SPX2' is the bias control signal line electrically connected to the second pixel circuit row of the prior art, and so on. SPX8' is the bias control signal line electrically connected to the eighth pixel circuit row of the prior art. Figure 17 It schematically shows the corresponding display effect of the display panel 100. Among them, when a porch stage Ph is set between adjacent image display cycles, by setting the bias pulse interval between the first bias sub-stage and the second bias sub-stage M15 of at least one image display cycle to be different from the bias pulse interval of the remaining image display cycles, the part of the brightness stripe region Y3 caused by setting the porch stage Ph can be moved in the second direction Y over time, as Figure 17It is translated upward to the luminance stripe region Y31 or downward to the luminance stripe region Y32 as shown in the figure, thereby weakening the problem of poor display effect caused by the fixation of the luminance stripe region Y3; at the same time, it can also reduce the luminance difference between the luminance stripe regions Y3, Y31, and Y32 and the remaining regions, improving the display luminance uniformity of the entire display panel 100.

[0070] Specifically, in combination with Figure 16 the timing of the existing bias control signal line SPX' and the light emission control signal line Emit shown in the figure, the duration of the bias pulse interval between the first bias sub-stage and the second bias sub-stage M15 in the image display period of the existing bias control signal line SPX' is fixed at K2, such that: outside the porch stage Ph, in the second bias sub-stage M15 of the pixel circuit row scanned first, there is an overlap in timing with the first bias sub-stage of the fixed pixel circuit row scanned later (as shown in Figure 16 the shaded area Y1 in the figure, the second bias sub-stage M15 of the first pixel circuit row overlaps in timing with the first bias sub-stage of the fifth pixel circuit row), at this time, two pixel circuit rows are connected to the anode reset voltage Vref2. Since the anode reset signal line (the signal line for providing the anode reset voltage Vref2) to which all the pixel circuits 10 in the display panel 100 are electrically connected is actually the same signal line, the actual load of the anode reset signal line is equivalent to the pixel circuits 10 of two pixel circuit rows at this time, that is, the anode reset signal line simultaneously resets the anodes 21 of the light-emitting elements 20 electrically connected to the two pixel circuit rows; and in the porch stage Ph, at this time, the second bias sub-stage M15 of the fifth pixel circuit row and the second bias sub-stage M15 of the sixth pixel circuit row do not have an overlapping part with the first bias sub-stage of any other pixel circuit row in timing. At this time, only one pixel circuit row is connected to the anode reset voltage Vref2, which is equivalent to the actual load of the anode reset signal line being only the pixel circuits 10 of one pixel circuit row, that is, the anode reset signal line only resets the anode 21 of the light-emitting element 20 electrically connected to one pixel circuit row. This results in inconsistent actual loads of the anode reset signal line outside the porch stage Ph and in the porch stage Ph, and further leads to different reset degrees of the anode 21 of the light-emitting element 20 in the second bias sub-stage M15, thereby causing the problem of display luminance difference; and the second bias sub-stage M15 of the existing pixel circuit row scanned first overlaps in timing with the first bias sub-stage of the fixed pixel circuit row scanned later, so the area with luminance difference on the display panel 100 is fixed, that is, it appears in the luminance stripe region Y3.

[0071] In the technical solution provided by the embodiments of the present application, when a porch stage Ph is set between adjacent image display cycles, the bias pulse interval between the first bias sub-stage and the second bias sub-stage M15 in at least one image display cycle is set to be different from the bias pulse intervals in the remaining image display cycles. As Figure 16 shown in the timing diagrams of the light emission control signal line Emit and the bias control signal line SPX, the duration of the bias pulse interval between the first bias sub-stage and the second bias sub-stage M15 in the image display cycle is adjusted to K1, such that: outside the porch stage Ph, the second bias sub-stage M15 of the pixel circuit rows scanned first and the first bias sub-stage of the fixed pixel circuit rows scanned later only partially overlap or do not overlap in timing (as Figure 16For the part corresponding to the schematic shaded area Y2, the second bias sub-stage M15 of the second pixel circuit row and the first bias sub-stage of the sixth pixel circuit row do not overlap in time. At this time, the actual load of the anode reset signal line is equivalent to the pixel circuit 10 of one pixel circuit row. In the porch stage Ph, at this time, the second bias sub-stage M15 of the fifth pixel circuit row and the second bias sub-stage M15 of the sixth pixel circuit row do not overlap with the first bias sub-stage of any other pixel circuit row in time. Therefore, the actual load of the anode reset signal line is also equivalent to the pixel circuit 10 of one pixel circuit row at this time, making the actual load of the anode reset signal line basically the same outside and inside the porch stage Ph. Furthermore, the reset degree of the anode 21 of the light-emitting element 20 in the second bias sub-stage M15 is basically the same, improving the brightness difference problem of the display panel 100. In addition, even if there is partial overlap in time between the second bias sub-stage M15 of the pixel circuit row scanned first and the first bias sub-stage of the fixed pixel circuit row scanned later, by optimizing and adjusting the duration K1 of the bias pulse interval, it can be made that in the porch stage Ph, the second bias sub-stage M15 of the fifth pixel circuit row and the second bias sub-stage M15 of the sixth pixel circuit row are no longer fixedly corresponding. Even more, it can even correspond upward to at least part of the second bias sub-stage M15 of the fourth pixel circuit row, or downward to at least part of the second bias sub-stage M15 of the seventh pixel circuit row. Thus, during the operation of the display panel 100, the brightness difference part no longer fixedly appears at the brightness stripe Y3, but appears at the brightness stripes Y3, Y31, and Y32 according to the timing of the image display cycle, thereby weakening the problem of poor display effect caused by the fixed brightness stripe area Y3. Optionally, the duration K1 of the bias pulse interval between the first bias sub-stage and the second bias sub-stage of the at least one image display cycle provided in the embodiment of the present application is greater than the duration K2 of the bias pulse interval of the remaining image display cycles. It should be noted that for the adjustment of the duration of the bias pulse interval in the embodiment of the present application, it can be to keep the timing of the first bias sub-stage in the data write scan frame Z1 unchanged and adjust the timing of the second bias sub-stage M15 in the bias hold scan frame Z3 to achieve the purpose of adjusting the bias pulse interval between the first bias sub-stage and the second bias sub-stage M15.

[0072] As can be seen from the above analysis, by optimizing the difference between the duration K1 of the bias pulse interval and the duration K2 of the bias pulse interval, the problem of poor display effect caused by the fixed luminance stripe region Y3 can be weakened, and the display luminance uniformity of the entire display panel 100 can be improved. Optionally, the duration of the porch stage Ph provided in the embodiments of the present application is less than K1 - K2; by setting the duration K1 of the bias pulse interval to be greater than the duration K2 of the bias pulse interval by at least the duration of the porch stage Ph, and optimizing the specific duration difference between K1 and K2, the number of the second bias sub-stages M15 corresponding to the porch stage Ph can be reduced; such as Figure 16 the second bias sub-stage M15 of the 6th pixel circuit row in

[0073] can be located outside the porch stage Ph due to the increase in the difference between K1 and K2, thereby reducing the area of the luminance abnormal region in the display panel 100 caused by the setting of the porch stage Ph and improving the display effect of the display panel 100. Alternatively, the duration of the porch stage provided in the embodiments of the present application is not less than K1 - K2, and the difference degree between the duration K1 of the bias pulse interval and the duration K2 of the bias pulse interval is reduced. While weakening the problem of poor display effect caused by the fixed luminance stripe region Y3 and improving the display luminance uniformity of the entire display panel 100, the display flicker problem caused by large timing differences can also be improved. Figure 18In the schematic timing diagram, in the timing part corresponding to the shaded area Y2, the second bias sub-stage M15 of the second pixel circuit row partially overlaps in timing with the first bias sub-stage of the sixth pixel circuit row; while in the porch stage Ph, the second bias sub-stage M15 of some pixel circuit rows does not have an overlapping part with the first bias sub-stage of any other pixel circuit rows in timing. At this time, relevant voltage compensation can also be performed on the corresponding part of the pixel circuit rows in the porch stage Ph during the second bias sub-stage M15 to compensate for the brightness difference problem caused by different reset degrees. That is, the anode reset module 14 provided in the embodiment of the present application is electrically connected to the anode reset signal line, and the anode reset signal line outputs the anode reset voltage Vref2; during the process of driving and scanning the pixel circuit rows based on the image display cycle, the driving method further includes: in the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the j-th pixel circuit row to the (j + x)-th pixel circuit row, applying a reset compensation voltage to the anode reset signal line on the basis of the anode reset voltage Vref2, where j and j + x are positive integers not greater than M and greater than 1. Continuing as Figure 18 As shown, in the timing corresponding to the porch stage Ph of the first pixel circuit row, the second bias sub-stage M15 of the fifth pixel circuit row to the sixth pixel circuit row does not have an overlapping part with the first bias sub-stage of any other pixel circuit rows in timing; therefore, in the timing corresponding to the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the fifth pixel circuit row, and in the second bias sub-stage M15 of the sixth pixel circuit row, the anode reset signal line only resets the anode 21 of the light-emitting element 20 electrically connected to one pixel circuit row. Compared with the situation where the anode 21 of the light-emitting element 20 electrically connected to two pixel circuit rows is reset during the second bias sub-stage M15 outside the porch stage Ph of the first pixel circuit row, this is equivalent to "over-resetting" the anode 21 of the light-emitting element 20 at this time, which will cause the brightness of the display panel 100 to be lower at the corresponding areas of the light-emitting elements 20 of the fifth pixel circuit row and the sixth pixel circuit row, and horizontal stripes will appear during the corresponding second bias sub-stage M15 in the porch stage Ph of the first pixel circuit row. Therefore, in the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the fifth pixel circuit row to the sixth pixel circuit row, applying a reset compensation voltage to the anode reset signal line on the basis of the anode reset voltage Vref2 to compensate for the "over-resetting" problem of the anode 21 of the light-emitting element 20 at this time, thereby improving the situation of horizontal stripes in the display brightness of the display panel 100.

[0074] In addition to the method of directly compensating for the "over-reset" condition of the anode 21 of the light-emitting element 20 provided above, the embodiments of the present application can also indirectly compensate for the "over-reset" condition of the anode 21 of the light-emitting element 20. Specifically, the bias module 17 is electrically connected to the bias signal line, and the bias signal line outputs a bias voltage DVH; during the process of driving and scanning the pixel circuit rows based on the image display period, the driving method further includes: in the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the j-th pixel circuit row to the j + x-th pixel circuit row, a bias compensation voltage is applied to the bias signal line based on the bias voltage DVH, where j and j + x are positive integers not greater than M and greater than 1. Continuing to combine Figure 18 , in the timing corresponding to the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the fifth pixel circuit row, and in the second bias sub-stage M15 of the sixth pixel circuit row, a bias compensation voltage is applied to the bias signal line based on the bias voltage DVH. After the pixel circuit 10 enters the light-emitting stage M2, the bias compensation voltage will act on the anode 21 of the light-emitting element 20 to compensate for the "over-reset" problem of the anode 21 of the light-emitting element 20, thereby improving the situation of the display brightness stripes of the display panel 100.

[0075] Based on this, the embodiments of the present application can also combine the above two compensation methods to achieve the purpose of voltage compensation for the light-emitting element 20. That is, the anode reset module 14 provided in the embodiments of the present application is electrically connected to the anode reset signal line, and the anode reset signal line outputs an anode reset voltage Vref2; and, the bias module 17 is electrically connected to the bias signal line, and the bias signal line outputs a bias voltage DVH. During the process of driving and scanning the pixel circuit rows based on the image display period, the driving method further includes: in the porch stage Ph of the first pixel circuit row, and in the second bias sub-stage M15 of the j-th pixel circuit row to the j + x-th pixel circuit row, a reset compensation voltage is applied to the anode reset signal line based on the anode reset voltage Vref2, and a bias compensation voltage is applied to the bias signal line based on the bias voltage DVH, where j and j + x are positive integers not greater than M and greater than 1.

[0076] Based on the same inventive concept, the embodiments of the present application also provide an electronic device. Refer to Figure 19Schematic structural diagram of the electronic device shown. The electronic device 1000 provided in the embodiments of the present application includes a display panel 100, and the display panel 100 includes M pixel circuit rows. And a driving circuit 40 electrically connected to the pixel circuit rows. Among them, the driving circuit 40 is used to execute the driving method of the display panel 100 provided in any of the above embodiments. Optionally, the driving circuit 40 provided in the embodiments of the present application can be integrated into the display panel 100. Among them, the display panel 100 includes a display area and a non-display area outside the display area, and the driving circuit 40 can be located in the non-display area of the display panel 100; specifically, the driving circuit 40 can be located in the non-display area on any one side of the display area in the pixel column arrangement direction, or the driving circuit 40 can be located in the non-display areas on both sides of the display area in the pixel column arrangement direction, or the driving circuit 40 can be located in the non-display area on any one side of the display area in the pixel row arrangement direction, or the driving circuit 40 can be located in the non-display areas on both sides of the display area in the pixel row arrangement direction, or the driving circuit 40 can be located in the non-display area on at least one side of the display area in the pixel column arrangement direction and the pixel row arrangement direction. The present application does not make specific limitations on this. At this time, the driving circuit 40 can directly provide corresponding timing levels for the light emission control signal line Emit, the reset control signal line S1, the data write control signal line S2, and the bias control signal line SPX.

[0077] Or as Figure 20 Schematic structural diagram of the electronic device shown. The integrated circuit 40 provided in the embodiments of the present application can also be integrated into a structure outside the display panel 100. For example, the electronic device 1000 includes a control main board 200 electrically connected to the display panel 100, and the display panel 100 is electrically connected to the control main board 200 through a flexible printed circuit board FPC. The driving circuit 40 can be integrated into the control main board 200. The driving circuit 40 can be electrically connected to the pixel circuit rows through driving lines. The driving circuit 40 outputs relevant control signals to the driving lines to control the driving lines to output corresponding control signals to the light emission control signal line Emit, the reset control signal line S1, the data write control signal line S2, and the bias control signal line SPX, so as to achieve the purpose of indirectly providing corresponding timing levels for the light emission control signal line Emit, the reset control signal line S1, the data write control signal line S2, and the bias control signal line SPX by the driving circuit 40. The present application does not make specific limitations on this.

[0078] In some embodiments, the electronic device 1000 provided in the embodiments of the present application can be a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, an in-vehicle display device, etc.

[0079] In summary, the embodiments of the present application provide a driving method for a display panel and an electronic device. The driving method for the display panel includes: driving and scanning the pixel circuit rows based on the image display period to control the display panel to perform screen display. Among them, the bias pulse interval between the first bias sub-stage and the second bias sub-stage in at least one of the image display periods is different from the duration of the bias pulse intervals in the remaining image display periods. Thus, by optimizing this duration, the replication problem when the display panel displays a low-brightness and low-order screen in a set area is improved, and the display effect of the display panel is enhanced.

[0080] In the description of the embodiments of the present application, it should be understood that terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application.

[0081] In addition, terms such as "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0082] In the embodiments of the present application, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communicable with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0083] In the embodiments of the present application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the horizontal height of the first feature is less than that of the second feature.

[0084] In the embodiments of the present application, when terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0085] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes M pixel circuit rows, each pixel circuit row includes a plurality of pixel circuits, each pixel circuit includes a light emission control module, an anode reset module, and a bias module, the light emission control module is electrically connected to a light emission control signal line, and both the anode reset module and the bias module are electrically connected to a bias control signal line, where M is a positive integer greater than 1; One image display period of the pixel circuit row includes at least two scan frames, the at least two scan frames include a data writing scan frame and at least one holding scan frame that are sequentially performed, and the at least one holding scan frame includes a first bias holding scan frame to an Nth bias holding scan frame that are sequentially performed, where N is a positive integer; Each scan frame includes a pre-stage and a light emission stage that are sequentially performed, the pre-stage of the data writing scan frame includes a data writing sub-stage, and the pre-stage of the data writing scan frame includes a first bias sub-stage, and the pre-stage of the ith bias holding scan frame includes a second bias sub-stage, where i is a positive integer not greater than N; The light emission control signal line transmits an invalid level during the pre-stage, and the light emission control signal line transmits a valid level during the light emission stage, and the bias control signal line transmits a valid level during both the first bias sub-stage and the second bias sub-stage; The driving method includes: Driving and scanning the pixel circuit row based on the image display period to control the display panel to perform screen display, where the bias pulse interval between the first bias sub-stage and the second bias sub-stage of at least one of the image display periods is different from the bias pulse interval of the remaining image display periods in terms of duration.

2. The driving method of the display panel according to claim 1, wherein Taking at least two consecutive image display periods as a repeated display period; Driving and scanning the pixel circuit row based on the image display period includes: Driving and scanning the pixel circuit row based on the repeated display period, where in the repeated display period, the bias pulse interval of at least one of the image display periods is different from the bias pulse interval of the remaining image display periods in terms of duration.

3. The driving method of the display panel according to claim 2, characterized in that, The number range of the image display periods included in the repeated display period is [2, 10].

4. The driving method of the display panel according to claim 2, wherein In the repeated display period, the bias pulse intervals of two adjacent image display periods are different in terms of duration.

5. The driving method of the display panel according to claim 4, wherein, In the repeated display period, the difference in the duration of the bias pulse intervals of two adjacent image display periods is the same.

6. The driving method of the display panel according to claim 5, wherein, In the repeated display period, the bias pulse intervals of two adjacent image display periods are respectively set to b11 and b22, where b11 and b22 satisfy the following conditions: Where Δb is the absolute value of the difference between b11 and b22, Flicker is the flicker value of the display panel, α is the Flicker coefficient of the display panel, and Line is the resolution of the display panel along the arrangement direction of the pixel circuit row.

7. The driving method of the display panel according to claim 4, wherein In the repeated display period, the bias pulse intervals of the at least two consecutive image display periods show an increasing trend.

8. The driving method of the display panel according to claim 4, characterized in that During the repeated display period, the duration of the bias pulse interval in at least two consecutive image display periods shows a decreasing trend.

9. The driving method of the display panel according to claim 4, wherein During the repeated display period, the duration of the bias pulse interval in at least two consecutive image display periods shows a trend of first increasing and then decreasing.

10. The driving method of the display panel according to claim 4, characterized in that, During the repeated display period, the duration of the bias pulse interval in at least two consecutive image display periods shows a trend of first decreasing and then increasing.

11. The driving method of the display panel according to any one of claims 1-10, characterized in that, During at least part of the image display period, a porch stage is further included between two adjacent image display periods.

12. The driving method of the display panel according to claim 11, wherein The duration K1 of the bias pulse interval between the first bias sub-stage and the second bias sub-stage in at least one of the image display periods is greater than the duration K2 of the bias pulse interval in the remaining image display periods.

13. The driving method of the display panel according to claim 12, wherein The duration of the porch stage is less than K1 - K2; Alternatively, the duration of the porch stage is not less than K1 - K2.

14. The driving method of the display panel according to claim 11, wherein The anode reset module is electrically connected to the anode reset signal line, and the anode reset signal line outputs an anode reset voltage; During the process of driving and scanning the pixel circuit rows based on the image display period, the driving method further includes: During the porch stage of the first pixel circuit row and during the second bias sub-stage of the j-th pixel circuit row to the (j + x)-th pixel circuit row, a reset compensation voltage is applied to the anode reset signal line based on the anode reset voltage, where j and j + x are positive integers not greater than M and greater than 1.

15. The driving method of the display panel according to claim 11, characterized in that, The bias module is electrically connected to the bias signal line, and the bias signal line outputs a bias voltage; During the process of driving and scanning the pixel circuit rows based on the image display period, the driving method further includes: During the porch stage of the first pixel circuit row and during the second bias sub-stage of the j-th pixel circuit row to the (j + x)-th pixel circuit row, a bias compensation voltage is applied to the bias signal line based on the bias voltage, where j and j + x are positive integers not greater than M and greater than 1.

16. The driving method of the display panel according to claim 11, wherein The anode reset module is electrically connected to the anode reset signal line, and the anode reset signal line outputs an anode reset voltage; and, the bias module is electrically connected to the bias signal line, and the bias signal line outputs a bias voltage; During the process of driving and scanning the pixel circuit rows based on the image display period, the driving method further includes: During the porch stage of the first pixel circuit row and during the second bias sub-stage of the j-th pixel circuit row to the (j + x)-th pixel circuit row, a reset compensation voltage is applied to the anode reset signal line based on the anode reset voltage, and a bias compensation voltage is applied to the bias signal line based on the bias voltage, where j and j + x are positive integers not greater than M and greater than 1.

17. An electronic device, characterized in that, The electronic device includes a display panel, and the display panel includes M pixel circuit rows; and a driving circuit electrically connected to the pixel circuit rows, where the driving circuit is configured to execute the driving method of the display panel according to any one of claims 1 - 17.

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