Electronic component including connection stud

Abstract

The invention relates to an electronic component including a connection post. More specifically, an electronic component including an electronic post is provided. An example electronic component, such as an electronic chip, includes a semiconductor substrate having opposing first and second faces and conductive posts intended to be connected to elements external to the electronic component, an insulating layer covering the second surface of the substrate, a first portion of the conductive pillar protrudes from the insulating layer and a second portion of the conductive pillar passes through the insulating layer and extends in the semiconductor substrate to a depth that is less than a thickness of the semiconductor substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of French Patent Application No. 2400536, titled "Composant électronique comprenant des piliers de connexion", filed on January 19, 2024, which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Field of the invention

[0003] The present disclosure relates to the field of electronic components having electrical connection posts, and more particularly to the field of electronic chips having electrical connection posts to be connected to a housing or another electronic chip. Background art

[0004] To connect an electronic chip to an external component, connection balls or posts can be provided on the surface of the electronic chip and connected to the conductive tracks of the electronic chip. Thus, it is possible to bring the connection balls or posts into contact with the conductive areas or tracks located on an external component (e.g., a housing or another electronic chip).

[0005] The reduction in the size of electronic chips has been accompanied by a reduction in the size of these connection elements. Using posts is preferred over using balls to obtain a high aspect ratio, which is the ratio of the height to the diameter of the connection pad.

[0006] However, using connection posts, especially when they have a high aspect ratio and / or when they have small dimensions, may have certain drawbacks: the brittleness of the connection posts, the high duration and cost of the connection post manufacturing method, or the risk of the connection posts tearing from the surface of the electronic chip on which they are formed. Summary of the invention

[0007] There is a need to at least partially improve certain aspects of an electronic chip including connection posts.

[0008] This object is achieved by an electronic component such as an electronic chip, the electronic component comprising: a semiconductor substrate having opposite first and second surfaces and conductive posts intended to be connected to elements external to the electronic component; an insulating layer covering the second surface of the substrate, a first portion of the conductive posts protruding from the insulating layer and a second portion of the conductive posts passing through the insulating layer and extending into the semiconductor substrate to a depth less than the thickness of the semiconductor substrate.

[0009] According to an embodiment, the second portion of the conductive post is formed by one or more cylindrical elements.

[0010] According to an embodiment, the second portion of the conductive post is formed by a plurality of coaxially arranged tubular elements.

[0011] According to an embodiment, it includes an electrically insulating layer disposed between the second portion of the conductive pillar and the semiconductor substrate.

[0012] According to an embodiment, it includes an interface layer, preferably made of TiCu, in contact with the second portion of the conductive pillar, and the interface layer is disposed between the conductive pillar and the electrically insulating layer.

[0013] According to an embodiment, it includes an active region extending in the semiconductor substrate from the second surface and including at least one discrete electronic component, and each conductive pillar further includes a connection track extending above the second surface of the semiconductor substrate and electrically connected to the active region.

[0014] According to an embodiment, the first portion of the conductive pillar has a height greater than 25 μm.

[0015] According to an embodiment, the second portion of the conductive pillar has a height of at least 5 μm.

[0016] This object is also achieved by a method of manufacturing an electronic component such as an electronic chip, the electronic component including a semiconductor substrate having opposite first and second surfaces and conductive pillars intended to be connected to elements external to the electronic component, the method including the following steps:

[0017] - Forming an electrically insulating layer on the second surface of the semiconductor substrate,

[0018] - Forming an opening that passes through the insulating layer and continues through a partial thickness of the semiconductor substrate,

[0019] - Forming the first portion of the conductive pillar by filling the opening with a conductive material,

[0020] - Forming the second portion of the conductive pillar from the first portion of the pillar.

[0021] According to an embodiment, the method includes the step of forming an electrically insulating layer in the opening before filling the opening with the conductive material.

[0022] According to an embodiment, the method includes the step of depositing an interface layer (preferably made of TiCu) in the opening between the step of forming the electrically insulating layer and the step of filling the opening with the conductive material. Description of the Drawings

[0023] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0024] Figure 1 is a partial and simplified cross-sectional view of an example of an electronic chip;

[0025] Figure 2 is a partial and simplified cross-sectional view of an electronic chip;

[0026] Figure 3 is a partial and simplified cross-sectional view of a column positioned in a substrate according to a specific embodiment of an electronic chip;

[0027] Figure 4 、 Figure 5 and Figure 6 are simplified top and cross-sectional views of different columns positioned in a substrate according to a specific embodiment of an electronic chip (the dotted line indicates the dividing line of the electronic chip formed in the substrate);

[0028] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、 Figure 7G and Figure 7H each is a partial and simplified cross-sectional view of a structure obtained in different steps of an embodiment of a method for manufacturing a Figure 2 microchip.

[0029] For better readability of the drawings, the elements in the drawings are not shown to scale uniformly. DETAILED DESCRIPTION

[0030] Similar features in the respective figures are denoted by similar reference numerals. In particular, the common structural and / or functional features among the respective embodiments may have the same reference numerals and may have exactly the same structure, dimensions, and material properties.

[0031] For clarity, only the steps and elements useful for understanding the described embodiments are illustrated and described in detail.

[0032] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection with no intermediate elements other than conductors, and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following description, when referring to terms defining an absolute position (such as the terms "edge", "rear", "top", "bottom", "left", "right", etc.) or terms defining a relative position (such as the terms "above", "below", "upper", "lower", etc.) or terms defining a direction (such as the terms "horizontal", "vertical", etc.), unless otherwise stated, they all refer to the orientation of the drawings.

[0034] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "around" mean within 10%, preferably within 5%. Additionally, the terms "insulating" and "conductive" are herein considered to mean "electrically insulating" and "electrically conductive", respectively.

[0035] Figure 1 is a partial and simplified cross-sectional view of an example of an electronic chip 10.

[0036] The electronic chip 10 includes:

[0037] - A semiconductor substrate 12, which includes a lower surface 14 (a first surface) and an upper surface 16

[0038] (a second surface);

[0039] - An insulating layer 18, which is capable of covering the lower surface 14;

[0040] - An active region 20 in the substrate 12, which is flush with the upper surface 16, and one or more electronic components (not shown) are formed inside and / or on top of the active region 20;

[0041] - An interconnect structure 22, which covers the upper surface 16 of the substrate, the interconnect structure 22 includes an upper surface and a lower surface in contact with the substrate 12, the interconnect structure includes an insulating layer 24 and conductive tracks 26 in the insulating layer 24, and some of the conductive tracks 26 are in contact with the active region 20;

[0042] - Openings 28 in the insulating layer 24, each opening exposing a part of one of the conductive tracks 26; and

[0043] - Connection posts 30, two connection posts are shown as an example in Figure 1 and each post is connected to one of the conductive tracks 26.

[0044] Each connection post 30 includes a shaft 32 extending along an axis A that is substantially orthogonal to the upper surface 16. The shaft 32 includes a base 34 on the side closest to the substrate 12, an end surface 36 opposite the base 34 on the side farthest from the substrate 12, and a sidewall 38 that couples the base 34 to the end surface 36. The connection post 30 also includes an interface layer 40 between the base 34 and the interconnect structure 22. The post 30 also includes a finishing layer 42 covering the end surface 36 and a block 44 of bonding material covering the finishing layer 42.

[0045] Using connection posts 30 such as those shown in Figure 1 may have certain disadvantages. When the connection posts 30 have small dimensions or a high aspect ratio (also known as the shape factor), the connection posts 30 may be brittle. Additionally, each connection post 30 is only mechanically coupled to the interconnect structure 22 through the interface layer 34.

[0046] In addition, during the manufacture of such a device, the method includes the step of etching an interface layer 40 deposited over the entire wafer after forming connection posts 30 thereon. Now, when the material is etched, the etching extends laterally under the conductive material of the connection posts 30 (a phenomenon called "undercutting"), which causes the interface layer 34 located under the posts 30 to be etched partially from its peripheral portion. This makes the coupling between the shaft 32 and the interconnect structure 22 brittle. Then an increased risk of tearing of the connection posts 30 from the connection structure 22 can be observed. As the diameter of the posts decreases, the percentage of contact surface area loss increases.

[0047] Figure 2 is a partial and simplified cross-sectional view of an example of an electronic chip 50. The electronic chip 50 includes Figure 1 all the elements of the electronic chip 10, except that the connection posts 30 are replaced by connection posts 60.

[0048] Each connection post 60 includes two parts mechanically fixed to each other:

[0049] - A first part (the upper part of the post), which is arranged to protrude from the chip 50 to allow an electrical connection with external elements (such as a housing or another electronic chip), and the first part extends or protrudes from the upper surface of an insulating layer 24 of the interconnect structure 22 covering the second surface 16 of the substrate 12.

[0050] - A second part (the lower part of the post), which passes completely through the insulating layer 24 of the interconnect structure 22 and a part of the substrate 12, and the height of the second part is lower than the thickness of the substrate 12.

[0051] More particularly, the first part of the post includes a shaft 62 extending along an axis Δ substantially orthogonal to the upper and lower surfaces of the substrate. The shaft protrudes from the insulating layer 24 of the interconnect structure 22 positioned on the upper surface 16 of the substrate 12. The shaft 62 has a base 64 arranged at the level of the upper surface of the interconnect structure 24, an end surface 66 arranged outside the substrate 12 and opposite to the base 64, and a side wall 68 connecting the base 64 to the end surface 66.

[0052] A decorative layer 72 covers the end surface 66 and is in direct physical contact with the end surface 66.

[0053] A mass 74 of bonding material covers the decorative layer 72.

[0054] The base 64 of the first part of the post is in direct contact with the second part of the post.

[0055] The first part is visible as it protrudes from the substrate. The second part is buried within the component: it is not visible during the normal use of the electronic component 50. Only by cutting the component 50 can it be observed.

[0056] The second part of the column may be formed by one or more elements 61. These elements are in direct contact with the base 64 of the shaft 62 of the first part 60 of the column.

[0057] The element 61 comprises a base (or lower surface), side walls and an upper surface. The upper surface is in direct contact with the upper portion of the column.

[0058] The elements 61 may have different shapes and / or different dimensions. The shapes and / or dimensions may be identical or different within the same column or between different columns.

[0059] According to various embodiments, the second portion of the column 60 may include a single element 61 ( Figure 3 , Figure 4 ) or multiple elements 61 ( Figure 2 , Figure 5 and Figure 6 ).

[0060] According to various embodiments, the second portion may be composed of a cylindrical element 61 ( Figure 3 and Figure 4 ) or multiple cylindrical elements 61 ( Figure 2 , Figure 5 ) is formed. The second portion of the column 60 may also be formed by one or more tubular elements 61. The tubular elements may be coaxially arranged ( Figure 6 ).

[0061] The cross-sectional area of the elements 61 or the sum of the cross-sectional areas of the elements 61 is preferably smaller than the cross-sectional area of the shaft 62 .

[0062] The elements 61 preferably have a height in the range of 5 μm to 50 μm. For example, they have a height of 10 μm. The average diameter of the elements 61 is preferably in the range of 1 μm to 40 μm. The average diameter of the cylindrical elements is, for example, 5 μm.

[0063] The average diameter means the diameter of an element 61 having a circular base having the same surface area as the element 61 .

[0064] Each post 60 is anchored in the substrate 12 across a portion of the thickness of the substrate 12 due to the element 61 or elements 61 of the second portion of the post 60. Figure 1 Compared to the mechanical stability of the column 30 shown in FIG, the mechanical stability of the column 60 is improved. The risk of the connecting strut 60 tearing is greatly reduced.

[0065] The electronic chip 50 further comprises an interface layer 70 which covers the base and the side walls of the element 61 (ie it completely covers the element 61 except for the upper surface in contact with the base 64 of the shaft 62 ).

[0066] This interface layer 70 acts as a seed layer during the formation of the element 61.

[0067] Since the interface layer 70 covers the element(s) 61, its developed surface area is larger than the surface area of the interface layer 40 that contacts the base 34 of the pillar 30 of the component shown in Figure 1 FIG.

[0068] Therefore, even for pillars of small dimensions (usually having an average diameter of the axis 62 less than 50 μm, or even less than or equal to 25 μm, or even less than or equal to 15 μm), the influence of the undercut of the interface layer 70 below the axis 62 of the pillar 60 is significantly reduced.

[0069] As an example, as shown in Figure 1 FIG., for the pillar 30 having an average diameter of the axis 32 of 15 μm and the interface layer 40 having a thickness of 0.3 μm, the percentage of the contact surface area lost between the pillar 30 and the interface layer 40 due to undercut is approximately 23%.

[0070] As a non - limiting illustration, for the pillar 60 as shown in Figure 2 FIG., having an average diameter of the axis 62 of 15 μm and the interface layer 70 having a thickness of 0.3 μm, if the pillar includes one element 61, two elements 61, and three elements 61 respectively, where each element 61 has a diameter of 5 μm and a height of 10 μm, then the percentage of the contact surface area lost between the pillar 60 and the interface layer 70 due to undercut will be only approximately 8%, 5%, and 3%.

[0071] An insulating layer 78 is arranged between the interface layer 70 and the substrate 12 to insulate the substrate 12 from the pillar 60.

[0072] In addition, the component includes connection tracks 76 (or RDL of the "redistribution layer") on the interconnect structure 22 and connects the axis 62 of the pillar 60 to one of the conductive tracks 26 in one of the openings 28.

[0073] There is also an interface layer 70 between the connection track 76 and the interconnect structure 22.

[0074] This interface layer 70 also acts as a seed layer during the formation of the connection track 76.

[0075] Now a method of manufacturing such an electronic chip 50 as shown in Figures 7A to 7H FIG. will be described. Figure 2 FIG.

[0076] The method includes at least the following steps:

[0077] - Provide a structure including a substrate 12 in which an active region 20 has been formed, a conduction track 26 positioned in or on the upper surface of the substrate 12 and connected to the active region 20,

[0078] - Cover the upper surface 16 of the substrate 12 with an insulating layer 24,

[0079] - Form an opening 82 passing through the insulating layer 24 and extending across a partial thickness of the semiconductor substrate 12,

[0080] - Form a first portion of the conductive column 60 by filling the opening 82 with a conductive material,

[0081] - Form a second portion of the conductive column 60 from a second portion of the column.

[0082] More particularly, the method may include the following steps:

[0083] a) Form an insulating layer 24 over a structure including the substrate 12, in which an active region 20 has been formed, a conduction track 26 positioned in or on the upper surface of the substrate 12 and connected to the active region 20, the insulating layer 24 covering the conduction track 26 and the upper surface 16 of the substrate 12( Figure 7A ),

[0084] b) Form one or more openings 82 at desired positions of each element 61 of the connection column 60, the openings passing through the insulating layer 24 and extending into the substrate 12( Figure 7B ),

[0085] c) Form an insulating layer 78 in the opening 82 to insulate the substrate 12 from the second portion of the column( Figure 7C ),

[0086] d) Form an opening 28 in the insulating layer 24 to make the conduction track 26 accessible,

[0087] e) Cover the obtained structure with an interface layer 70( Figure 7D ),

[0088] f) Locally deposit a protective film 80 over the structure to define the area on which the conductive material is to be deposited and protect other areas( Figure 7E ),

[0089] g) Deposit a conductive material to form the element(s) 61 of the second portion of the column 60 and then form the connection element 76( Figure 7F ),

[0090] h) Locally deposit a protective film 81 over the structure obtained in step f) to define the area on which the conductive material of the axis 62 of the column 60 is to be deposited and protect other areas,

[0091] i) Growing the axis 62 of the post 60 from the element 61( Figure 7G ),

[0092] j) Forming a decorative layer 72 and a block 74 of bonding material on the end surface 66 of the axis 62 of the post 60( Figure 7H ),

[0093] k) Removing the protective film 81,

[0094] l) Etching the interface layer 70 to electrically insulate the posts 60 from each other.

[0095] During step a), one or more discrete components (not shown) have been formed inside and / or on top of the active region 20. The (one or more) discrete components are selected, for example, from transistors, diodes, thyristors, triacs, filters, etc.

[0096] According to an embodiment, at this stage of the process, the substrate 12 corresponds to the plate.

[0097] The substrate 12 is made of, for example, silicon (Si), silicon carbide (SiC), III-V compounds (in particular gallium nitride (GaN)), or II-VI compounds. The substrate 12 may have a single-layer or multi-layer structure, such as a structure of the silicon-on-insulator (SOI) type. As an example, the substrate 12 may include a GaN layer covering a silicon support. According to an embodiment, the thickness of the substrate 12 is in the range of 50 μm to 300 μm.

[0098] A single active region is shown in the figure, but the active regions 20 of multiple microchips may be formed inside and / or on top of the substrate 12, and the active regions 20 may be identical or different.

[0099] In Figure 7A , the interconnect structure 22 includes two conduction tracks 26 connected to the active region 20 and an insulating layer 24 covering the conduction tracks 26 and the upper surface 16 of the substrate 12 surrounding the conduction tracks 26.

[0100] More than two conduction tracks 26 may be connected to the active region 20.

[0101] The conduction track 26 is made of a material selected, for example, from copper, copper alloy, titanium, titanium alloy, titanium nitride, platinum, platinum alloy. It may also be aluminum. According to an embodiment, the thickness of each metal track 26 is in the range of 0.5 μm to 1.5 μm.

[0102] The insulating layer 24 may be a multi-layer formed by multiple insulating layers.

[0103] The insulating layer 24 can be made of a dielectric material, such as an oxide or a nitride, preferably silicon oxide (SiO2), silicon nitride (e.g., Si3N4), silicon oxynitride (e.g., SiO x N y ) or hafnium oxide (HfO2). The insulating layer 24 can also be made of a polymer material.

[0104] According to an embodiment, the thickness of the insulating layer 24 is in the range of 0.5 μm to 1.5 μm.

[0105] Figure 7B Shown is the structure obtained after forming the openings 82 at the desired positions of each element 61 of the connection posts 60 (step b). The openings 82 completely penetrate the interconnect structure 22 and extend from the upper surface 16 to a partial thickness of the substrate 12. The openings are blind holes (in other words, the openings do not completely penetrate the substrate 12). The depth of the openings 82 can be in the range of 5 μm to 50 μm.

[0106] One or more openings 82 are formed for each post in order to form one or more elements 61, respectively.

[0107] In the figure, the openings 82 have a circular cross-section. However, the openings 82 can have a square cross-section, a rectangular cross-section, or a rectangular cross-section with rounded corners.

[0108] The openings 82 can be formed by laser etching.

[0109] Preferably, the openings 82 are formed by a deep reactive ion etching (DRIE) step.

[0110] In order to form the openings 82, a mask can be used. The layer 24 is etched through its entire thickness through the opening of the mask. Then, the openings 82 continue through a partial thickness of the substrate 12. The mask can be a resin mask. The insulating layer 24 (e.g., made of an oxide) can act as a "hard mask" during the formation of the openings 82 in the substrate 12.

[0111] During step c), an insulating layer 78 is formed in each opening. Figure 7C Shown is the structure obtained.

[0112] The insulating layer 78 covers the sidewalls and the bottom of the openings 82. The insulating layer 78 can be formed by depositing an insulating layer into the openings 82 or by oxidation of the substrate 12. For example, this step can be performed by thermal oxidation, low-temperature oxidation, wet oxidation, plasma-enhanced chemical vapor deposition (PECVD). Figure 7C Shown is an embodiment in which the insulating layer is obtained by oxidation of the substrate 12. The thickness of the insulating layer is selected so as not to close the openings 82. For example, in the range of 100 nm to 1 μm.

[0113] For each connection post 60 to be formed, an opening 28 is made in the insulating layer 24 to expose one of the conduction tracks 26 (step d). These openings 28 can be formed by using a mask.

[0114] During step e), an interface layer 70 is formed. At this stage of the method, the interface layer 70 covers all the walls of the cavity 82, in particular the side walls and the bottom of the cavity 82, the walls of the opening 28, and the exposed portion of the insulating layer 24 connecting the cavity 82 to the corresponding opening 28.

[0115] The thickness of the interface layer 70 is in the range of 10 nm to 1 μm. The interface layer 70 serves as a seed for forming the post 60 and the connection track 76 of the connection post 60. The interface layer 70 can include a titanium or chromium layer (serving as a bonding layer) and a copper layer (serving as a seed layer for subsequently forming the shaft 62 and the connection track 76). The interface layer 70 is preferably made of TiCu.

[0116] During step f), protective films 80 are deposited on the structure. They serve as a mask during the formation of the posts, and the posts 60 are formed in the openings of the mask.

[0117] During step g), the element(s) 61 of the second part of the post and the track 76 ( Figure 7F ) are formed.

[0118] For each connection post 60 to be formed, each cavity 82 is completely filled with a conductive material, thereby forming the element 61 of the connection post 60. When the cavity 82 is filled, the connection part 76 of each connection post is formed.

[0119] The conductive material for forming the element 61 can be deposited on the interface layer 70 by plasma enhanced chemical vapor deposition (PECVD) or by atomic layer deposition (ALD).

[0120] Preferably, the conductive material of the element 61 is deposited by ALD. The ALD technique is particularly advantageous for filling openings with small dimensions and / or with a high aspect ratio, i.e., when the ratio of the cavity height to the cavity diameter is high. In this case, the deposition of the conductive material is performed starting from the interface layer 70 in a direction substantially perpendicular to the interface layer 70. The deposition of the conductive material is performed in particular starting from the side walls of the cavity 82.

[0121] The conductive material for forming the connection track 76 can be deposited on the interface layer 70 by electrodeposition. The growth starts from the interface layer 70.

[0122] The thickness of the interface layer is, for example, in the range of 0.3 to 0.9 μm.

[0123] In step h), a protective film 81 is locally formed on the structure obtained in step g).

[0124] The protective film 80 deposited in step f) can be removed before step h), or the protective film 81 of step h) can be deposited over the film 80 applied in step f) so as to cover them.

[0125] The protective film 80 formed in step f) and / or the protective film 81 formed in step h) is, for example, a resin. They can be removed by wet etching ("stripping").

[0126] The protective film 81 includes an opening that is in a line perpendicular to the position of the axis 62 of the column 60 to be deposited in step g).

[0127] The growth of the first part of the column 60 is preferably carried out by electrodeposition. The conductive material forming the axis 62 is deposited from the second part of the column 60. The growth occurs in a direction substantially perpendicular to the main surfaces 14 and 16 of the substrate 12 ( Figure 7G ).

[0128] To form the axis 62, the conductive material can thus be deposited substantially over a thickness equal to half of the average diameter of the element 61. Once formed, the axis 62 projects from the upper surface 16 of the substrate 12.

[0129] The axis 62 can have a substantially cylindrical shape, which has an axis Δ, and the base is circular, square, rectangular, etc. The average diameter D of the axis 62 of the column 60 is in the range of 10 μm to 150 μm. According to the embodiment, the end surface 66 is substantially perpendicular to the axis Δ.

[0130] The total height H of the axis 62 from the base 64 to the end surface 66 is, for example, in the range of 75 μm to 400 μm. The height by which the axis 62 projects from the insulating layer 24 is in the range of 25 μm to 100 μm. The aspect ratio of the axis 62 (which corresponds to the ratio of the total height H of the axis 62 to the average diameter D of the axis 62) is in the range of 0.5 to 40.

[0131] The axis 62, the element 61, and the connection track 76 are preferably made of the same material. The axis 62, the element 61, and the connection track 76 are made of a metal, for example, made of copper, nickel, silver, gold, or an alloy of these metals. Preferably, they are made of copper.

[0132] In step h), for each connection column 60, a decorative layer 72 and a block 74 of bonding material are formed on the end surface 66.

[0133] The thickness of the decorative layer 72 is in the range of 10 nm to 5 μm, for example 3 μm. The decorative layer 72 is made of a conductive material, which improves the bonding of the block 74. The decorative layer 72 is made of metal, for example, especially gold, silver, platinum, palladium, nickel, titanium, chromium, and / or tantalum. Preferably, it is made of nickel. Such a layer can be deposited by physical vapor deposition (PVD). In the case where the assembly method is not carried out in a neutral or reducing atmosphere, the decorative layer 72 also enables the end surface 66 of the shaft 62 to avoid oxidation.

[0134] The material forming the block 74 depends particularly on the assembly method implemented to bond the electronic chip 50 to another component. The assembly method can particularly include a soldering step or a sintering step.

[0135] The material forming the block 74 is, for example, a solder material. It can be tin, silver, or one of their alloys, such as SnAgCu, SnAg, or SnAgPb. It can also be a gold-based material (such as SnAu or SnAuCu), a palladium-based material (e.g., SnPd or SnPdCu), or a platinum-based material (such as SnPt or SnPtCu).

[0136] The height of the block 74 measured from the decorative layer 72 can be approximately 25 μm.

[0137] After removing the protective film 80 (step f), the interface layer 70 located between the columns, more particularly between the connection tracks 76, is removed, preferably by etching (step l). The removal can be carried out by wet etching. The etching solution can be a hydrofluoric acid (HF) solution or an ammonia solution. The etching solution will be selected according to the nature of the passivation layer 24 (e.g., oxide or polymer).

[0138] The method can also include a cutting step to separate different electronic chips 50 formed in the same substrate 12.

[0139] At the end of the method, a chip as shown in Figure 2 is obtained.

[0140] Then, each individualized electronic chip 50 can be bonded to an external component, for example, a package or another electronic chip.

[0141] Such electronic chips find applications in many industrial fields, and particularly in the automotive and telephone fields.

[0142] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants can be combined, and those skilled in the art will think of other variants.

[0143] Based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. An electronic component, comprising: A semiconductor substrate having opposite first and second surfaces and conductive pillars configured to connect to components external to the electronic component; An insulating layer covering the second surface of the substrate, Wherein a first portion of the conductive pillar protrudes from the insulating layer and a second portion of the conductive pillar passes through the insulating layer and extends in the semiconductor substrate to a depth less than the thickness of the semiconductor substrate.

2. The electronic component according to claim 1, wherein the second portion of the conductive pillar is formed by one or more cylindrical elements.

3. The electronic component according to claim 1, wherein the second portion of the conductive pillar is formed by a plurality of coaxially arranged tubular elements.

4. The electronic component according to claim 1, comprising an electrically insulating layer disposed between the second portion of the conductive pillar and the semiconductor substrate.

5. The electronic component according to claim 1, comprising an interface layer in contact with the second portion of the conductive pillar, the interface layer being disposed between the conductive pillar and the electrically insulating layer.

6. The electronic component according to claim 1, comprising an active region extending from the second surface into the semiconductor substrate and containing at least one discrete electronic component, each conductive pillar further comprising a connection track extending above the second surface of the semiconductor substrate and electrically connected to the active region.

7. The electronic component according to claim 1, wherein the first portion of the conductive pillar has a height greater than 25 μm.

8. The electronic component according to claim 1, wherein the second portion of the conductive pillar has a height of at least 5 μm.

9. A method of manufacturing an electronic component, the electronic component comprising a semiconductor substrate having opposite first and second surfaces and conductive pillars configured to connect to components external to the electronic component, the method comprising: Forming an electrically insulating layer on the second surface of the semiconductor substrate; Forming an opening passing through the electrically insulating layer and extending through a partial thickness of the semiconductor substrate; Forming a first portion of the conductive pillar by filling the opening with a conductive material; Forming a second portion of the conductive pillar from the first portion of the pillar.

10. The method according to claim 9, further comprising forming an electrically insulating layer in the opening before filling the opening with the conductive material.

11. The method according to claim 10, further comprising depositing an interface layer into the opening between forming the electrically insulating layer and filling the opening with the conductive material.

12. The method according to claim 11, wherein the interface layer comprises TiCu.

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