High-power low-stray SiC MOSFET module

Abstract

The invention discloses a high-power low-stray SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) module. The module comprises a bottom-layer ceramic substrate, a top-layer ceramic substrate, a first SiC MOSFET chip and a second SiC MOSFET chip, wherein the first SiC MOSFET chip and the second SiC MOSFET chip are provided with a plurality of bridge arms; the first SiC MOSFET chips and the second SiC MOSFET chips of the bridge arms with odd numbers are symmetrically arranged on the bottom-layer ceramic substrate, and the corresponding DC + copper-clad region, grid copper-clad region and source copper-clad region are arranged on the bottom-layer ceramic substrate; the first SiC MOSFET chips and the second SiC MOSFET chips with the even number of bridge arms are symmetrically arranged on the top layer ceramic substrate, and the corresponding DC + copper-clad region, the grid copper-clad region and the source copper-clad region are arranged on the top layer ceramic substrate. According to the invention, the parasitic inductance of each branch is reduced by utilizing the mutual coupling relationship of the inductors between the branches.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor packaging, and particularly relates to a high-power low-stray SiC MOSFET module. Background Art

[0002] Wide-bandgap semiconductor power devices represented by silicon carbide (SiC) MOSFETs have advantages such as high-frequency switching, high-temperature operation, and low losses. Currently, they have gradually replaced Si IGBTs and are widely used in fields such as electric traction, photovoltaic power generation, and smart grids. In high-power applications, the demand for high-capacity power modules is increasing continuously, which requires the use of multiple parallel-connected SiC MOSFET chips. A smaller capacitance means that the SiC MOSFET can achieve a higher switching speed, which makes the SiC MOSFET sensitive to the parasitic inductance of the package. A higher parasitic inductance will cause the voltage peak between devices to increase during the switching transient, reducing the system efficiency and electromagnetic interference problems. When the power loop design in a multi-chip power module is asymmetric, the parasitic inductances of the parallel-connected chips may be different, resulting in current imbalance between the chips. As SiC devices have a much faster switching speed than Si IGBTs, this phenomenon is even more serious. The chip subjected to a large current will exhibit greater switching losses, leading to a higher junction temperature and posture.

[0003] Therefore, for a parallel multi-chip SiC MOSFET module, low loop inductance and balanced parasitic inductance of parallel branches are crucial issues, which helps to fully utilize the high switching speed advantage of SiC power devices. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-power low-stray SiC MOSFET module to solve the problem of current imbalance between chips caused by module stray and parasitic inductance.

[0005] The present invention solves the above technical problems through the following technical solutions: A high-power low-stray SiC MOSFET module includes a bottom ceramic substrate, a top ceramic substrate, and first SiC MOSFET chips and second SiC MOSFET chips of multiple bridge arms; the first SiC MOSFET chip of each bridge arm is the power chip of its upper bridge arm, and the second SiC MOSFET chip of each bridge arm is the power chip of its lower bridge arm; Each first SiC MOSFET chip corresponds to a set of DC+ copper-clad areas, gate copper-clad areas, source copper-clad areas, DC+ connection terminals, gate connection terminals, and source connection terminals. The drain of the first SiC MOSFET chip is connected to the corresponding DC+ copper-clad area, its gate is connected to the corresponding gate copper-clad area, and its source is connected to the corresponding source copper-clad area. The DC+ connection terminal, gate connection terminal, and source connection terminal are respectively arranged on the corresponding DC+ copper-clad area, gate copper-clad area, and source copper-clad area; Each second SiC MOSFET chip corresponds to a set of DC- copper-clad areas, gate copper-clad areas, source copper-clad areas, DC- connection terminals, gate connection terminals, and source connection terminals. The gate of the second SiC MOSFET chip is connected to the corresponding gate copper-clad area, and its source is connected to the corresponding source copper-clad area and DC- copper-clad area. The DC- connection terminal, gate connection terminal, and source connection terminal are respectively arranged on the corresponding DC- copper-clad area, gate copper-clad area, and source copper-clad area; For each bridge arm numbered in sequence, the first SiC MOSFET chips and second SiC MOSFET chips of the bridge arms with odd numbers are symmetrically arranged on the bottom ceramic substrate, and the DC+ copper-clad area, gate copper-clad area, source copper-clad area corresponding to the first SiC MOSFET chip and the gate copper-clad area, source copper-clad area corresponding to the second SiC MOSFET chip are arranged on the bottom ceramic substrate; the first SiC MOSFET chips and second SiC MOSFET chips of the bridge arms with even numbers are symmetrically arranged on the top ceramic substrate, and the DC+ copper-clad area, gate copper-clad area, source copper-clad area corresponding to the first SiC MOSFET chip and the gate copper-clad area, source copper-clad area corresponding to the second SiC MOSFET chip are arranged on the top ceramic substrate; the (i + 1)-th bridge arm is located between the i-th bridge arm and the (i + 2)-th bridge arm; A first AC copper-clad area is provided on the bottom ceramic substrate, and a first AC connection terminal is provided in the first AC copper-clad area; a second AC copper-clad area is provided on the top ceramic substrate, and a second AC connection terminal is provided in the second AC copper-clad area; the source of the first SiC MOSFET chip of the bridge arms with odd numbers is further connected to the second AC copper-clad area, the drain of the second SiC MOSFET chip of the bridge arms with odd numbers is further connected to the first AC copper-clad area, the source of the first SiC MOSFET chip of the bridge arms with even numbers is further connected to the first AC copper-clad area, and the drain of the second SiC MOSFET chip of the bridge arms with even numbers is further connected to the second AC copper-clad area; the DC- copper-clad area corresponding to the second SiC MOSFET chip of the bridge arms with odd numbers is arranged on the top ceramic substrate, and the DC- copper-clad area corresponding to the second SiC MOSFET chip of the bridge arms with even numbers is arranged on the bottom ceramic substrate; All the DC+ copper-clad areas are connected together, all the DC- copper-clad areas are connected together, and the first AC copper-clad area is connected to the second AC copper-clad area.

[0006] First, through the multi-dimensional encapsulation structure optimization of the internal layout of the module, the present invention improves the electromagnetic distribution of each SiCMOSFET chip, thereby suppressing the parasitic effect of the module and curbing the influence of the spatial distribution parameters on the high-speed switching performance of the SiC MOSFET. Second, for the problem of uneven conduction current distribution of the parallel SiC MOSFET chips caused by the inconsistency of the internal parasitic resistance and inductance parameters of the parallel SiC MOSFET chips, the present invention realizes the balanced conduction current distribution of the parallel SiC MOSFET chips by adjusting the layout of the copper-clad areas.

[0007] Further, the drain of each first SiC MOSFET chip is fixedly connected to the corresponding DC+ copper-clad area by welding or sintering; the source of each first SiC MOSFET chip is fixedly connected to the corresponding first AC copper-clad area or the second AC copper-clad area by welding or sintering; The gate of each first SiC MOSFET chip is connected to the corresponding gate copper-clad area by a metal bonding wire, and the source of each first SiC MOSFET chip is connected to the corresponding source copper-clad area by a metal bonding wire.

[0008] Further, the drain of each second SiC MOSFET chip is fixedly connected to the corresponding first AC copper-clad area or the second AC copper-clad area by welding or sintering; the source of each second SiC MOSFET chip is fixedly connected to the corresponding DC- copper-clad area by welding or sintering; The gate of each second SiC MOSFET chip is connected to the corresponding gate copper-clad area by a metal bonding wire, and the source of each second SiC MOSFET chip is connected to the corresponding source copper-clad area by a metal bonding wire.

[0009] Further, the DC+ terminal is welded to the corresponding DC+ copper-clad area, the DC- terminal is welded to the corresponding DC- copper-clad area, the gate terminal is welded to the corresponding gate copper-clad area, the source terminal is welded to the corresponding source copper-clad area, the first AC terminal is welded to the first AC copper-clad area, and the second AC terminal is welded to the second AC copper-clad area.

[0010] Further, all the DC+ copper-clad areas are connected together by molybdenum sheets, all the DC- copper-clad areas are connected together by molybdenum sheets, and the first AC copper-clad area is connected to the second AC copper-clad area by a molybdenum sheet.

[0011] Further, the drain of the first SiC MOSFET chip is provided on the lower surface of the first SiC MOSFET chip, and the gate and source are provided on the upper surface of the first SiC MOSFET chip; The drain of the second SiC MOSFET chip is provided on the lower surface of the second SiC MOSFET chip, and the gate and source are provided on the upper surface of the second SiC MOSFET chip.

[0012] Further, both the bottom ceramic substrate and the top ceramic substrate are DBC ceramic substrates.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: The SiC MOSFET module of the present invention adopts a double-layer structure. The power circuit starts from the DC+ terminal, is led to the SiC MOSFET chip (i.e., the first SiC MOSFET chip) of the upper bridge arm through the DC+ copper-clad area, then is led to the SiC MOSFET chip (i.e., the second SiC MOSFET chip) of the lower bridge arm and the DC- copper-clad area through the AC copper-clad area, and finally reaches the DC- terminal, realizing multi-dimensional interleaving of the power circuits between the SiC MOSFET chips and reducing the loop inductance; based on the fact that the current directions of the branches where each adjacent parallel SiC MOSFET chips are located are opposite, using the mutual coupling relationship of the inductances between the branches, the parasitic inductance of each branch is reduced, and the current imbalance problem is improved.

[0014] The SiC MOSFET module of the present invention has double-sided heat dissipation ability, improves the power density of the module, and has the advantages of compact space and simple assembly. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only one embodiment of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 is the circuit schematic diagram of the high-power low-stray SiC MOSFET module in the embodiment of the present invention; Figure 2 is the package structure diagram of the high-power low-stray SiC MOSFET module in the embodiment of the present invention; Figure 3 is the layout schematic diagram of the bottom ceramic substrate in the embodiment of the present invention; Figure 4 is the layout schematic diagram of the top ceramic substrate in the embodiment of the present invention.

[0017] Description of the reference numerals: 1 - bottom ceramic substrate, 2 - top ceramic substrate, 3 - first AC copper-clad area, 4 - first DC+ copper-clad area, 5 - G1 copper-clad area, 6 - S1 copper-clad area, 7 - G4 copper-clad area, 8 - S4 copper-clad area, 9 - third DC+ copper-clad area, 10 - G3 copper-clad area, 11 - S3 copper-clad area, 12 - G6 copper-clad area, 13 - S6 copper-clad area, 14 - second DC- copper-clad area, 15 - first DC+ terminal, 16 - G1 terminal, 17 - G4 terminal, 18 - S4 terminal, 19 - third DC+ terminal, 20 - G3 terminal, 21 - S3 terminal, 22 - G6 terminal, 23 - S6 terminal, 24 - second DC- terminal, 25 - first AC terminal, 26 - S1 terminal, 27 - second AC copper-clad area, 28 - second DC+ copper-clad area, 29 - S2 copper-clad area, 30 - G2 copper-clad area, 31 - first DC- copper-clad area, 32 - S5 copper-clad area, 33 - G5 copper-clad area, 34 - third DC- copper-clad area, 35 - third DC- terminal, 36 - S2 terminal, 37 - G2 terminal, 38 - second DC+ terminal, 39 - first DC- terminal, 40 - S5 terminal, 41 - G5 terminal. Detailed implementation manners

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0019] The technical solutions of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0020] As Figure 1As shown in the figure, the high-power and low-spurious SiC MOSFET module of this embodiment includes three bridge arms, and each bridge arm is composed of two series-connected SiC MOSFET chips. If the three bridge arms are numbered in sequence, the first bridge arm includes SiC MOSFET chip Q1 and SiC MOSFET chip Q4, the second bridge arm includes SiC MOSFET chip Q2 and SiC MOSFET chip Q5, and the third bridge arm includes SiC MOSFET chip Q3 and SiC MOSFET chip Q6. Among them, SiC MOSFET chip Q1, SiC MOSFET chip Q2, and SiC MOSFET chip Q3 are the power chips of the upper bridge arm, that is, the first SiC MOSFET chip of the corresponding bridge arm, and SiC MOSFET chip Q4, SiC MOSFET chip Q5, and SiC MOSFET chip Q6 are the power chips of the lower bridge arm, that is, the second SiC MOSFET chip of the corresponding bridge arm.

[0021] As Figures 2 to 4 shown in the figure, the high-power and low-spurious SiC MOSFET module provided by the present invention includes a bottom ceramic substrate 1, a top ceramic substrate 2, SiC MOSFET chip Q1, SiC MOSFET chip Q4, SiC MOSFET chip Q2, SiC MOSFET chip Q5, SiC MOSFET chip Q3, and SiC MOSFET chip Q6.

[0022] The upper surface of SiC MOSFET chip Q1 is provided with a gate and a source, and the lower surface is provided with a drain. SiC MOSFET chip Q1 corresponds to the first DC+ copper-clad area 4, G1 copper-clad area 5 (i.e., gate copper-clad area), S1 copper-clad area 6 (i.e., source copper-clad area), the first DC+ wiring terminal 15, G1 wiring terminal 16 (i.e., gate wiring terminal), and S1 wiring terminal 26 (i.e., source wiring terminal). The drain of SiC MOSFET chip Q1 is connected to the first DC+ copper-clad area 4, its gate is connected to the G1 copper-clad area 5, its source is connected to the S1 copper-clad area 6, and the first DC+ wiring terminal 15, G1 wiring terminal 16, and S1 wiring terminal 26 are respectively arranged on the first DC+ copper-clad area 4, G1 copper-clad area 5, and S1 copper-clad area 6.

[0023] The upper surface of the SiC MOSFET chip Q2 is provided with a gate and a source, and the lower surface is provided with a drain. The SiC MOSFET chip Q2 corresponds to the second DC+ copper-clad area 28, G2 copper-clad area 30, S2 copper-clad area 29, second DC+ terminal 38, G2 terminal 37, and S2 terminal 36. The drain of the SiC MOSFET chip Q2 is connected to the second DC+ copper-clad area 28, its gate is connected to the G2 copper-clad area 30, its source is connected to the S2 copper-clad area 29, and the second DC+ terminal 38, G2 terminal 37, and S2 terminal 36 are respectively arranged on the second DC+ copper-clad area 28, G2 copper-clad area 30, and S2 copper-clad area 29.

[0024] The upper surface of the SiC MOSFET chip Q3 is provided with a gate and a source, and the lower surface is provided with a drain. The SiC MOSFET chip Q3 corresponds to the third DC+ copper-clad area 9, G3 copper-clad area 10, S3 copper-clad area 11, third DC+ terminal 19, G3 terminal 20, and S3 terminal 21. The drain of the SiC MOSFET chip Q3 is connected to the third DC+ copper-clad area 9, its gate is connected to the G3 copper-clad area 10, its source is connected to the S3 copper-clad area 11, and the third DC+ terminal 19, G3 terminal 20, and S3 terminal 21 are respectively arranged on the third DC+ copper-clad area 9, G3 copper-clad area 10, and S3 copper-clad area 11.

[0025] The upper surface of the SiC MOSFET chip Q4 is provided with a gate and a source, and the lower surface is provided with a drain. The SiC MOSFET chip Q4 corresponds to the first DC- copper-clad area 31, G4 copper-clad area 7, S4 copper-clad area 8, first DC- terminal 39, G4 terminal 17, and S4 terminal 18. The gate of the SiC MOSFET chip Q4 is connected to the G4 copper-clad area 7, its source is connected to the S4 copper-clad area 8 and the first DC- copper-clad area 31, and the first DC- terminal 39, G4 terminal 17, and S4 terminal 18 are respectively arranged on the first DC- copper-clad area 31, G4 copper-clad area 7, and S4 copper-clad area 8.

[0026] The upper surface of the SiC MOSFET chip Q5 is provided with a gate and a source, and the lower surface is provided with a drain. The SiC MOSFET chip Q5 corresponds to the second DC- copper-clad area 14, G5 copper-clad area 33, S5 copper-clad area 32, second DC- terminal 24, G5 terminal 41, and S5 terminal 40. The gate of the SiC MOSFET chip Q5 is connected to the G5 copper-clad area 33, its source is connected to the S5 copper-clad area 32 and the second DC- copper-clad area 14, and the second DC- terminal 24, G5 terminal 41, and S5 terminal 40 are respectively arranged on the second DC- copper-clad area 14, G5 copper-clad area 33, and S5 copper-clad area 32.

[0027] The upper surface of the SiC MOSFET chip Q6 is provided with a gate and a source, and the lower surface is provided with a drain. The SiC MOSFET chip Q6 corresponds to the third DC copper-clad area 34, the G6 copper-clad area 12, the S6 copper-clad area 13, the third DC connection terminal 35, the G6 connection terminal 22, and the S6 connection terminal 23. The gate of the SiC MOSFET chip Q6 is connected to the G6 copper-clad area 12, its source is connected to the S6 copper-clad area 13 and the third DC copper-clad area 34, and the third DC connection terminal 35, the G6 connection terminal 22, and the S6 connection terminal 23 are respectively arranged on the third DC copper-clad area 34, the G6 copper-clad area 12, and the S6 copper-clad area 13.

[0028] As Figure 3 shown, the SiC MOSFET chips Q1 and Q4 of the first bridge arm are symmetrically arranged on the bottom ceramic substrate 1, and the first DC+ copper-clad area 4, the G1 copper-clad area 5, the S1 copper-clad area 6, the G4 copper-clad area 7, and the S4 copper-clad area 8 are arranged on the bottom ceramic substrate 1. The SiC MOSFET chips Q3 and Q6 of the third bridge arm are symmetrically arranged on the bottom ceramic substrate 1, and the third DC+ copper-clad area 9, the G3 copper-clad area 10, the S3 copper-clad area 11, the G6 copper-clad area 12, and the S6 copper-clad area 13 are arranged on the bottom ceramic substrate 1.

[0029] As Figure 4 shown, the SiC MOSFET chips Q2 and Q5 of the second bridge arm are symmetrically arranged on the top ceramic substrate 2, and the second DC+ copper-clad area 28, the G2 copper-clad area 30, the S2 copper-clad area 29, the G5 copper-clad area 33, and the S5 copper-clad area 32 are arranged on the top ceramic substrate 2.

[0030] As Figure 3 and Figure 4 shown, the second bridge arm is located between the first bridge arm and the third bridge arm.

[0031] As Figure 3 shown, a first AC copper-clad area 3 is provided on the bottom ceramic substrate 1, and a first AC connection terminal 25 is provided on the first AC copper-clad area 3. As Figure 4As shown, a second AC copper-clad area 27 is provided on the top ceramic substrate 2, and a second AC terminal is provided in the second AC copper-clad area 27. The sources of the SiC MOSFET chips Q1 and Q3 are also connected to the second AC copper-clad area 27. The drains of the SiC MOSFET chips Q4 and Q6 are also connected to the first AC copper-clad area 3. The source of the SiC MOSFET chip Q2 is connected to the first AC copper-clad area 3. The drain of the SiC MOSFET chip Q5 is connected to the second AC copper-clad area 27. The first DC - copper-clad area 31 and the third DC - copper-clad area 34 are provided on the top ceramic substrate 2, and the second DC - copper-clad area 14 is provided on the bottom ceramic substrate 1.

[0032] The first DC + copper-clad area 4, the second DC + copper-clad area 28, and the third DC + copper-clad area 9 are connected together to realize the parallel connection of the SiC MOSFET chips Q1, Q2, and Q3, forming the upper bridge arm of the half-bridge circuit; the first DC - copper-clad area 31, the second DC - copper-clad area 14, and the third DC - copper-clad area 34 are connected together to realize the parallel connection of the SiC MOSFET chips Q4, Q5, and Q6, forming the lower bridge arm of the half-bridge circuit; the first AC copper-clad area 3 is connected to the second AC copper-clad area 27 to realize the series connection of the upper bridge arm and the lower bridge arm.

[0033] In the SiC MOSFET module, the power loop starts from the DC + terminal, is led to the SiC MOSFET chips of the upper bridge arm through the DC + copper-clad area, then is led to the SiC MOSFET chips of the lower bridge arm and the DC - copper-clad area through the AC copper-clad area, and finally reaches the DC - terminal. From the perspective of parasitic inductance, the double-layer three-dimensional packaging structure composed of the bottom ceramic substrate 1 and the top ceramic substrate 2 can overlap the power loop of the entire module, realizing the multi-dimensional interleaving of the power loops between the SiC MOSFET chips, reducing the loop inductance; by virtue of the fact that the current directions of the branches where each adjacent parallel SiC MOSFET chips are located are opposite, the mutual coupling relationship of the inductances between the branches is used to reduce the parasitic inductance of each branch, improving the current imbalance problem.

[0034] Compared with the traditional packaging structure, the present invention optimizes the multi-dimensional packaging structure of the internal layout of the module, improves the electromagnetic distribution of each SiC MOSFET chip, thereby suppressing the parasitic effect of the module and curbing the influence of the spatial distribution parameters on the high-speed switching performance of the SiC MOSFET; secondly, for the problem of uneven conduction current distribution of the parallel SiC MOSFET chips caused by the inconsistency of the internal parasitic resistance and inductance parameters of the parallel SiC MOSFET chips, the present invention realizes the balanced conduction current distribution of the parallel SiC MOSFET chips by adjusting the layout of the copper-clad area. The packaging structure provided by the present invention can obtain better performance at a lower cost, has double-sided heat dissipation ability, improves the power density of the module, and has the characteristics of compact space and simple assembly.

[0035] In a specific embodiment of the present invention, the drain of the SiC MOSFET chip Q1 is fixedly connected to the first DC+ copper-clad area 4 by welding or sintering, and the source of the SiC MOSFET chip Q1 is fixedly connected to the second AC copper-clad area 27 by welding or sintering; the gate of the SiC MOSFET chip Q1 is connected to the G1 copper-clad area 5 by a bonding wire, and the source of the SiC MOSFET chip Q1 is connected to the S1 copper-clad area 6 by a bonding wire.

[0036] The drain of the SiC MOSFET chip Q2 is fixedly connected to the second DC+ copper-clad area 28 by welding or sintering, and the source of the SiC MOSFET chip Q2 is fixedly connected to the first AC copper-clad area 3 by welding or sintering; the gate of the SiC MOSFET chip Q2 is connected to the G2 copper-clad area 30 by a bonding wire, and the source of the SiC MOSFET chip Q2 is connected to the S2 copper-clad area 29 by a bonding wire.

[0037] The drain of the SiC MOSFET chip Q3 is fixedly connected to the third DC+ copper-clad area 9 by welding or sintering, and the source of the SiC MOSFET chip Q3 is fixedly connected to the second AC copper-clad area 27 by welding or sintering; the gate of the SiC MOSFET chip Q3 is connected to the G3 copper-clad area 10 by a bonding wire, and the source of the SiC MOSFET chip Q3 is connected to the S3 copper-clad area 11 by a bonding wire.

[0038] The drain of the SiC MOSFET chip Q4 is fixedly connected to the first AC copper-clad area 3 by welding or sintering, and the source of the SiC MOSFET chip Q4 is fixedly connected to the first DC- copper-clad area 31 by welding or sintering; the gate of the SiC MOSFET chip Q4 is connected to the G4 copper-clad area 7 by a bonding wire, and the source of the SiC MOSFET chip Q4 is connected to the S4 copper-clad area 8 by a bonding wire.

[0039] The drain of the SiC MOSFET chip Q5 is fixedly connected to the second AC copper-clad area 27 by soldering or sintering, and the source of the SiC MOSFET chip Q5 is fixedly connected to the second DC - copper-clad area 14 by soldering or sintering; the gate of the SiC MOSFET chip Q5 is connected to the G5 copper-clad area 33 by a bonding wire, and the source of the SiC MOSFET chip Q5 is connected to the S5 copper-clad area 32 by a bonding wire.

[0040] The drain of the SiC MOSFET chip Q6 is fixedly connected to the first AC copper-clad area 3 by soldering or sintering, and the source of the SiC MOSFET chip Q6 is fixedly connected to the third DC - copper-clad area 34 by soldering or sintering; the gate of the SiC MOSFET chip Q6 is connected to the G6 copper-clad area 12 by a bonding wire, and the source of the SiC MOSFET chip Q6 is connected to the S6 copper-clad area 13 by a bonding wire.

[0041] In a specific embodiment of the present invention, the first DC+ terminal 15 is soldered to the first DC+ copper-clad area 4, the second DC+ terminal 38 is soldered to the second DC+ copper-clad area 28, and the third DC+ terminal 19 is soldered to the third DC+ copper-clad area 9.

[0042] The first DC- terminal 39 is soldered to the first DC- copper-clad area 31, the second DC- terminal 24 is soldered to the second DC- copper-clad area 14, and the third DC- terminal 35 is soldered to the third DC- copper-clad area 34.

[0043] The G1 terminal 16 is soldered to the G1 copper-clad area 5, and the S1 terminal 26 is soldered to the S1 copper-clad area 6; the G2 terminal 37 is soldered to the G2 copper-clad area 30, and the S2 terminal 36 is soldered to the S2 copper-clad area 29; the G3 terminal 20 is soldered to the G3 copper-clad area 10, and the S3 terminal 21 is soldered to the S3 copper-clad area 11; the G4 terminal 17 is soldered to the G4 copper-clad area 7, and the S4 terminal 18 is soldered to the S4 copper-clad area 8; the G5 terminal 41 is soldered to the G5 copper-clad area 33, and the S5 terminal 40 is soldered to the S5 copper-clad area 32; the G6 terminal 22 is soldered to the G6 copper-clad area 12, and the S6 terminal 23 is soldered to the S6 copper-clad area 13.

[0044] The first AC terminal 25 is soldered to the first AC copper-clad area 3, and the second AC terminal is soldered to the second AC copper-clad area 27.

[0045] In a specific embodiment of the present invention, the first DC+ copper-clad area 4, the second DC+ copper-clad area 28, and the third DC+ copper-clad area 9 are connected together by molybdenum sheets; the first DC- copper-clad area 31, the second DC- copper-clad area 14, and the third DC- copper-clad area 34 are connected together by molybdenum sheets; the first AC copper-clad area 3 and the second AC copper-clad area 27 are connected by molybdenum sheets.

[0046] In a specific embodiment of the present invention, both the bottom ceramic substrate 1 and the top ceramic substrate 2 are DBC ceramic substrates.

[0047] For a high-power low-stray SiC MOSFET module including four bridge arms, two SiC MOSFET chips of the first bridge arm and the third bridge arm are symmetrically arranged on the bottom ceramic substrate, and two SiC MOSFET chips of the second bridge arm and the fourth bridge arm are symmetrically arranged on the top ceramic substrate. The second bridge arm is located between the first bridge arm and the third bridge arm, and the third bridge arm is located between the second bridge arm and the fourth bridge arm.

[0048] The above-disclosed are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or variations, which should all be covered within the protection scope of the present invention.

Claims

1. A high-power and low-spurious SiC MOSFET module, characterized in that: The module includes a bottom ceramic substrate, a top ceramic substrate, first SiC MOSFET chips and second SiC MOSFET chips of multiple bridge arms; the first SiC MOSFET chip of each bridge arm is the power chip of its upper bridge arm, and the second SiC MOSFET chip of each bridge arm is the power chip of its lower bridge arm; Each first SiC MOSFET chip corresponds to a set of DC+ copper-clad areas, gate copper-clad areas, source copper-clad areas, DC+ terminals, gate terminals and source terminals. The drain of the first SiC MOSFET chip is connected to the corresponding DC+ copper-clad area, its gate is connected to the corresponding gate copper-clad area, and its source is connected to the corresponding source copper-clad area. The DC+ terminal, gate terminal and source terminal are respectively arranged on the corresponding DC+ copper-clad area, gate copper-clad area and source copper-clad area; Each second SiC MOSFET chip corresponds to a set of DC- copper-clad areas, gate copper-clad areas, source copper-clad areas, DC- terminals, gate terminals and source terminals. The gate of the second SiC MOSFET chip is connected to the corresponding gate copper-clad area, and its source is connected to the corresponding source copper-clad area and DC- copper-clad area. The DC- terminal, gate terminal and source terminal are respectively arranged on the corresponding DC- copper-clad area, gate copper-clad area and source copper-clad area; For each bridge arm numbered in sequence, the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm with an odd number are symmetrically arranged on the bottom ceramic substrate, and the DC+ copper-clad area, gate copper-clad area, source copper-clad area corresponding to the first SiC MOSFET chip and the gate copper-clad area, source copper-clad area corresponding to the second SiC MOSFET chip are arranged on the bottom ceramic substrate; the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm with an even number are symmetrically arranged on the top ceramic substrate, and the DC+ copper-clad area, gate copper-clad area, source copper-clad area corresponding to the first SiC MOSFET chip and the gate copper-clad area, source copper-clad area corresponding to the second SiC MOSFET chip are arranged on the top ceramic substrate; the (i + 1)-th bridge arm is located between the i-th bridge arm and the (i + 2)-th bridge arm; A first AC copper-clad area is provided on the underlying ceramic substrate, and a first AC terminal is provided in the first AC copper-clad area; a second AC copper-clad area is provided on the top ceramic substrate, and a second AC terminal is provided in the second AC copper-clad area; the source electrode of the first SiC MOSFET chip of the odd-numbered bridge arm is also connected to the second AC copper-clad area, and the drain electrode of the second SiC MOSFET chip of the odd-numbered bridge arm is also connected to the first AC copper-clad area; the source electrode of the first SiC MOSFET chip of the even-numbered bridge arm is also connected to the first AC copper-clad area, and the drain electrode of the second SiC MOSFET chip of the even-numbered bridge arm is also connected to the second AC copper-clad area; the DC copper-clad area corresponding to the second SiC MOSFET chip of the odd-numbered bridge arm is provided on the top ceramic substrate, and the DC copper-clad area corresponding to the second SiC MOSFET chip of the even-numbered bridge arm is provided on the underlying ceramic substrate; All the DC+ copper-clad areas are connected together, all the DC- copper-clad areas are connected together, and the first AC copper-clad area is connected to the second AC copper-clad area.

2. The high-power and low-spurious SiC MOSFET module according to claim 1, wherein: The drain electrode of each first SiC MOSFET chip is fixedly connected to the corresponding DC+ copper-clad area by welding or sintering; the source electrode of each first SiC MOSFET chip is fixedly connected to the corresponding first AC copper-clad area or second AC copper-clad area by welding or sintering; The gate electrode of each first SiC MOSFET chip is connected to the corresponding gate copper-clad area by a metal bonding wire, and the source electrode of each first SiC MOSFET chip is connected to the corresponding source copper-clad area by a metal bonding wire.

3. The high-power and low-spurious SiC MOSFET module according to claim 1, wherein: The drain electrode of each second SiC MOSFET chip is fixedly connected to the corresponding first AC copper-clad area or second AC copper-clad area by welding or sintering; the source electrode of each second SiC MOSFET chip is fixedly connected to the corresponding DC- copper-clad area by welding or sintering; The gate electrode of each second SiC MOSFET chip is connected to the corresponding gate copper-clad area by a metal bonding wire, and the source electrode of each second SiC MOSFET chip is connected to the corresponding source copper-clad area by a metal bonding wire.

4. The high-power and low-spurious SiC MOSFET module according to claim 1, characterized in that: The DC+ terminal is welded to the corresponding DC+ copper-clad area, the DC- terminal is welded to the corresponding DC- copper-clad area, the gate terminal is welded to the corresponding gate copper-clad area, the source terminal is welded to the corresponding source copper-clad area, the first AC terminal is welded to the first AC copper-clad area, and the second AC terminal is welded to the second AC copper-clad area.

5. The high-power and low-spurious SiC MOSFET module according to claim 1, characterized in that: All the DC+ copper-clad areas are connected together by molybdenum sheets, all the DC- copper-clad areas are connected together by molybdenum sheets, and the first AC copper-clad area is connected to the second AC copper-clad area by a molybdenum sheet.

6. The high-power and low-spurious SiC MOSFET module according to claim 1, characterized in that: The drain electrode of the first SiC MOSFET chip is provided on the lower surface of the first SiC MOSFET chip, and the gate electrode and the source electrode are provided on the upper surface of the first SiC MOSFET chip; The drain of the second SiC MOSFET chip is provided on the lower surface of the second SiC MOSFET chip, and the gate and source are provided on the upper surface of the second SiC MOSFET chip.

7. The high-power and low-spurious SiC MOSFET module according to any one of claims 1 to 6, characterized in that: Both the bottom ceramic substrate and the top ceramic substrate are DBC ceramic substrates.

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