Optoelectronic integrated chip and optical interconnection structure

Abstract

The embodiment of the invention relates to a photoelectric integrated chip and an optical interconnection structure. The photoelectric integrated chip comprises a first electric chip used for providing a driving signal; the first connecting layer is arranged on one side of the first electric chip, is electrically connected with the first electric chip and is used for transmitting a driving signal; the VCSEL array is arranged on one side, far away from the first electric chip, of the first connecting layer, is electrically connected with the first connecting layer and is used for emitting light under the action of a driving signal; wherein the light emitting direction of the VCSEL array is parallel to the stacking direction of the first electric chip, the first connecting layer and the VCSEL array.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical communication technologies, and in particular, to an optoelectronic integrated chip and an optical interconnection structure. Background Art

[0002] Optical communication is a communication method that uses light waves as carriers and optical fibers or the atmosphere as transmission media to achieve information transmission. The basic principle of optical communication is to convert an electrical signal into an optical signal, transmit it through a transmission medium, and then convert the optical signal back into an electrical signal at the receiving end. Therefore, optical communication has an extremely high transmission bandwidth and can meet the transmission requirements of a large amount of data. However, the existing optical emission modules used to support optical communication are relatively large in size and cannot meet the usage requirements of users. Summary of the Invention

[0003] Based on this, it is necessary to provide an optoelectronic integrated chip and an optical interconnection structure for the above technical problems.

[0004] In a first aspect, the present application provides an optoelectronic integrated chip, including:

[0005] A first electrical chip for providing a driving signal;

[0006] A first connection layer disposed on one side of the first electrical chip and electrically connected to the first electrical chip for transmitting the driving signal;

[0007] A VCSEL array disposed on a side of the first connection layer away from the first electrical chip and electrically connected to the first connection layer for emitting light under the action of the driving signal;

[0008] Wherein, the light emission direction of the VCSEL array is parallel to the stacking direction of the first electrical chip, the first connection layer, and the VCSEL array.

[0009] In one embodiment, the first connection layer includes:

[0010] A silicon dielectric plate, in which a plurality of through holes are provided, and the through holes extend from a first surface of the silicon dielectric plate to a second surface; the first surface is the surface of the silicon dielectric plate close to the first electrical chip, and the second surface is the surface of the silicon dielectric plate close to the VCSEL array;

[0011] Wherein, one end of the through hole is electrically connected to the first electrical chip through a micro bump, and the other end of the through hole is electrically connected to the VCSEL array through a micro bump.

[0012] In one embodiment, it further includes a redistribution layer disposed between the silicon dielectric plate and the first electrical chip, and the redistribution layer is electrically connected to the vias in the silicon dielectric plate and the first electrical chip respectively; or

[0013] The redistribution layer is disposed between the silicon dielectric plate and the VCSEL array, and the redistribution layer is electrically connected to the vias in the silicon dielectric plate and the VCSEL array respectively.

[0014] In one embodiment, the VCSEL array adopts a flip-chip structure, and the light-emitting direction of the VCSEL array is away from the first electrical chip.

[0015] In a second aspect, the present application provides an optical interconnection structure, including an optical emission module, an optical reception module, and an optical fiber for connecting the optical emission module and the optical reception module;

[0016] The optical emission module includes a first printed circuit board, a first encapsulation layer, and the optoelectronic integrated chip as described above which are stacked, and the first electrical chip of the optoelectronic integrated chip is electrically connected to the first encapsulation layer;

[0017] The optical reception module includes a second printed circuit board, a second encapsulation layer, a second electrical chip, a second connection layer, and a photodetector array. The second electrical chip is electrically connected to the second printed circuit board through the second encapsulation layer and is point-connected to the photodetector array through the second connection layer.

[0018] In one embodiment, the optical emission module further includes:

[0019] An optical path adjustment unit disposed between the VCSEL array and the optical fiber, and the optical path adjustment unit is used to adjust the optical path of the light beam from the VCSEL array so that the included angle between the outgoing light and the incident light of the optical path adjustment unit is 90°, so as to project the outgoing light onto the optical fiber.

[0020] In one embodiment, the optical path adjustment unit includes:

[0021] A first convex lens for receiving the light beam from the VCSEL array and emitting parallel light from the light-emitting surface of the first convex lens;

[0022] A first plane mirror disposed on the light-emitting side of the first convex lens, and the included angle between the first plane mirror and the optical axis of the first convex lens is 45°, and the first plane mirror is used to reflect the light beam from the first convex lens;

[0023] A second convex lens disposed on the light-emitting side of the first plane mirror for focusing the light beam from the first plane mirror and projecting it onto the optical fiber.

[0024] In one embodiment, the optical path adjusting unit includes:

[0025] A first convex lens for receiving the light beam from the VCSEL array and emitting parallel light through the light emitting surface of the first convex lens;

[0026] A first concave mirror disposed on the light emitting side of the first convex lens for reflecting the light beam from the first convex lens to the optical fiber.

[0027] In one embodiment, the first printed circuit board is electrically connected to the first encapsulation layer through solder balls, and the first encapsulation layer and the first electrical chip are electrically connected through bumps;

[0028] The second printed circuit board is electrically connected to the second encapsulation layer through solder balls, the second encapsulation layer and the second electrical chip are electrically connected through bumps, and the second electrical chip and the photodetector array are electrically connected through micro-bumps.

[0029] In one embodiment, it further includes:

[0030] A memory and a processor;

[0031] A third connection layer for connecting the memory and the first encapsulation layer and connecting the processor and the first encapsulation layer;

[0032] A switching chip electrically connected to the second encapsulation layer.

[0033] In the above-mentioned optoelectronic integrated chip and optical interconnection structure, by using a VCSEL array with an output light direction parallel to the stacking direction of the first electrical chip, the first connection layer, and the VCSEL array as the light source for optical communication, more lasers can be accommodated in the same planar space, thereby reducing the volume of the optoelectronic integrated chip and increasing the total transmission rate of the entire optoelectronic integrated packaging structure. In addition, compared with the solution of placing the VCSEL array below the first electrical chip, the first electrical chip does not block the light output path of the VCSEL array, thereby improving the light utilization rate of the VCSEL array, reducing losses, and improving the heat dissipation capacity of the optoelectronic integrated device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 One of the cross-sectional schematic diagrams of an optoelectronic integrated chip according to an embodiment;

[0036] Figure 2 Another cross-sectional schematic diagram of an optoelectronic integrated chip according to an embodiment;

[0037] Figure 3 One of the partial cross-sectional schematic diagrams of an optical interconnection structure according to an embodiment;

[0038] Figure 4 One of the structural schematic diagrams of an optical path adjustment unit according to an embodiment;

[0039] Figure 5 Another structural schematic diagram of an optical path adjustment unit according to an embodiment;

[0040] Figure 6 Another partial cross-sectional schematic diagram of an optical interconnection structure according to an embodiment;

[0041] Figure 7 Schematic diagram of the positions of a memory, a processor, and an optoelectronic integrated chip according to an embodiment;

[0042] Figure 8 Schematic diagram of the positions of an optoelectronic detection array and a switching chip according to an embodiment.

[0043] Description of component labels:

[0044] Optical emission module: 10; First electrical chip: 110; First connection layer: 120; Silicon dielectric plate: 121; Through hole: 122; VCSEL array: 130; First printed circuit board: 140; First encapsulation layer: 150; Optical path adjustment unit: 160; First convex lens: 161; First plane mirror: 162; Second convex lens: 163; First concave mirror: 164; Optical reception module: 20; Second electrical chip: 210; Second connection layer: 220; Optoelectronic detection array: 230; Second printed circuit board: 240; Second encapsulation layer: 250; Optical fiber: 30; Memory: 40; Processor: 50; Third connection layer: 60; Switching chip: 70. Detailed implementation manners

[0045] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various components, but these components are not limited by these terms. These terms are only used to distinguish a first component from another component. For example, without departing from the scope of this application, the first electronic chip may be referred to as the second electronic chip, and similarly, the second electronic chip may be referred to as the first electronic chip.

[0047] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. The meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. The meaning of "several" is at least one, such as one, two, etc., unless otherwise specifically defined.

[0048] The embodiments of this application provide an optoelectronic integrated chip applied to an optical interconnection structure to achieve the function of optical communication. Among them, the optical emission module is used to convert an electrical signal into an optical signal, and generally includes light sources such as semiconductor lasers and light-emitting diodes, and a modulator. The optical reception module is used to convert the received optical signal into an electrical signal, and perform processing such as amplification, demodulation, and decoding to recover the original information. The optical reception module generally includes photodetectors such as photodiodes and avalanche photodiodes, and an amplifier, a demodulator, etc.

[0049] In the field of optical communication technology, for short-distance communication scenarios, on the side of the optical emission module, a linear-drive pluggable optics (LPO) and a co-packaged optics (CPO) optical engine architecture can be adopted. The above two structures eliminate the traditional DSP or CDR devices used for long-distance signal recovery, so about 50% of the module power consumption is saved.

[0050] However, whether for pluggable optical modules or LPO optical modules, the mainstream packaging method for their internal optical engines is still COB (Chips on Board) packaging. COB packaging refers to bonding discrete incoming optical chips and electrical chips in a flip-chip manner on the surface of a PCB, and achieving electrical interconnection between chips and between chips and the PCB through Wire bonding using gold wires or aluminum wires. Taking the current common packaging standards of Quad SmallForm-factor Pluggable (QSFP) and Octal Small Form-factor Pluggable (OSFP) as examples, the width of the internal PCB is approximately between 17 mm and 19 mm. With the increase in module rate, the packaging space for internal optoelectronic chips has become very crowded, and wire bonding also occupies a large layout area, resulting in design complexity for chip mounting and internal wiring of the PCB.

[0051] The present application provides an optoelectronic integrated chip. Figure 1 One of the cross-sectional schematic diagrams of the optoelectronic integrated chip according to an embodiment, refer to Figure 1 , the optoelectronic integrated chip includes a first electrical chip 110, a first connection layer 120, and a laser.

[0052] Among them, the first connection layer 120 is disposed on one side of the first electrical chip 110, and the laser is disposed on the side of the first connection layer 120 away from the first electrical chip 110. That is, the first electrical chip 110, the first connection layer 120, and the laser are stacked. Compared with the method of setting the first electrical chip 110 and the laser on the same layer, the stacked first electrical chip 110 and the laser can effectively reduce the occupied area in the plane.

[0053] In the related art, an edge-emitting laser is usually used as the emission light source. However, due to the emission mode of the edge-emitting laser, the edge-emitting laser needs to be arranged in a linear pattern, and the arrangement quantity is strictly affected by the size of the optical interconnection structure, and the number of lasers will affect the total transmission rate of the optoelectronic integrated chip. This embodiment uses a vertical-cavity surface-emitting laser including multiple vertical-cavity surface-emitting lasers (Vertical-Cavity Surface-Emitting Laser). Since the light emission direction of the laser is parallel to the stacking direction of the first electrical chip 110, the first connection layer 120, and the laser, that is, the light emission direction of the laser is perpendicular to the light-emitting surface of the laser, more vertical-cavity surface-emitting lasers can be arranged in the optoelectronic integrated chip by making full use of the space, thereby improving the total transmission rate of the optoelectronic integrated chip.

[0054] The first electrical chip 110 is used to provide a driving signal. The first connection layer 120 is electrically connected to the first electrical chip 110 and is also electrically connected to the laser. The first connection layer 120 is used to transmit the driving signal provided by the first electrical chip 110 to the laser, and the laser is used to emit light under the action of the driving signal. Based on the stacked structure of the first electrical chip 110, the first connection layer 120, and the laser, the signal transmission path of the driving signal in this embodiment is shorter. Therefore, the loss and delay of the driving signal on the transmission path can be effectively reduced, thereby improving the accuracy of the driving signal.

[0055] In the embodiment of the application, by using a laser whose light-emitting direction is parallel to the stacking direction of the first electrical chip 110, the first connection layer 120, and the laser as the light source for optical communication, more lasers can be accommodated in the same planar space. Thus, the volume of the optoelectronic integrated chip can be reduced, and the total transmission rate of the entire optoelectronic integrated packaging structure can be increased. Additionally, compared with the solution of placing the laser below the first electrical chip 110, the first electrical chip 110 in this embodiment does not block the light-emitting path of the laser. Therefore, the light utilization rate of the laser can be increased, the loss can be reduced, and the heat dissipation capacity of the optoelectronic integrated device can be improved.

[0056] Figure 2 is a second cross-sectional schematic diagram of an optoelectronic integrated chip according to an embodiment. Refer to Figure 2 , in one of the embodiments, the first connection layer 120 includes a silicon dielectric plate 121. The silicon dielectric plate 121 is used to ensure the structural stability of the first connection layer 120 and can provide electrical insulation between the first electrical chip 110 and the VCSEL array 130 to ensure the reliable light emission of the VCSEL array 130. A plurality of through holes 122 are provided in the silicon dielectric plate 121, and the through holes 122 extend from the first surface of the silicon dielectric plate 121 to the second surface. The first surface is the surface of the silicon dielectric plate 121 close to the first electrical chip 110, and the second surface is the surface of the silicon dielectric plate 121 close to the VCSEL array 130. Among them, the diameter of the through hole 122 is from several micrometers to dozens of micrometers, and the through hole 122 is a vertical interconnection structure penetrating the silicon dielectric plate 121 to achieve electrical connection between the first electrical chip 110 and the VCSEL array 130. Therefore, the first connection layer 120 in this embodiment can also be referred to as a Through Silicon Via Interposer (TSV-interposer). The TSV-interposer with vertical interconnection function in the embodiment of the present application can, on the one hand, further shorten the signal transmission path between the first electrical chip 110 and the VCSEL array 130 to reduce the loss and delay of the driving signal on the transmission path, and on the other hand, can eliminate the in-plane wiring, which is beneficial to the high-density integration requirements of the optoelectronic integrated chip.

[0057] In one embodiment, one end of the through hole 122 is electrically connected to the first electrical chip 110 via micro-bumps, and the other end of the through hole 122 is electrically connected to the VCSEL array 130 via micro-bumps. Specifically, the size of the micro-bumps is generally between a few micrometers and dozens of micrometers, that is, the size of the micro-bumps corresponds to the size of the through hole 122. Therefore, by using micro-bumps to connect the first electrical chip 110 and the VCSEL array 130 located on both sides of the first connection layer 120, the distance between adjacent micro-bumps can meet the integration requirements of the optoelectronic integrated chip on the premise of ensuring no short circuit, and the volume of the optoelectronic integrated chip can be reduced.

[0058] In one embodiment, the optoelectronic integrated chip further includes a redistribution layer. Exemplarily, the redistribution layer is disposed between the silicon dielectric plate 121 and the first electrical chip 110, and the redistribution layer is electrically connected to the through hole 122 in the silicon dielectric plate 121 and the first electrical chip 110 respectively. Specifically, the redistribution layer can be electrically connected to the through hole 122 in the silicon dielectric plate 121 via micro-bumps and electrically connected to the first electrical chip 110 via bumps. Another exemplarily, the redistribution layer is disposed between the silicon dielectric plate 121 and the VCSEL array 130, and the redistribution layer is electrically connected to the through hole 122 in the silicon dielectric plate 121 and the VCSEL array 130 respectively. Specifically, the redistribution layer can be electrically connected to the through hole 122 in the silicon dielectric plate 121 via micro-bumps and electrically connected to the VCSEL array 130 via bumps. By providing the redistribution layer, the circuit routing can be optimized to meet the connection requirements between the first electrical chip 110 and the VCSEL array 130.

[0059] In one embodiment, the VCSEL array 130 adopts a flip-chip structure, and the light-emitting direction of the VCSEL array 130 is away from the first electrical chip 110. That is, for the VCSEL array 130, the driving signal comes from the side of the VCSEL array 130 facing the first electrical chip 110, and the light is emitted from the side away from the first electrical chip 110. In the related art, in the front-mounted structure where the driving signal source and the light emission are on the same side, the driving signal needs to be transmitted to the VCSEL array 130 through a conductive glass substrate. Therefore, the conductive glass substrate is also located on the light-emitting path of the VCSEL array 130, resulting in optical problems such as light absorption and optical path deflection. In this embodiment, since the flip-chip structure of the VCSEL array 130 is adopted, there is no obstruction of the conductive glass substrate on the light-emitting path, so the optical problems caused by the glass substrate can be improved. Moreover, since the glass substrate is cancelled, the entire optoelectronic integrated chip is thinner and more compact.

[0060] The embodiment of the present application also provides an optical interconnection structure. Figure 3 One of the partial cross-sectional schematic diagrams of the optical interconnection structure of an embodiment, refer to Figure 3, the optical interconnection structure includes an optical emission module 10, an optical reception module 20, and an optical fiber 30 for connecting the optical emission module 10 and the optical reception module 20. The structure including the optical emission module 10, the optical reception module 20, and the optical fiber 30 may also be referred to as an Optical Engine (OE).

[0061] Among them, the optical emission module 10 includes a first printed circuit board 140, a first encapsulation layer 150, and the optoelectronic integrated chip as described above, which are stacked. The first electrical chip 110 of the optoelectronic integrated chip is electrically connected to the first encapsulation layer 150. The optical reception module 20 includes a second printed circuit board 240, a second encapsulation layer 250, a second electrical chip 210, a second connection layer 220, and a photoelectric detection array 230, which are stacked. The second electrical chip 210 is electrically connected to the second printed circuit board 240 through the second encapsulation layer 250 and is dot-connected to the photoelectric detection array 230 through the second connection layer 220.

[0062] Specifically, both the first encapsulation layer 150 and the second encapsulation layer 250 are organic encapsulation layers. The organic encapsulation layer refers to an encapsulation layer based on materials such as epoxy resin and polyimide. The organic encapsulation layer can be well matched with the chip and the printed circuit board, thus playing a role in protecting the chip and providing electrical connection. The organic encapsulation layer also includes via structures and conductive lines to achieve the electrical signal transmission between the first electrical chip 110 and the first printed circuit board 140, and to achieve the electrical signal transmission between the second electrical chip 210 and the second printed circuit board 240.

[0063] In this embodiment, the second electrical chip 210, the second connection layer 220, and the photoelectric detection array 230 are stacked. Compared with the method of setting the second electrical chip 210 and the photoelectric detection array 230 on the same layer, the stacked second electrical chip 210 and the photoelectric detection array 230 can effectively reduce the occupied area in the plane. Moreover, the transmission path of the photo-induced signal output by the photoelectric detection array 230 in this embodiment is short, so the loss and delay of the photo-induced signal on the transmission path can be effectively reduced, thereby improving the accuracy of the photo-induced signal. Further, the photoelectric detection array 230 can be flip-chip arranged on the second electrical chip 210, so that the second electrical chip 210 does not block the light incident path of the photoelectric detection array 230, thereby improving the light utilization rate of the photoelectric detection array 230 and ensuring the reliable transmission of data.

[0064] In one embodiment, the first printed circuit board 140 is electrically connected to the first encapsulation layer 150 via solder balls, and the first encapsulation layer 150 and the first electrical chip 110 are electrically connected via bumps. The second printed circuit board 240 is electrically connected to the second encapsulation layer 250 via solder balls, the second encapsulation layer 250 and the second electrical chip 210 are electrically connected via bumps, and the second electrical chip 210 and the photoelectric detection array 230 are electrically connected via micro-bumps. Specifically, solder balls, bumps, and micro-bumps are all used to achieve electrical connection and mechanical fixation, and are key components to ensure that the optical interconnection structure can work properly and realize signal transmission and physical support. Among them, the diameter range of solder balls is usually between 0.25 mm and 0.76 mm, the diameter of bumps is usually between 100 μm and 150 μm, and the size of micro-bumps is the smallest, with a diameter even less than 2 μm. Based on different sizes, the difficulty of the preparation processes of solder balls, bumps, and micro-bumps gradually increases. Therefore, in this embodiment, different-sized connection structures are used between different structures, which can reduce the preparation difficulty of the optical interconnection structure on the premise of ensuring the reliability of electrical and mechanical connections, thereby improving the yield of the optical interconnection structure.

[0065] In one embodiment, the optical emission module 10 further includes an optical path adjustment unit 160. The optical path adjustment unit 160 is disposed between the VCSEL array 130 and the optical fiber 30. The optical path adjustment unit 160 is used to adjust the optical path of the light beam from the VCSEL array 130 so that the included angle between the outgoing light and the incident light of the optical path adjustment unit 160 is 90°, so as to project the outgoing light onto the optical fiber 30. In the embodiment of the application, by deflecting the transmission direction of the light beam through the optical path adjustment unit 160, the extending direction of the optical fiber 30 can be parallel to the light-emitting surface of the VCSEL array 130, reducing the influence of the setting of the optical fiber 30 on the longitudinal size of the optical interconnection structure, thereby realizing a compact layout of the optical interconnection structure.

[0066] Figure 4 is one of the schematic structural diagrams of the optical path adjustment unit 160 in an embodiment. Refer to Figure 4 In one embodiment, the optical path adjustment unit 160 includes a first convex lens 161, a first plane mirror 162, and a second convex lens 163. Among them, the first convex lens 161 is used to receive the light beam from the VCSEL array 130 and emit parallel light through the light-emitting surface of the first convex lens 161. The first plane mirror 162 is disposed on the light-emitting side of the first convex lens 161. The included angle between the first plane mirror 162 and the optical axis of the first convex lens 161 is 45°. The first plane mirror 162 is used to reflect the light beam from the first convex lens 161. The second convex lens 163 is disposed on the light-emitting side of the first plane mirror 162 and is used to focus the light beam from the first plane mirror 162 and project it onto the optical fiber 30.

[0067] Figure 5FIG. 2 is a second schematic structural diagram of the optical path adjustment unit 160 according to an embodiment. Refer to Figure 5 , in one embodiment, the optical path adjustment unit 160 includes a first convex lens 161 and a first concave mirror 164. The first convex lens 161 is configured to receive the light beam from the VCSEL array 130 and emit parallel light through the light-emitting surface of the first convex lens 161. The first concave mirror 164 is disposed on the light-emitting side of the first convex lens 161 and is configured to reflect the light beam from the first convex lens 161 to the optical fiber 30.

[0068] Figure 6 FIG. 2 is a second partial cross-sectional schematic diagram of the optical interconnection structure according to an embodiment. Refer to Figure 6 , in one embodiment, the optical interconnection structure further includes a memory 40, a processor 50, a third connection layer 60, and a switching chip 70. The third connection layer 60 is configured to connect the memory 40 and the first packaging layer 150, and connect the processor 50 and the first packaging layer 150. The switching chip 70 is electrically connected to the second packaging layer 250. The memory 40 and the processor 50 are connected to the first printed circuit board 140 through the first packaging layer 150, and the switching chip 70 is connected to the second printed circuit board 240 through the second packaging layer 250.

[0069] Specifically, the memory 40 is configured to store various configuration information required for optical communication, such as wavelength allocation, signal modulation mode, communication protocol parameters, etc. The memory 40 can also be used as a temporary storage area for data during the data transmission process of optical communication. For example, when the data generation speed at the sending end is relatively fast and the bandwidth of the transmission link is limited, the memory 40 can temporarily store this data to avoid data loss. At the receiving end, if the data processing speed cannot keep up with the receiving speed, the memory 40 can also cache the data to ensure the integrity of the data. The memory 40 is, for example, a High Bandwidth Memory (HBM). The high-bandwidth memory adopts a stacked 3D packaging technology, vertically stacks multiple DRAM chips together, and uses Through-Silicon Via 122 (TSV) technology to achieve high-speed interconnection between chips.

[0070] The processor 50 is configured to adjust working parameters such as the output power of the VCSEL array 130 in real time and process the electrical signals in the optical communication system. At the sending end, the processor 50 needs to perform operations such as encoding and modulation on the input raw data to convert it into a signal format suitable for optical transmission. At the receiving end, the processor 50 needs to perform operations such as decoding and demodulation on the electrical signals converted from the received optical signals to recover the raw data.

[0071] The switching chip 70 is used to implement data switching and forwarding. In an optical communication system, there are usually multiple nodes and links. The switching chip 70 can forward data from one input port to the corresponding output port according to the destination address of the data packet. For example, in the optical interconnection network of a data center, the switching chip 70 can quickly and accurately forward the data generated by a server to other servers or storage devices.

[0072] In the embodiments of the application, through the connection function of the third connection layer 60, the memory 40, the processor 50, and the switching chip 70 are integrated into the optical interconnection structure, which can further improve the function of the optical interconnection structure and enhance the integration degree of the optical interconnection structure.

[0073] Figure 7 FIG. is a schematic diagram of the positions of the memory 40, the processor 50, and the optoelectronic integrated chip in an embodiment. Refer to Figure 7 , the VCSEL array 130 is disposed on one side close to the photodetector array 230 to shorten the transmission path of the light beam. The memory 40 and the processor 50 are disposed on the side away from the photodetector array 230. The optical interconnection structure may include two memories 40, and the two memories 40 are respectively disposed on the opposite sides of the processor 50. Figure 8 FIG. is a schematic diagram of the positions of the photodetector array 230 and the switching chip 70 in an embodiment. Refer to Figure 8 , the orthographic projection of the switching chip 70 on the second printed circuit board 240 is located in the middle of the second printed circuit board 240, and multiple photodetector arrays 230 are respectively disposed on both sides of the second printed circuit board 240.

[0074] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0075] The above embodiments only represent several implementation manners of the embodiments of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application should be subject to the appended claims.

Claims

1. An optoelectronic integrated chip, characterized in that, Comprising: A first electrical chip for providing a driving signal; A first connection layer provided on one side of the first electrical chip and electrically connected to the first electrical chip for transmitting the driving signal; A VCSEL array provided on the side of the first connection layer away from the first electrical chip and electrically connected to the first connection layer for emitting light under the action of the driving signal; Wherein, the light emission direction of the VCSEL array is parallel to the stacking direction of the first electrical chip, the first connection layer, and the VCSEL array.

2. The optoelectronic integrated chip according to claim 1, wherein The first connection layer includes: A silicon dielectric plate having a plurality of through holes therein, the through holes extending from a first surface of the silicon dielectric plate to a second surface; the first surface is the surface of the silicon dielectric plate close to the first electrical chip side, and the second surface is the surface of the silicon dielectric plate close to the VCSEL array side; Wherein, one end of the through hole is electrically connected to the first electrical chip through a micro bump, and the other end of the through hole is electrically connected to the VCSEL array through a micro bump.

3. The optoelectronic integrated chip according to claim 2, characterized in that, Further comprising a redistribution layer; The redistribution layer is provided between the silicon dielectric plate and the first electrical chip, and the redistribution layer is electrically connected to the through holes in the silicon dielectric plate and the first electrical chip respectively; or The redistribution layer is provided between the silicon dielectric plate and the VCSEL array, and the redistribution layer is electrically connected to the through holes in the silicon dielectric plate and the VCSEL array respectively.

4. The optoelectronic integrated chip according to any one of claims 1 to 3, characterized in that The VCSEL array adopts a flip-chip structure, and the light emission direction of the VCSEL array is away from the first electrical chip.

5. An optical interconnection structure, characterized in that, Including an optical emission module, an optical reception module, and an optical fiber for connecting the optical emission module and the optical reception module; The optical emission module includes a first printed circuit board, a first encapsulation layer, and the optoelectronic integrated chip according to any one of claims 1 to 4 stacked, and the first electrical chip of the optoelectronic integrated chip is electrically connected to the first encapsulation layer; The optical reception module includes a second printed circuit board, a second encapsulation layer, a second electrical chip, a second connection layer, and a photodetector array, the second electrical chip is electrically connected to the second printed circuit board through the second encapsulation layer and is dot-connected to the photodetector array through the second connection layer.

6. The optical interconnection structure according to claim 5, characterized in that The optical emission module further includes: An optical path adjustment unit provided between the VCSEL array and the optical fiber, the optical path adjustment unit is used to adjust the optical path of the light beam from the VCSEL array so that the included angle between the outgoing light and the incident light of the optical path adjustment unit is 90°, so as to project the outgoing light onto the optical fiber.

7. The optical interconnection structure according to claim 6, wherein The optical path adjustment unit includes: A first convex lens for receiving the light beam from the VCSEL array and emitting parallel light through the light-emitting surface of the first convex lens; A first plane mirror provided on the light-emitting side of the first convex lens, the included angle between the first plane mirror and the optical axis of the first convex lens is 45°, and the first plane mirror is used to reflect the light beam from the first convex lens; A second convex lens, disposed on the light-emitting side of the first plane mirror, for focusing the light beam from the first plane mirror and projecting it onto the optical fiber.

8. The optical interconnection structure according to claim 6, wherein, The optical path adjustment unit includes: A first convex lens, for receiving the light beam from the VCSEL array and emitting parallel light from the light-emitting surface of the first convex lens; A first concave mirror, disposed on the light-emitting side of the first convex lens, for reflecting the light beam from the first convex lens to the optical fiber.

9. The optical interconnection structure according to claim 5, wherein The first printed circuit board is electrically connected to the first encapsulation layer through solder balls, and the first encapsulation layer and the first electrical chip are electrically connected through bumps; The second printed circuit board is electrically connected to the second encapsulation layer through solder balls, the second encapsulation layer and the second electrical chip are electrically connected through bumps, and the second electrical chip and the photoelectric detection array are electrically connected through micro-bumps.

10. The optical interconnection structure according to claim 5, characterized in that, Further included are: A memory and a processor; A third connection layer, which is used to connect the memory and the first encapsulation layer, and connect the processor and the first encapsulation layer; A switching chip, electrically connected to the second encapsulation layer.

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