Backup power circuit charging and discharging circuit and storage server

Abstract

The present disclosure provides a charging and discharging circuit for a backup power circuit and a storage server, wherein the charging and discharging circuit includes a main control circuit and a power conversion circuit, the main control circuit including four PWM signal output pins; the power conversion circuit includes four MOS transistors and a first inductor, the four MOS transistors including a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor is connected to the drain of the third MOS transistor via a first inductor and a current sampling resistor; the gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins. This solution simplifies the circuit and ensures the safety of the circuit, reduces the circuit cost, and reduces the PCB layout area; in addition, the electronic components that make up the circuit are all universal devices, eliminating material supply risks.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a charging and discharging circuit of a backup power circuit and a storage server. Background Art

[0002] Currently, the storage server's backup power circuitry consists of two unidirectional circuits: forward and reverse. The forward circuit is a buck-boost circuit built using peripheral circuits such as an MCU and MOS transistors. The PSU (Power Supply Unit) charges the battery backup unit (BBU). The reverse circuit is a buck circuit built using a dual-channel step-down chip, which discharges the BBU in reverse to power the system. This implementation not only requires numerous components, reducing circuit reliability and increasing costs, but also the buck chip used for reverse discharge is imported and not a universal component, posing a significant risk of stock shortages. Summary of the Invention

[0003] The present disclosure provides a charging and discharging circuit for a backup power circuit and a storage server, which can simplify the circuit, reduce costs, and eliminate the risk of out-of-stock.

[0004] In order to solve the above technical problems, the present disclosure provides a charging and discharging circuit of a backup power circuit, comprising:

[0005] A main control circuit, comprising four PWM signal output pins;

[0006] A power conversion circuit includes four MOS transistors and a first inductor. The four MOS transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor is connected to the drain of the third MOS transistor via the first inductor and a current sampling resistor. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and is grounded. The gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins.

[0007] An embodiment of the present disclosure further provides a storage server, which includes the circuit described above to charge and discharge the backup power circuit of the storage server.

[0008] The present disclosure provides a charging and discharging circuit for a backup power circuit, comprising: a main control circuit and a power conversion circuit, the main control circuit including four PWM signal output pins; the power conversion circuit including four MOS transistors and a first inductor, the four MOS transistors including a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the drain of the first MOS transistor being connected to the source of the second MOS transistor, the drain of the third MOS transistor being connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor being connected to the drain of the third MOS transistor via a first inductor and a current sampling resistor; the drain of the second MOS transistor being connected to the drain of the fourth MOS transistor and both being grounded; and the gates of the four MOS transistors being respectively connected to the output signals of the four PWM signal output pins. A power conversion circuit built using four MOS transistors implements a four-switch bidirectional buck-boost circuit. A master control circuit controls the operating modes of the MOS transistors in the power conversion circuit to achieve bidirectional energy flow, thereby realizing the BBU charging and discharging circuit. The analog plus digital drive protection strategy simplifies the circuit while ensuring circuit safety, reducing circuit costs and PCB layout area. Furthermore, the electronic components that make up the circuit are all universal devices, eliminating material supply risks. This circuit is suitable for any product requiring battery energy storage and backup power.

[0009] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0011] Figure 1 A structural block diagram of a charging and discharging circuit of a backup power circuit provided in an embodiment of the present disclosure;

[0012] Figure 2 A circuit schematic diagram of a main control circuit provided by an embodiment of the present disclosure;

[0013] Figure 3 A circuit schematic diagram of a power conversion circuit provided by an embodiment of the present disclosure;

[0014] Figure 4 A schematic diagram of a charge-discharge switching process provided by an embodiment of the present disclosure;

[0015] Figure 5 A circuit schematic diagram of a current sampling and protection circuit provided in an embodiment of the present disclosure;

[0016] Figure 6A circuit schematic diagram of a reference voltage circuit provided by an embodiment of the present disclosure;

[0017] Figure 7 A circuit schematic diagram of a driving circuit provided in an embodiment of the present disclosure;

[0018] Figure 8 A circuit schematic diagram of a voltage sampling circuit provided by an embodiment of the present disclosure;

[0019] Figure 9 A circuit schematic diagram of a working power supply circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0021] Explanation of terms:

[0022] MCU, Micro Control Unit, single-chip microcomputer;

[0023] MOS, Metal Oxide Semiconductor, Metal Oxide Semiconductor;

[0024] PSU, Power Supply Unit, power supply unit;

[0025] BBU, Battery Backup Unit, battery backup unit;

[0026] PWM, Pulse-width modulation, pulse width modulation;

[0027] BUCK-BOOST, step-up and step-down;

[0028] LED, Light-Emitting Diode, light-emitting diode;

[0029] PCB (Printed Circuit Board), printed circuit board, also known as printed circuit board.

[0030] The following describes a charging and discharging circuit of a backup power circuit and a storage server according to embodiments of the present disclosure with reference to the accompanying drawings.

[0031] A first aspect of the embodiments of the present application provides an embodiment of a charging and discharging circuit of a backup power circuit.

[0032] like Figure 1 As shown, the charging and discharging circuit 100 of the backup power circuit includes a main control circuit 101 and a power conversion circuit 102. The main control circuit 101 controls the power conversion circuit 102 to charge and discharge the backup power circuit 103:

[0033] The main control circuit 101 includes four PWM signal output pins;

[0034] The power conversion circuit 102 includes four MOS transistors and a first inductor. The four MOS transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor is connected to the drain of the third MOS transistor via the first inductor and a current sampling resistor. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and both are grounded. The gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins.

[0035] As an example, Figure 2 As shown, the main control circuit 101 includes a main control chip MCU of the model STM32F446RCT6TR, and the 42#, 43#, 26# and 27# pins of the MCU output four PWM signals for controlling the working mode of the four MOS tubes in the power conversion circuit 102, that is, the four PWM signal output pins output two complementary PWM signals to control the four MOS tubes in the power conversion circuit, realizing the bidirectional flow of energy and completing the functions of charging and discharging the BBU; the main control circuit 101 also includes an 8MHz crystal oscillator X1, a working power status indicator LED1, a main control chip working status indicator LED2, a working alarm indicator LED3, a reset button SW1, a J1-UART interface, a J2-IIC interface, a J4-burning interface, etc. The main control chip U7 is The control core of the entire charge and discharge circuit is responsible for the normal operation of the entire circuit; the 52# pin of the main control chip U7 is the fault input pin, which receives the POWER_FAULT signal. When the pin detects a circuit fault signal, it immediately stops the power output; the 57# pin is the control pin of the main control chip working status indicator LED2. When the system is working in the forward state, the pin controls the main control chip working status indicator LED2 to be always on. When the system is working in the reverse state, the pin controls the main control chip working status indicator LED2 to flash at a low frequency; the 33# pin is the control pin of the working alarm indicator LED3. When the circuit is working normally, the pin controls the working alarm indicator LED3 to flash at a low frequency. When the system circuit fails, the pin controls the working alarm indicator LED3 to flash at a high frequency. Figure 3 As shown, the four MOS transistors are a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, and a fourth MOS transistor Q4. The drain of the first MOS transistor Q1 is connected to the drain of the third MOS transistor Q3 via a first inductor L1 and a resistor R82. The gates of the first MOS transistor Q1 to the fourth MOS transistor Q4 are connected to the PWM signals output by the four PWM signal output pins.

[0036] Thus, the PWM signals outputted by the four PWM signal output pins of the main control circuit 101 respectively control the working states of the four MOS tubes of the power conversion circuit 102 to control the direction of energy flow and complete the functions of charging and discharging the BBU.

[0037] Through the technical solution of the embodiment of the present application, a four-switch bidirectional buck-boost circuit is implemented using a power conversion circuit 102 constructed using four MOS transistors. The main control circuit 101 controls the operating mode of the MOS transistors in the power conversion circuit 102 to achieve bidirectional energy flow, thereby realizing the charging and discharging circuit of the BBU. The analog plus digital drive protection strategy can simplify the circuit while ensuring circuit safety, reduce circuit costs, and reduce PCB layout area. In addition, the electronic components that make up the circuit are all universal devices, eliminating material supply risks. The circuit of this solution is suitable for any product that requires battery energy storage and backup power.

[0038] In one embodiment, a capacitor and a resistor are connected in series between the source and drain of each of the four MOS transistors, and a clamping diode is connected in parallel to the gate of each of the four MOS transistors. Figure 3 As shown in FIG, the capacitor and resistor connected in parallel at both ends of the drain and source of each MOS tube are used to absorb the peak voltage when the MOS tube is switched, such as capacitor C3 and resistor R13; the clamping diode connected in parallel to the gate of each MOS tube is used to prevent the driving voltage from being too high and breaking down the MOS tube, such as clamping diode D5.

[0039] Through the technical solution of the embodiment of the present application, a series capacitor and resistor are connected in parallel between the source and drain of the MOS tube to absorb the peak voltage when the MOS tube is switched; and a clamping diode is connected in parallel to the gate of the MOS tube to prevent the driving voltage from being too high and breaking down the MOS tube, thereby further improving the safety of the circuit.

[0040] In one embodiment, the main control circuit 101 is configured to: in response to the PSU working normally, control the power conversion circuit 102 to work in the charging mode, and the main control circuit 101 to work in the current discontinuous control mode; in response to the PSU working abnormality, control the power conversion circuit 102 to enter the discharge mode at the beginning of the next switching cycle, and the discharge mode is the BUCK-BOOST mode. For example, Figure 4As shown, whether a PSU fault occurs is detected. If no PSU fault occurs, the charge and discharge circuit operates in the BBU charging mode. In the charging mode, the circuit operates in the current discontinuous control mode to ensure that the current of the first inductor drops to 0A within one cycle, preparing for current reversal. In response to a PSU fault, the circuit enters the BBU discharge mode in the next switching cycle, and the discharge mode is the BUCK-BOOST mode.

[0041] Through the technical solutions of the embodiments of this application, the BBU utilizes a discontinuous current control mode during charging to ensure that the inductive current of the power conversion circuit can quickly reverse, thereby ensuring the timely discharge of the BBU and enabling seamless switching of energy flow direction. This means there is no time delay when the energy flow direction changes, keeping the BBU in a constant hot standby state. This also reduces current surges and improves the reliability of backup power switching. The BBU also operates in buck-boost mode during discharge, enabling both step-down and step-up voltages. This expands the operating voltage range of the BBU during discharge and indirectly improves its backup power capability.

[0042] In one embodiment, the charge and discharge circuit further includes a current sampling and protection circuit, which includes multiple groups of operational amplifier circuits. The operational amplifier circuit includes a differential amplifier circuit and a comparison circuit. The output end of the differential amplifier circuit is connected to the first input end of the comparison circuit, the second input end of the comparison circuit is connected to the reference voltage end, and the output end of the comparison circuit is connected to the fault input pin of the main control circuit 101; the input ends of the multiple differential amplifier circuits are respectively connected to the multiple current collection ends of the power conversion circuit 102; and the output ends of the multiple differential amplifier circuits are respectively connected to the multiple AD sampling pins of the main control circuit 101. As an example, Figure 5As shown, the current sampling and protection circuit includes three groups of operational amplifier circuits, each group of operational amplifier circuits includes a differential amplifier circuit composed of an operational amplifier chip of model LM358A-SR and a comparison circuit composed of an operational amplifier chip of model LM358A-SR. The output pins of the three operational amplifier chips U14.1, U15.1 and U20.1 are all connected to an input pin of the corresponding comparison circuit and the AD sampling pin of the main control circuit 101 at the same time; the multiple current collection terminals of the power conversion circuit 102 include the PSU end current collection terminal, the BBU end current collection terminal and the first inductor current collection terminal, and one input terminal of the three operational amplifier chips U14.1, U15.1 and U20.1 is respectively connected to the PSU end current collection terminal, the BBU end current collection terminal and the first inductor current collection terminal; to collect the current at the PSU end The circuit of is used as an example to explain in detail. PWR_D and PSU_P12V are differential signals and are sent to the AD sampling pin of the main control chip of the main control circuit 101 through the differential amplifier circuit composed of the operational amplifier chip U14.1 and peripheral resistors and capacitors. The PSU current value can be obtained after conversion by the internal algorithm of the main control chip. The amplified signal also enters the 6# pin of U14.2 and is compared with the reference voltage of the 5# pin of U14.2. If it is greater than the voltage value of the 5# pin, the 7# pin of U14.2 outputs a low level. D17 is a clamping diode to prevent the signal voltage from being too large to break down the main control chip. The other two paths are similar and will not be described in detail. Figure 3 As shown in the figure, when the current flows through the current sampling resistors R17, R18 and R82, the voltage drop generated is collected by the current sampling and protection circuit and sent to the AD sampling pins (pins 8#, 11# and 20#) of the main control chip to obtain the current value at the corresponding position for circuit control.

[0043] Through the technical solution of the embodiment of the present application, the three differential amplifier circuits of the three groups of operational amplifier circuits are respectively used to collect the current values ​​of the PSU end, BBU end and the first inductor in the power conversion circuit 102. These current values ​​are not only used in the control operation, but also used for overcurrent protection through the comparison circuit to improve the reliability of the circuit.

[0044] In one embodiment, the charge and discharge circuit further includes a reference voltage circuit, which includes a voltage regulator and a second operational amplifier. The output of the voltage regulator is connected to an input pin of the second operational amplifier, and the output pin of the second operational amplifier is connected to the reference voltage terminal of the current sampling and protection circuit. As an example, Figure 6As shown, the voltage regulator includes a power chip of model TL431AIDBZR, and the second operational amplifier is composed of an operational amplifier chip U18 of model OPA2188AID and its peripheral circuits. The output pin DRV_UVP of the operational amplifier chip U18 outputs a stable 1.5V reference voltage, which is used as a reference voltage for other circuits. For example, it is used as a reference voltage for the differential amplifier circuit of the current sampling and protection circuit. The current sampling and protection circuit uses 1.5V as the reference voltage. Without using a negative power supply, the bidirectional current sampling function is realized, which simplifies the circuit.

[0045] Through the technical solution of the embodiment of the present application, a stable reference voltage is provided for the chip in the circuit, thereby improving the reliability of the circuit.

[0046] In one embodiment, the charge and discharge circuit further includes a drive circuit 103, which includes a first drive unit, a second drive unit, and an AND gate logic protection unit, wherein: two input pins of the first drive unit and two input pins of the second drive unit are respectively connected to the output signals of four PWM signal output pins through resistors, and the two output pins of the first drive unit are respectively connected to the gates of the first MOS transistor and the second MOS transistor; the two output pins of the second drive unit are respectively connected to the gates of the third MOS transistor and the fourth MOS transistor; the AND gate logic protection unit includes a four-way AND gate logic chip, wherein the first input ends of the four AND gates of the four-way AND gate logic chip are respectively connected to the PWM signals output by the four PWM signal output pins of the main control circuit 101, and the second input ends of the four AND gates are all connected to the fault input pin of the main control circuit 101; the output ends of the multiple comparison circuits of the current sampling and protection circuit and the output end of the reference voltage circuit are all connected to the fault input pin of the main control circuit 101 through resistors and diodes connected in series, and the fault input pin is connected to an RC charging circuit composed of a resistor and a capacitor; the four output ends of the four-way AND gate logic chip are respectively connected to the input pins of the first drive unit and the second drive unit.

[0047] As an example, Figure 7As shown, the first and second drive units have the same circuit structure, both including a dual-channel driver chip (U9 / U10) model SQ55664SXD. This dual-channel driver chip is used to amplify the PWM signal output by the main control circuit 101 to drive the four MOS transistors in the power conversion circuit 102. The AND gate logic protection unit includes a driver protection circuit composed of a four-channel AND gate logic chip U13 model 74LVC08APW. When the charge-discharge circuit is operating normally, the four-channel AND gate logic chip U13 normally outputs the PWM signal from the main control circuit 101. When the charge-discharge circuit fails, the four-channel AND gate logic chip U13 pulls all output signals low, causing the MOS transistors in the power conversion circuit 102 to stop operating. The main function of the four-way AND gate logic chip U13 is to promptly shut down the drive signal from the main control circuit 101 when overcurrent and drive undervoltage occur, thereby protecting the MOS tube from further damage. Its protection principle is: diodes D16 / D15 / D14 / D20 form an OR gate circuit. When the four current sampling signals PWR_OCP, BAT_OCP, L_OCP output by the current sampling and protection circuit and the DRV_UVP output by the reference voltage circuit are all high, the fault input pin POWER_FAULT is high and the PWM signal from the main control circuit 101 is output normally. When any one of the signals PWR_OCP, BAT_OCP, L_OCP and DRV_UVP becomes low, the fault input pin POWER_FAULT is low, and the PWM drive signal from the main control circuit 101 is locked to a low level. At the same time, the POWER_FAULT signal is sent to the main control circuit 101 to alarm. This protection method leverages the fast response speed of analog circuits to provide rapid protection. Sending an alarm signal to the main control circuit 101 allows the main control circuit 101 to receive the alarm information and programmatically halt power conversion. Furthermore, resistor R58 and capacitor C72 form an RC charging circuit. This RC charging circuit's primary function is to delay the transition of POWER_FAULT from low to high, thereby providing the main control circuit 101 with sufficient reaction time for software-level alarming and control.

[0048] Through the technical solution of the embodiment of the present application, an AND gate logic protection unit is added to the driving circuit, which can quickly respond to the fault signal and prevent the occurrence of major faults.

[0049] In one embodiment, the charge and discharge circuit further includes a voltage sampling circuit, which includes multiple first operational amplifiers, the input terminals of the multiple first operational amplifiers are connected to multiple voltage collection terminals of the power conversion circuit 102 through voltage divider resistors, and the output terminals of the multiple first operational amplifiers are respectively connected to multiple AD sampling pins of the main control circuit 101. As an example, Figure 8As shown, the voltage sampling circuit includes two first operational amplifiers, which are used to collect the PSU terminal voltage and the BBU terminal voltage respectively for control operations; the two first operational amplifiers include an operational amplifier chip of model LM358A-SR, a clamping diode and other resistors and capacitors. For example, the voltage signal obtained by voltage division by resistors R62 and R68 is used as the input of the operational amplifier chip U19.1. The 2# pin and the 1# pin of U19.1 are short-circuited to form a voltage follower circuit. The signal output by the operational amplifier chip U19.1 is sent to the main control circuit 101 for PSU voltage collection, and then the actual PSU voltage value can be obtained through calculation by the main control circuit 101. The same is true for BBU voltage sampling. Figure 2 As shown in the figure, pins 9# and 10# of the main control chip are used to collect the voltage at the PSU end and the voltage at the BBU end, respectively.

[0050] Through the technical solution of the embodiment of the present application, the PSU terminal voltage and the BBU terminal voltage are collected through the above-mentioned circuit and used in the control operation, thereby improving the safety of the circuit.

[0051] In one embodiment, the working power supply circuit of the charge and discharge circuit is as follows: Figure 9 As shown, the working power supply circuit includes a power supply voltage regulator chip U11 of model AMS117-3.3, the power supply voltage regulator chip U11 and peripheral circuits, which provide 12V and 3.3V working voltages for the entire circuit. 3.3V is mainly used to power other chips.

[0052] On the basis of any of the above embodiments, an embodiment of the present disclosure further provides a storage server, which includes the charging and discharging circuit of any of the above embodiments to charge and discharge the backup power circuit of the storage server.

[0053] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0054] The above is a detailed introduction to a target detection method provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the circuits and core ideas of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present disclosure, several improvements and modifications can be made to the present disclosure, and these improvements and modifications also fall within the scope of protection of the claims of the present disclosure.

Claims

1. A charging and discharging circuit for a backup power circuit, characterized in that: include: A main control circuit, comprising four PWM signal output pins; A power conversion circuit, the power conversion circuit comprising four MOS transistors and a first inductor, the four MOS transistors including a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, the drain of the first MOS transistor is connected to the drain of the third MOS transistor via the first inductor and a current sampling resistor; the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and both are grounded; the gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins; A drive circuit includes a first drive unit, a second drive unit, and an AND gate logic protection unit. Two input pins of the first drive unit and two input pins of the second drive unit are respectively connected to the output signals of the four PWM signal output pins through resistors. The two output pins of the first drive unit are respectively connected to the gates of the first and second MOS transistors; the two output pins of the second drive unit are respectively connected to the gates of the third and fourth MOS transistors; the AND gate logic protection unit includes a four-way AND gate logic chip. The first input ends of the four AND gates of the four-way AND gate logic chip are respectively connected to the PWM signals output by the four PWM signal output pins of the main control circuit, and the second input ends of the four AND gates are all connected to the fault input pin of the main control circuit; the output ends of the multiple comparison circuits of the current sampling and protection circuit and the output end of the reference voltage circuit are each connected to the fault input pin of the main control circuit through a resistor and a diode connected in series. The fault input pin is connected to an RC charging circuit composed of a resistor and a capacitor; the four output ends of the four-way AND gate logic chip are respectively connected to the input pins of the first drive unit and the second drive unit.

2. The circuit according to claim 1, wherein: The main control circuit is configured as follows: In response to the PSU operating normally, controlling the power conversion circuit to operate in a charging mode and the main control circuit to operate in a current discontinuous control mode; In response to the PSU operating abnormality, the power conversion circuit is controlled to enter a discharge mode at the beginning of the next switching cycle, and the discharge mode is a BUCK-BOOST mode.

3. The circuit according to claim 1 or 2, characterized in that The charge and discharge circuit also includes a current sampling and protection circuit, which includes multiple groups of operational amplifier circuits. The operational amplifier circuit includes a differential amplifier circuit and a comparison circuit. The output end of the differential amplifier circuit is connected to the first input end of the comparison circuit, the second input end of the comparison circuit is connected to the reference voltage end, and the output end of the comparison circuit is connected to the fault input pin of the main control circuit; the input ends of the multiple differential amplifier circuits are respectively connected to the multiple current collection ends of the power conversion circuit; and the output ends of the multiple differential amplifier circuits are respectively connected to the multiple AD sampling pins of the main control circuit.

4. The circuit according to claim 3, characterized in that The charge and discharge circuit also includes a reference voltage circuit, which includes a voltage regulator and a second operational amplifier. The output end of the voltage regulator is connected to an input pin of the second operational amplifier, and the output pin of the second operational amplifier is connected to the reference voltage end of the current sampling and protection circuit.

5. The circuit according to claim 3, characterized in that The multiple current collection terminals of the power conversion circuit include a PSU current collection terminal, a BBU current collection terminal and a first inductor current collection terminal.

6. The circuit according to claim 1, wherein: The charge and discharge circuit also includes a voltage sampling circuit, which includes multiple first operational amplifiers. The input ends of the multiple first operational amplifiers are connected to the multiple voltage collection ends of the power conversion circuit through voltage-dividing resistors, and the output ends of the multiple first operational amplifiers are respectively connected to the multiple AD sampling pins of the main control circuit.

7. The circuit according to claim 1, wherein: A capacitor and a resistor are connected in series in parallel between the source and drain of the four MOS tubes, and a clamping diode is connected in parallel to the gate of the four MOS tubes.

8. A storage server, characterized in that: The storage server comprises the circuit according to any one of claims 1 to 7, so as to charge and discharge the backup power circuit of the storage server.

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