Blanking signal generation circuit, switching converter and control circuit thereof

Abstract

The invention discloses a blanking signal generation circuit, a switching converter and a control circuit of the switching converter. A main power tube of the switching converter is connected between a voltage input end and a switching node, the blanking signal generation circuit is used for providing a blanking signal, the main power tube is kept on during an effective level period of the blanking signal, and the blanking signal generation circuit comprises a detection circuit used for comparing the potential of the voltage input end with the potential of the switching node and generating a blanking signal according to the comparison result. An adjusting signal is provided according to the comparison result; the logic circuit is used for providing a blanking signal according to the adjusting signal and a driving signal of the main power tube, and the logic circuit outputs an effective level of the blanking signal when the driving signal represents that the main power tube starts to be conducted and outputs an ineffective level of the blanking signal at least after the adjusting signal represents that the main power tube is completely conducted. Therefore, the dynamic adjustment of the blanking duration can be realized, and the dynamic performance of the switching converter can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a blanking signal generation circuit, a switching converter and its control circuit. Background Art

[0002] With the continuous development of electronic devices, the performance requirements for switching power supplies are increasing day by day. As a common switching power supply topology, the buck (BUCK) converter is widely used in the technical fields of consumer electronics and automotive electronics to convert a higher input voltage into a lower stable output voltage to meet the power supply requirements of the load.

[0003] In a BUCK converter, the main power transistor and the freewheeling power transistor are connected in series between the input terminal and the ground, and are thus respectively referred to as the upper transistor and the lower transistor. The drive signals for controlling the on and off of the upper and lower transistors are generated by a control circuit. The dual-loop control circuit is a common control circuit architecture. In the dual-loop control circuit, a sampling signal of the inductor current is obtained via the current loop, and an error signal of the voltage feedback signal is obtained via the voltage loop. The duty ratio of the drive signal is adjusted according to the comparison result between the sampling signal and the error signal.

[0004] During the actual operation of the BUCK converter, the ringing on the parasitic inductor of the upper transistor and the reverse recovery charge of the lower transistor will introduce errors to the sampling signal of the inductor current. In the prior art, in order to avoid misoperation of the BUCK converter caused by such errors, a blanking signal (BLANK signal) is usually used to temporarily shield the sampling signal.

[0005] In order to make the sampling signal adapt to the conduction speeds of different power transistors and truly reflect the inductor current, the existing BLANK signals are often designed conservatively with a relatively long duration. However, an overly long BLANK signal time will reduce the timeliness of feedback control. During the blanking period, the control circuit cannot accurately obtain the real-time state information of the circuit, resulting in a slower response speed to load changes or input voltage fluctuations, affecting the dynamic performance of the switching converter and making it inapplicable to high-frequency and small-duty-cycle application scenarios. Summary of the Invention

[0006] In view of the above problems, the purpose of the present application is to provide a blanking signal generation circuit, a switching converter and its control circuit, which can dynamically adjust the duration of the blanking signal.

[0007] According to one aspect of the present application, a blanking signal generation circuit for a switching converter is provided. The main power transistor of the switching converter is connected between a voltage input terminal and a switching node. The blanking signal generation circuit is used to provide a blanking signal, and the main power transistor remains conducting during the active level of the blanking signal. Wherein, the blanking signal generation circuit includes: a detection circuit for comparing the potentials of the voltage input terminal and the switching node and providing an adjustment signal according to the comparison result; and a logic circuit for providing the blanking signal according to the adjustment signal and the drive signal of the main power transistor. Wherein, the logic circuit outputs the active level of the blanking signal when the drive signal indicates that the main power transistor starts to conduct, and outputs the inactive level of the blanking signal after the adjustment signal indicates that the main power transistor is fully conducting.

[0008] Optionally, the detection circuit is used to provide the active level of the adjustment signal when the potential of the switching node rises to the potential of the voltage input terminal, and the active level of the adjustment signal indicates that the main power transistor is fully conducting.

[0009] Optionally, the detection circuit includes: a first transistor whose control terminal receives the drive signal and whose first terminal is connected to the voltage input terminal; a first inverter whose positive power supply terminal receives the bootstrap voltage of the switching converter, whose negative power supply terminal is connected to the switching node, whose input terminal is connected to the second terminal of the first transistor, and whose output terminal provides the adjustment signal; and a second transistor whose control terminal receives the blanking signal, whose first terminal receives the bootstrap voltage, and whose second terminal is connected to the second terminal of the first transistor.

[0010] Optionally, the detection circuit further includes: an anti-interference module connected between the second terminal of the first transistor and the input terminal of the first inverter. The anti-interference module is used to charge the first terminal of the first transistor when the main power transistor is conducting, so that the voltage of the first terminal of the first transistor follows the bootstrap voltage.

[0011] Optionally, the anti-interference module includes: a third transistor whose first terminal is connected to the input terminal of the first inverter, whose second terminal is connected to the second terminal of the first transistor, and whose control terminal receives the bootstrap voltage; a fourth transistor whose first terminal receives the bootstrap voltage, whose second terminal is connected to the input terminal of the first inverter, and whose control terminal receives the blanking signal; a fifth transistor and a first resistor connected in series, the first terminal of the fifth transistor receives the bootstrap voltage, the control terminal receives the inverted signal of the blanking signal, and the first resistor is connected to the second terminal of the first transistor; and a first capacitor whose first terminal receives the bootstrap voltage and whose second terminal is connected to the second terminal of the first transistor.

[0012] Optionally, the logic circuit includes: a NAND gate having a first terminal receiving the drive signal and a second terminal receiving the adjustment signal; and an AND gate having a first terminal connected to the output terminal of the NAND gate, a second terminal receiving the drive signal, and an output terminal providing the blanking signal.

[0013] Optionally, when the adjustment signal indicates that the main power transistor is fully turned on and after a preset time period has elapsed, the logic circuit outputs an invalid level of the blanking signal.

[0014] Optionally, the logic circuit further includes: a delay module connected between the NAND gate and the AND gate to provide signal delay for the preset time period.

[0015] Optionally, the delay module includes: a sixth transistor, a second resistor, and a seventh transistor connected in series, a first terminal of the sixth transistor receiving the bootstrap voltage, a second terminal of the seventh transistor connected to the switching node, control terminals of the sixth transistor and the seventh transistor being connected and connected to the output terminal of the NAND gate; a second capacitor connected between the first terminal and the second terminal of the seventh transistor; and a second inverter having an input terminal connected to the first terminal of the seventh transistor and an output terminal connected to the first terminal of the AND gate.

[0016] According to a second aspect of the present application, there is provided a control circuit for a switching converter. The main power transistor of the switching converter is connected between a voltage input terminal and a switching node, and the inductor of the switching converter is connected between the switching node and a voltage output terminal. The control circuit is configured to provide a drive signal for the main power transistor. The control circuit includes: an error amplification unit configured to output an error signal according to a comparison result between a feedback signal of the output voltage of the switching converter and a reference signal; a comparator configured to compare a sampled signal of the inductor current with the error signal and provide a pulse width modulation signal according to the comparison result; a logic unit configured to provide a control signal according to a clock signal and the pulse width modulation signal, the clock signal being used to determine a turn-on time of the main power transistor, and the pulse width modulation signal being used to determine a turn-off time of the main power transistor; a drive unit configured to convert the control signal into a drive signal for the main power transistor; and a switching transistor having a first terminal connected to an intermediate node between the comparator and the logic unit, a second terminal grounded, and a control terminal connected to the blanking signal generation circuit as described in any one of the above to block the pulse width modulation signal during an active level of the blanking signal.

[0017] According to a third aspect of the present application, there is provided a switching converter, which includes: a main power transistor and a freewheeling power transistor connected between a voltage input terminal and the ground, a switching node being formed therebetween; an inductor connected between the switching node and a voltage output terminal; and the control circuit as described above to provide a drive signal for the main power transistor.

[0018] According to the blanking signal generation circuit, switching converter and its control circuit provided by the present application, the detection circuit compares the switch node voltage with the input voltage of the switching converter, so as to judge whether the upper transistor is fully turned on according to the relative magnitude of the two, thereby realizing the dynamic adjustment of the blanking signal duration. The minimum blanking duration is obtained while ensuring that the main power transistor is fully turned on, which is beneficial to improving the dynamic performance of the switching converter, and can also achieve a higher conversion ratio and conversion frequency, meeting the application requirements of high frequency and small duty cycle under low power consumption applications.

[0019] Furthermore, by setting a delay module in the logic circuit, the blanking signal is inverted to an invalid level after the main power transistor is fully turned on and experiences a preset duration, which is more beneficial to shielding the influence of the parasitic capacitance of the main power transistor.

[0020] Furthermore, by setting an anti-interference module in the detection circuit, false detection caused by the rapid rise of the bootstrap voltage and the switch node voltage during the conduction process of the main power transistor is avoided, which is beneficial to improving the stability of the switching converter. Description of the Drawings

[0021] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0022] Figure 1 A schematic structural diagram of the switching converter according to an embodiment of the present application is shown;

[0023] Figure 2 A working waveform diagram of the switching converter when the blanking signal has a fixed duration is shown;

[0024] Figure 3 A schematic structural diagram of the signal generation circuit according to an embodiment of the present application is shown;

[0025] Figure 4 A schematic structural diagram of the detection circuit is shown;

[0026] Figure 5 A schematic structural diagram of the logic circuit is shown;

[0027] Figure 6 A working waveform diagram of the switching converter when the blanking signal has a dynamic duration is shown. Detailed Embodiments

[0028] The various embodiments of the present invention will be described in more detail below with reference to the drawings. In each drawing, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means there are no intermediate elements between the two.

[0030] In the following description, a "transistor" refers to an active device that includes at least one control terminal and two current terminals. A "switching transistor" refers to a transistor operating in a switching state, and a "power transistor" refers to a transistor used as a power switch. A transistor includes, for example, any one selected from bipolar transistors or field effect transistors. The "control terminal" of a transistor is the base of a bipolar transistor or the gate of a field effect transistor, and the conduction state of the transistor is controlled by applying a voltage or current to the control terminal. In the conduction state of the transistor, current flows from the first terminal at a high potential to the second terminal at a low potential.

[0031] Meanwhile, in this patent specification and claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use the difference in names as a way to distinguish components, but rather use the difference in the functions of components as the criterion for distinction.

[0032] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0033] Figure 1 The schematic structural diagram of the switching converter showing an embodiment of the present application is referenced. Figure 1 , taking the buck converter as an example, the switching converter 1 includes a power circuit 10 and a control circuit 20.

[0034] The input terminal of the power circuit 10, i.e., the voltage input terminal of the BUCK converter, receives the input voltage Vin; the output terminal, i.e., the voltage output terminal of the BUCK converter, provides the output voltage Vout. Refer to Figure 1 , the power circuit 10 includes a main power transistor MH, a freewheeling power transistor ML, an inductor L1, a capacitor Cout, and a load Rload.

[0035] The main power transistor MH and the freewheeling power transistor ML are sequentially connected between the voltage input terminal and the ground. Thus, usually, the main power transistor MH is also referred to as the upper transistor MH, and the freewheeling power transistor ML is also referred to as the lower transistor ML. The upper transistor MH and the lower transistor ML are, for example, N-type MOSFETs, and the node between them is called the switching node SW. The inductor L1 is connected between the switching node SW and the output terminal, the capacitor Cout is connected between the output terminal and the ground, and the load Rload is connected in parallel with the capacitor Cout. In Figure 1 the parasitic inductance LM of the upper transistor MH is also shown, and this parasitic inductance LM is located between the input terminal and the power transistor MH.

[0036] Under the control of the corresponding drive signals, the upper transistor MH and the lower transistor ML alternately conduct and disconnect. During the conduction period of the upper transistor MH, the lower transistor ML is disconnected, and the input voltage Vin charges the inductor L1 and supplies power to the output terminal. During the conduction period of the lower transistor ML, the upper transistor MH is disconnected, and the inductor L1 supplies power to the output terminal through the lower transistor ML. In consecutive switching cycles, a continuous output is generated at the output terminal of the power circuit 10, and is filtered by the capacitor Cout to obtain a substantially constant output voltage Vout.

[0037] The control circuit 20 is used to provide the drive signal HSON for the upper transistor MH and the drive signal LSON for the lower transistor ML. Refer to Figure 1 , the control circuit 20 includes a sampling unit 21, an error amplification unit 22, a comparator CMP, a logic unit 23, an upper transistor drive unit 24, a lower transistor drive unit (not shown in the figure), and a protection unit 25.

[0038] The sampling unit 21 samples the current of the inductor L1 to obtain a sampling signal CS. This sampling signal CS is usually a voltage signal. In some embodiments, the sampling unit 21, for example, obtains the sampling voltage CS by detecting the drain-source voltage drop of the upper transistor MH, and this application does not impose too many restrictions on this.

[0039] The error amplification unit 22 is used to compare the feedback signal of the output voltage Vout with the corresponding reference signal REF, amplify and output the error signal COMP between the two. Among them, the error amplification unit 22 can, for example, select an amplifier with differential input and single-ended output, or a transconductance amplifier. In Figure 1In the example, the output voltage Vout is used as a feedback signal and compared with its corresponding reference signal REF. However, it should be understood that in some other embodiments, the output voltage Vout can also be sampled to obtain a feedback signal.

[0040] The non-inverting input terminal of the comparator CMP receives the sampled voltage CS, and the inverting input terminal receives the error signal COMP. The comparator CMP compares the sampled voltage CS and the error signal COMP to generate a pulse width modulation signal PWM, which can be used to adjust the duty cycle of the upper transistor drive signal HSON.

[0041] The logic unit 23 generates an upper transistor control signal CTS according to the pulse width modulation signal PWM and the clock signal CLK. Among them, the clock signal CLK is used to determine the conduction moment of the upper transistor, and the pulse width modulation signal PWM is used to determine the turn-off moment of the upper transistor. Exemplarily, the upper transistor control signal CTS can be generated by the cross-connected NOR gates NOR1 and NOR2.

[0042] The upper transistor drive unit 24 generates a drive signal HSON for the upper transistor MH according to the upper transistor control signal CTS. The upper transistor drive unit 24 includes, for example, an inverter composed of switching transistors MA1 and MA2. Among them, the switching transistor MA1 can be a P-type MOSFET, the switching transistor MA2 can be an N-type MOSFET, and the control terminals of the switching transistors MA1 and MA2 are connected together as the input terminal of the inverter and receive the upper transistor control signal CTS. The first terminal of the switching transistor MA1 receives the bootstrap voltage BOOT, the second terminal of the switching transistor MA1 is connected to the first terminal of the switching transistor MA2 as the output terminal of the inverter and provides the upper transistor drive signal HSON, and the second terminal of the switching transistor MA2 is connected to the switching node SW of the power circuit 10. When the upper transistor control signal CTS turns on the switching transistor MA1 and turns off the switching transistor MA2, the bootstrap voltage BOOT charges the control terminal of the upper transistor MH, thereby controlling the upper transistor MH to conduct; when the upper transistor control signal CTS turns on the switching transistor MA2 and turns off the switching transistor MA1, the control terminal of the upper transistor MH is discharged, thereby controlling the upper transistor MH to turn off. In some embodiments, the size of the switching transistor MA1 can be adjusted to meet the requirements for the conduction speed of the upper transistor MH under different working conditions. It should be understood that although not shown in Figure 1 the switching converter 1 should also include a bootstrap circuit to provide the bootstrap voltage BOOT.

[0043] In some embodiments, the logic unit 23 also provides a lower transistor control signal, and the lower transistor drive unit provides a lower transistor drive signal LSON according to the lower transistor control signal, thereby controlling the conduction and turn-off of the lower transistor ML.

[0044] It should be noted that the above exemplary description should not limit the specific structures of the sampling unit 21, error amplification unit 22, logic unit 23, upper transistor driving unit 24, and lower transistor driving unit. These units can be implemented according to any existing technology.

[0045] During the operation of the BUCK converter 1, the control circuit 20 dynamically adjusts the duty cycles of the upper transistor MH and the lower transistor ML in the switching period according to the feedback signal of the output voltage Vout, so as to obtain the desired output voltage Vout or output current.

[0046] To avoid the ringing on the parasitic inductor LM and the reverse recovery charge of the lower transistor ML from affecting the sampling signal CS, the BUCK converter 1 of the present application further includes a protection circuit 25.

[0047] Specifically, the protection circuit 25 includes a switching transistor MN. The switching transistor MN is, for example, an N-type MOSFET. Its first end is connected to the output end of the comparator CMP, the second end is grounded, and the control end receives the blanking signal BLANK. The blanking signal BLANK controls the on / off of the switching transistor MN. When the switching transistor MN is turned on, the pulse width modulation signal PWM is shielded. Therefore, when the on / off states of the upper transistor MH and the lower transistor ML change, the influence of the fluctuation of the sampling signal CS on the operating state of the BUCK converter can be shielded.

[0048] In some embodiments, the effective duration of the blanking signal BLANK is fixed, that is, the shielding duration of the sampling signal CS is fixed. Figure 2 Shows the operating waveform diagram of the switching converter when the blanking signal has a fixed duration. Wherein, T is the fixed duration of the blanking signal BLANK, and t1 and t2 are the durations required for the upper transistor MH to be fully turned on at different conduction speeds.

[0049] Refer to Figure 2 , due to the different conduction speeds of the upper transistor MH, the following two situations may occur:

[0050] In the first situation, the duration t1 required for the upper transistor MH to be fully turned on is less than T. The potential of the switching node SW quickly rises to near the input voltage Vin. After the end of the BLANK time, the sampling signal CS can correctly reflect the current situation of the upper transistor MH, and the pulse width modulation signal PWM can correctly adjust the duty cycle of the upper transistor driving signal HSON and control the upper transistor MH to turn off correctly.

[0051] In the second situation, the duration t2 required for the upper transistor to be fully turned on is greater than T. After the end of the BLANK time, the potential of the switching node SW is still in the rising stage. At this time, the sampling signal CS cannot correctly reflect the current situation of the upper transistor MH, the duty cycle adjustment of the upper transistor driving signal HSON is abnormal, and the upper transistor MH is turned off without being fully turned on.

[0052] To avoid the occurrence of the second case, the BLANK of the blanking signal is set conservatively with a relatively long duration.

[0053] In a preferred embodiment, referring to Figure 1 , the protection unit 25 further includes a signal generation circuit 100 for providing a dynamic blanking signal BLANK with adjustable blanking duration. Among them, the first power supply terminal of the signal generation circuit 100 is connected to the voltage input terminal to receive the input voltage Vin (hereinafter referred to as the Vin terminal), the second power supply terminal receives the bootstrap voltage BOOT (hereinafter referred to as the BOOT terminal), the third power supply terminal is connected to the switch node SW of the power circuit 10 (hereinafter referred to as the SW terminal), and the output terminal provides the blanking signal BLANK.

[0054] Figure 3 The schematic structural diagram of the signal generation circuit according to the embodiment of the present application is shown. Referring to Figure 3 , the signal generation circuit 100 includes a detection circuit 110 and a logic circuit 120. The detection circuit 110 is used to compare the potentials of the Vin terminal and the SW terminal, and provide an adjustment signal S1 according to the comparison result. Among them, when the potential of the SW terminal is raised to the potential of the Vin terminal, the detection circuit 110 provides the effective level of the adjustment signal, and this effective level indicates that the upper transistor is fully turned on. The logic circuit 120 is used to provide the blanking signal BLANK according to the adjustment signal S1 and the upper transistor drive signal HSON. Among them, the logic circuit outputs the effective level of the BLANK signal when the upper transistor drive signal HSON indicates that the upper transistor MH starts to conduct, and outputs the invalid level of the blanking signal BLANK at least after the adjustment signal S1 indicates that the upper transistor is fully turned on. During the effective level of the blanking signal BLANK, the upper transistor MH correctly maintains the on state, so the reliability of the BUCK converter can be improved.

[0055] Figure 4 The schematic structural diagram of the detection circuit is shown, Figure 5 The schematic structural diagram of the logic circuit is shown. The following will refer to Figure 4 and Figure 5 in the examples to make a detailed description of the signal generation circuit 100.

[0056] Referring to Figure 4 , the detection circuit 110 includes a first transistor M1, a second transistor M2, and a first inverter INV1.

[0057] The control terminal of the first transistor M1 receives the upper transistor drive signal HSON, and the first terminal is connected to the Vin terminal. The positive power supply terminal of the first inverter INV1 is connected to the BOOT terminal, the negative power supply terminal is connected to the SW terminal, the input terminal (hereinafter referred to as node B) is connected to the second terminal of the first transistor M1 (hereinafter referred to as node A), and the output terminal is connected to the logic circuit 120 to provide the regulation signal S1. The second transistor M2 is connected between the first power supply terminal and node A, and the control terminal receives the blanking signal BLANK.

[0058] Further, in a preferred embodiment, the detection circuit 110 further includes an anti-interference module 111. The anti-interference module 111 is connected between node A and node B, and is used to charge node A when the upper transistor MH is turned on, so that the voltage of node A can correctly follow the boost voltage increase.

[0059] The anti-interference module 111 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first resistor R1, and a first capacitor C1.

[0060] The first terminal of the third transistor M3 is connected to node B, the second terminal is connected to node A, and the control terminal is connected to the BOOT terminal. The fourth transistor M4 is connected between the BOOT terminal and node B, and the control terminal receives the blanking signal BLANK. The fifth transistor M5 and the first resistor R1 are sequentially connected between the BOOT terminal and node A, and the control terminal of the fifth transistor M5 receives the inverted signal BZ of the blanking signal BLANK. The first capacitor C1 is connected between the BOOT terminal and node A.

[0061] Regarding the detection unit 110b of the second embodiment, when the upper transistor drive signal HSON is at a low level, the first transistor M1 is turned off. At this time, the second transistor M2 and the fourth transistor M4 are turned on, the fifth transistor M5 is turned off, and the potentials of node A and node B are close to the potential of the boost voltage BOOT, and this potential is also considered to be a high level by the first inverter INV1, so the regulation signal S1 of a low level is output.

[0062] Reference Figure 5 The logic circuit 120 includes a NAND gate NAND and an AND gate AND.

[0063] The first input terminal of the NAND gate NAND receives the upper transistor drive signal HSON, and the second terminal is connected to the detection circuit 110 to receive the regulation signal S1. The first input terminal of the AND gate AND is connected to the output terminal of the NAND gate NAND, the second input terminal receives the upper transistor drive signal HSON, and the output terminal provides the blanking signal BLANK.

[0064] In a preferred embodiment, to ensure that the ringing effect of the parasitic inductance LM can be avoided, a delay module 121 is further included in the logic circuit 120, which is connected between the output end of the NAND gate and the first input end of the AND gate, and is used to provide a signal delay with a preset duration tA between the NAND gate and the AND gate.

[0065] Reference Figure 5 , the delay module 121 includes a sixth transistor M6, a seventh transistor M7, a second resistor R2, a second capacitor C2, and a second inverter INV2.

[0066] The sixth transistor M6, the second resistor R2, and the seventh transistor M7 are sequentially connected between the BOOT terminal and the SW terminal. The control terminals of the sixth transistor M6 and the seventh transistor M7 are connected together and connected to the output end of the NAND gate. The input end of the second inverter INV2 is connected to the middle node between the second resistor R2 and the seventh transistor M7, and the output end is connected to the first input end of the AND gate. The second capacitor C2 is connected between the middle node between the second resistor R2 and the seventh transistor M7 and the SW terminal.

[0067] In this delay module 121, the RC duration of the second resistor R2 and the second capacitor C2 provides the above-mentioned preset duration tA. Therefore, on the basis of ensuring that the upper transistor MH is fully turned on, the ringing effect of the parasitic inductance LM can be further ensured to be eliminated, and the reliability of the switching converter is improved.

[0068] Furthermore, in some embodiments, the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 can be adjusted with reference to the turn-on speed of the upper transistor MH to adjust the delay duration tA. For example, when the turn-on rate of the upper transistor is slow, since the influence of the parasitic inductance ML is very small, tA can be reduced; conversely, when the turn-on rate of the upper transistor is fast, tA can be increased, which is more conducive to the dynamic minimization adjustment of the blanking duration.

[0069] It should be understood that the above-mentioned delay module 121, and even the above-mentioned logic circuit 120, should not be limited to Figure 5 the examples shown. For example, at least the delay module 121 can also be implemented using a timer circuit.

[0070] In Figure 4 and Figure 5 's examples, for example, the first transistor M1, the third transistor M3, and the seventh transistor M7 are N-type MOSFETs, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are P-type MOSFETs.

[0071] The above upper transistor drive signal HSON and blanking signal BLANK are both invalid at low level and valid at high level as an example. That is to say, when the upper transistor drive signal HSON is at high level, the upper transistor MH conducts, and conversely, the upper transistor MH turns off; when the BLANK signal is at high level, the pulse width modulation signal PWM is shielded (that is, the influence of the sampling signal CS is shielded), and conversely, the duty cycle of the upper transistor drive signal HSON is adjusted according to the pulse width modulation signal PWM. Figure 6 The working waveform diagram of the switching converter when the blanking signal has a dynamic duration is shown. The following combines Figures 4 to 6 Briefly describe the working principle of the signal generation circuit 100.

[0072] First, the case without the anti-interference module 111 is described:

[0073] When the upper transistor drive signal HSON is at low level, the first transistor M1 turns off. At this time, the blanking signal BLANK output by the logic unit 120 is also at low level, the second transistor M2 conducts, and the potential of node A approaches the potential of the bootstrap voltage BOOT. Since the first inverter operates in the power supply domain provided by BOOT-SW, the potential of node A is considered to be high level by the first inverter INV1 at this time. Correspondingly, the first inverter INV outputs a low-level adjustment signal S1.

[0074] When the upper transistor drive signal HSON flips to high level, the upper transistor HM and the first transistor M1 conduct, and the blanking signal BLANK flips to high level, and the second transistor M2 turns off. When the upper transistor HM just starts to conduct, the potential of the SW terminal has not been pulled up yet. Therefore, the potential of node A is still considered to be high level by the first inverter INV1 at this time, and the low-level adjustment signal S1 is maintained.

[0075] Due to the different conduction speeds of the upper transistors, after a short time t1 or a long time t2, the potential of the SW terminal may be raised to be close to the input voltage Vin. At this time, due to the conduction of the transistor M1, the potential of node A is also close to the input voltage Vin. Therefore, the potential of node A is considered to be low level by the first inverter INV1, and correspondingly, the first inverter INV outputs a low-level adjustment signal S1.

[0076] After experiencing the delay duration tA provided by the delay module 121, the blanking signal BLANK is flipped to low level, and the blanking duration ends. Therefore, regardless of the size relationship between the duration t1 or t2 required for the upper transistor MH to fully conduct and the delay duration tA provided by the delay module 121, the blanking duration can cover the duration required for the upper transistor MH to fully conduct.

[0077] In the case including the anti-interference module 111:

[0078] When the upper transistor drive signal HSON is at a low level, the first transistor M1 is turned off. At this time, the blanking signal BLANK output by the logic unit 120 is also at a low level, the second transistor M2 is turned on, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, and the potentials of node A and node B approach the potential of the bootstrap voltage BOOT. The first inverter INV outputs a low-level adjustment signal S1.

[0079] When the upper transistor drive signal HSON flips to a high level, the upper transistor HM and the first transistor M1 are turned on, the blanking signal BLANK flips to a high level, the second transistor M2 and the fourth transistor M4 are turned off, and the fifth transistor M5 is turned on. The conducting fifth transistor M5 and the first capacitor C1 charge node A, causing the potential of node A to rise following the BOOT potential and stably maintaining near the BOOT potential. Therefore, it can avoid misidentifying the conduction state of the upper transistor when the potential of the SW terminal is rapidly raised when the upper transistor HM is turned on and the potential of node A cannot be rapidly raised, which is more conducive to improving the operating stability of the BUCK converter.

[0080] The anti-interference module 111 does not affect the operation of the logic circuit 120, which will not be elaborated here.

[0081] According to the blanking signal generation circuit, the switching converter and its control circuit provided by the present application, the detection circuit compares the switching node voltage with the input voltage of the switching converter to judge whether the upper transistor is fully turned on by the relative magnitudes of the two, so as to realize the dynamic adjustment of the blanking signal duration. Obtaining the minimum blanking duration while ensuring the full conduction of the main power transistor is conducive to improving the dynamic performance of the switching converter, and can also achieve a higher conversion ratio and conversion frequency, meeting the application requirements of high frequency and small duty cycle under low power consumption applications.

[0082] Furthermore, by setting a delay module in the logic circuit, the blanking signal flips to an invalid level after the main power transistor is fully turned on and experiences a preset duration, which is more conducive to shielding the influence of the parasitic capacitance of the main power transistor.

[0083] Furthermore, by setting an anti-interference module in the detection circuit, false detection caused by the rapid rise of the bootstrap voltage and the switching node voltage during the conduction process of the main power transistor is avoided, which is conducive to improving the stability of the switching converter.

[0084] As described above with respect to the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The protection scope of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. A blanking signal generation circuit for a switching converter, wherein a main power transistor of the switching converter is connected between a voltage input terminal and a switching node, the blanking signal generation circuit is configured to provide a blanking signal, and the main power transistor remains conducting during an active level of the blanking signal, wherein, The blanking signal generation circuit includes: a detection circuit configured to compare the potential of the voltage input terminal with that of the switch node and provide an adjustment signal according to the comparison result; and a logic circuit configured to provide the blanking signal according to the adjustment signal and the driving signal of the main power transistor, wherein, when the driving signal indicates that the main power transistor starts to conduct, the logic circuit outputs the valid level of the blanking signal, and when the adjustment signal indicates that the main power transistor is fully conducting, the logic circuit outputs the invalid level of the blanking signal.

2. The blanking signal generation circuit according to claim 1, wherein The detection circuit is configured to provide the valid level of the adjustment signal when the potential of the switch node rises to the potential of the voltage input terminal, and the valid level of the adjustment signal indicates that the main power transistor is fully conducting.

3. The blanking signal generation circuit according to claim 2, wherein, The detection circuit includes: a first transistor, the control terminal of which receives the driving signal, and the first terminal of which is connected to the voltage input terminal; a first inverter, the positive power supply terminal of which receives the bootstrap voltage of the switching converter, the negative power supply terminal of which is connected to the switch node, the input terminal of which is connected to the second terminal of the first transistor, and the output terminal of which provides the adjustment signal; and a second transistor, the control terminal of which receives the blanking signal, the first terminal of which receives the bootstrap voltage, and the second terminal of which is connected to the second terminal of the first transistor.

4. The blanking signal generation circuit according to claim 3, wherein, The detection circuit further includes: an anti-interference module connected between the second terminal of the first transistor and the input terminal of the first inverter, and the anti-interference module is configured to charge the first terminal of the first transistor when the main power transistor conducts, so that the voltage of the first terminal of the first transistor follows the bootstrap voltage.

5. The blanking signal generation circuit according to claim 4, wherein, The anti-interference module includes: a third transistor, the first terminal of which is connected to the input terminal of the first inverter, the second terminal of which is connected to the second terminal of the first transistor, and the control terminal of which receives the bootstrap voltage; a fourth transistor, the first terminal of which receives the bootstrap voltage, the second terminal of which is connected to the input terminal of the first inverter, and the control terminal of which receives the blanking signal; a fifth transistor and a first resistor connected in series, the first terminal of the fifth transistor receives the bootstrap voltage, the control terminal of which receives the inverted signal of the blanking signal, and the first resistor is connected to the second terminal of the first transistor; and a first capacitor, the first terminal of which receives the bootstrap voltage, and the second terminal of which is connected to the second terminal of the first transistor.

6. The blanking signal generation circuit according to claim 1, wherein, The logic circuit includes: a NAND gate, the first terminal of which receives the driving signal, and the second terminal of which receives the adjustment signal; and an AND gate, the first terminal of which is connected to the output terminal of the NAND gate, the second terminal of which receives the driving signal, and the output terminal of which provides the blanking signal.

7. The blanking signal generation circuit according to claim 6, wherein, The logic circuit outputs the invalid level of the blanking signal when the adjustment signal indicates that the main power transistor is fully conducting and after a preset time duration.

8. The blanking signal generation circuit according to claim 7, wherein, The logic circuit further includes: a delay module connected between the NAND gate and the AND gate to provide a signal delay of the preset time duration.

9. The blanking signal generation circuit according to claim 8, wherein, The delay module includes: A sixth transistor, a second resistor, and a seventh transistor connected in series, a first end of the sixth transistor receiving the bootstrap voltage, a second end of the seventh transistor connected to the switching node, and control ends of the sixth transistor and the seventh transistor being connected and connected to an output end of the NAND gate; A second capacitor connected between a first end and a second end of the seventh transistor; and A second inverter, an input end thereof being connected to the first end of the seventh transistor, and an output end thereof being connected to a first end of the AND gate.

10. A control circuit for a switching converter, wherein, A main power transistor of the switching converter is connected between a voltage input end and the switching node, an inductor of the switching converter is connected between the switching node and a voltage output end, and the control circuit is configured to provide a driving signal for the main power transistor, The control circuit includes: An error amplification unit configured to output an error signal according to a comparison result between a feedback signal of the output voltage of the switching converter and a reference signal; A comparator configured to compare a sampled signal of the inductor current with the error signal and provide a pulse width modulation signal according to the comparison result; A logic unit configured to provide a control signal according to a clock signal and the pulse width modulation signal, the clock signal being used to determine a conduction moment of the main power transistor, and the pulse width modulation signal being used to determine a turn-off moment of the main power transistor; A driving unit configured to convert the control signal into a driving signal for the main power transistor; and A switching transistor, a first end thereof being connected to an intermediate node between the comparator and the logic unit, a second end thereof being grounded, and a control end thereof being connected to the blanking signal generation circuit according to any one of claims 1-9 to shield the pulse width modulation signal during an active level of the blanking signal.

11. A switching converter, wherein, Comprising: A main power transistor and a freewheeling power transistor connected between a voltage input end and the ground, a switching node being formed therebetween; An inductor connected between the switching node and a voltage output end; And The control circuit according to claim 10 to provide a driving signal for the main power transistor.

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