Adaptive shift long cable harmonic suppression method and deployment method based on FPGA

Abstract

The invention relates to the technical field of oil and gas development, and provides a self-adaptive shift long cable harmonic suppression method and deployment method based on an FPGA (Field Programmable Gate Array), and the harmonic suppression method comprises the steps: constructing a power weight self-adaptive shift filter; acquiring frequency converter output data and a power coefficient of the submersible motor, and calculating filtering output of a power weight adaptive shift filter; calculating an error sequence and constructing an error root-mean-square criterion, calculating a gradient for the power coefficient through the error root-mean-square criterion, and updating the power coefficient; calculating a self-adaptive threshold value; and adjusting the power coefficient according to the self-adaptive threshold value and adjusting the filtering output of the power weight self-adaptive shift filter, thereby realizing harmonic suppression of the long cable. According to the invention, the power coefficient is adaptively adjusted in combination with the multi-channel parallel FPGA architecture, so that the harmonic suppression performance is improved while the filtering output calculation complexity is reduced, and the problems of high harmonic content, long processing delay and high cost in a long-line cable system are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of oil and gas development, and in particular to an adaptive shift long cable harmonic suppression method and deployment method based on FPGA. Background Art

[0002] During the oilfield exploitation process, as the exploitation depth gradually increases, a large number of harmonic components are included in the high-frequency PWM wave output by the frequency converter that controls the submersible motor. After being transmitted through a long-distance cable, the resonance is amplified step by step, resulting in the deterioration of power quality and affecting the operation efficiency of the submersible motor. Therefore, there are problems such as high harmonic content, long processing delay, and high cost in the long cable system.

[0003] The main existing methods for removing harmonics in downhole electric submersible pumps include LC filtering, active power filtering, harmonic isolation transformers, and multi-pulse rectifier transformers. LC filtering uses a combination of inductors and capacitors, or a series compensation method for harmonic suppression, but it has a high cost, a large volume, and limited suppression effect. Active power filtering is based on Kalman's adaptive harmonic detection, active harmonic control based on deep neural networks or genetic optimization, etc. However, these methods have high complexity, poor real-time performance, and great limitations in engineering implementation. Harmonic isolation transformers reduce harmonic transmission by changing the current path, usually using independent windings, closed magnetic circuits, or specific shielding structures to prevent the harmonics generated by the load from being transmitted to the power grid through the transformer, and are suitable for occasions with high harmonic pollution, but have limited filtering effect on low-frequency harmonics. Multi-pulse rectifier transformers, such as the transformers used in 12-pulse, 18-pulse, or 24-pulse frequency converters, increase the rectification phase number, raise the lowest order of harmonics, and reduce the amplitude of harmonic currents, thereby reducing the generation of harmonics. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the related technologies. For this purpose, the present invention provides an adaptive shift long cable harmonic suppression method and deployment method based on FPGA (Field Programmable Gate Array), which realizes the dynamic optimization of filter coefficients by constructing a power-weight structure and introducing an adaptive threshold criterion for the mean and variance of errors, and combines a multi-channel parallel FPGA architecture to reduce the computational complexity while improving the harmonic suppression performance, and solves the problems of high harmonic content, long processing delay, and high cost in the long cable system.

[0005] The present invention provides an adaptive shift long cable harmonic suppression method based on FPGA, including: S1: Construct a power-weight adaptive shift filter; S2: Obtain the power coefficients of the power-weight adaptive shift filter and the output data of the frequency converter of the submersible motor, and calculate the filtered output of the power-weight adaptive shift filter according to the power coefficients and the output data of the frequency converter of the submersible motor; S3: Calculate the error sequence based on the filtered output and the output data of the frequency converter of the submersible motor; S4: Construct the root mean square error criterion based on the error sequence, and calculate the gradient of the power coefficient through the root mean square error criterion to update the power coefficient; S5: Calculate the mean and variance of the error based on the error sequence, and calculate the adaptive threshold based on the mean and variance of the error; S6: Adjust the power coefficient according to the adaptive threshold and adjust the filtered output of the power - weighted adaptive shift filter according to the adjusted power coefficient to achieve harmonic suppression of the long cable.

[0006] Furthermore, in step S1, the calculation expression of the power - weighted adaptive shift filter is: ; where, is the power - weighted adaptive shift filter, is the filter order, is the filter weight, is the -th order filter power coefficient, is a complex variable, is a set of complex numbers.

[0007] Furthermore, in step S2, take the output data of the frequency converter of the submersible motor as the input data of the power - weighted adaptive shift filter, and the calculation expression of the filtered output of the power - weighted adaptive shift filter is: ; where, is the filtered output of the -th shifted power - weighted adaptive shift filter, is the input sequence of the -th shifted -th order filter, is a set of integers.

[0008] Furthermore, in step S3, the calculation expression of the error sequence is: ; where, is the error sequence of the -th shift, is the input sequence of the -th shift, is the filter order, is the filter weight, is the -th order filter power coefficient, is the The input sequence of the -th order filter for the

[0009] th shift. Further, the calculation expression of the root mean square error criterion is: ; where, is the root mean square error criterion, is the mean function, is the input sequence of the -th shift, is the filter order, is the filter weight, is the power coefficient of the -th order filter, is the input sequence of the -th order filter for the th shift.

[0010] Further, taking the gradient of the root mean square error criterion with respect to the power coefficient and updating the power coefficient, the calculation expression for the power coefficient update is: ; where, is the updated power coefficient of the -th order, is the power coefficient of the -th order before update, is the compensation factor, is the error sequence of the th shift, is the input sequence of the -th order filter for the th shift, is the sign function.

[0011] Further, in step S5, the calculation expression of the adaptive threshold is: ; where, is the adaptive threshold of the th shift, is the first forgetting factor, is the second forgetting factor, is the adaptive threshold of the th shift, is the error mean of the th shift, is the confidence coefficient, is the error standard deviation of the th shift, is the error mean of the th shift, is the error sequence for the th shift, and is the standard deviation of the error for the

[0012] Further, in step S6,

[0013] wherein, is the updated th order power coefficient, is the th order power coefficient before update, is the error sequence for the th shift, and is the adaptive threshold for the

[0014] The present invention also provides a deployment method for deploying the above-mentioned FPGA-based adaptive shift long cable harmonic suppression method on a multi-channel parallel FPGA architecture, including the following steps: S100: Select a system clock frequency, which is determined by the well depth; S200: Determine the resource occupancy of the input signal buffer module, parameter storage module, and adaptive filtering module according to the filter length, data bit width, and system clock; S300: The power-weighted adaptive shift filter adopts a two-stage pipelined structure. The first-stage pipelined structure is used to process the reading of power coefficients and the shift accumulation operation of data, and the second-stage pipelined structure is used for the adaptive update of power coefficients; S400: Calculate cross-errors for the filtering results of each channel of the power-weighted adaptive shift filter to obtain multiple errors, and perform weighted combination on the multiple errors; Calculate the errors by calculating the errors between the filtering outputs of multiple parallel channels and the same reference signal, and perform weighted combination on the multiple errors. The calculation expression is: ; wherein, is the cross-error, is the number of parallel channels, is the th weight coefficient of the th th shift input sequence, is the th th shift power-weighted adaptive shift filter output of the S500: Perform weighted averaging on the filtering results of multiple parallel channels.

[0015] Furthermore, the multi-channel parallel FPGA architecture includes: An input signal buffer module, which is a 20×16-bit FIFO shift register for storing the inverter output data of the submersible motor. A parameter storage module for storing power coefficients. An adaptive filtering module, including a power-weighted adaptive shift filter, which is a cascaded 20-channel 16-bit shift adder for calculating the filtering output of the power-weighted adaptive shift filter and adjusting the power coefficients.

[0016] One or more of the above technical solutions in the embodiments of the present invention have at least one of the following technical effects: By adaptively adjusting the power coefficients in combination with the multi-channel parallel FPGA architecture, the present invention reduces the computational complexity while improving the harmonic suppression performance, and solves the problems of high harmonic content, long processing delay, and high cost in the long cable system.

[0017] The additional aspects and advantages of the present invention will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present invention. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a schematic flowchart of a method for suppressing harmonics in a long cable based on FPGA provided by the present invention.

[0020] Figure 2 is a schematic flowchart of a deployment method.

[0021] Figure 3 is a timing relationship diagram between key signals during data transmission using the FPGA parallel architecture of the present invention.

[0022] Figure 4 is a schematic diagram of voltage waveforms before and after harmonic filtering of a long cable in an embodiment of the present invention.

[0023] Figure 5 is a schematic diagram of the change of each harmonic component of a long cable in an embodiment of the present invention. Detailed Embodiments

[0024] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0025] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0026] The following will describe Figures 1 to 5 a method for suppressing harmonic waves of a long cable with adaptive shift length based on FPGA and a deployment method of the present invention.

[0027] As Figure 1 shown, a method for suppressing harmonic waves of a long cable with adaptive shift length based on FPGA includes: S1: Construct a power-weighted adaptive shift filter; The calculation expression of the power-weighted adaptive shift filter is: ; wherein, is the power-weighted adaptive shift filter, is the filter order, is the filter weight, is the power coefficient of the order filter, is a complex variable,

[0028] S2: Obtain the power coefficients of the power-weighted adaptive shift filter and the output data of the frequency converter of the submersible motor, and calculate the filtered output of the power-weighted adaptive shift filter according to the power coefficients and the output data of the frequency converter of the submersible motor; Take the inverter output data of the submersible motor as the input data of the power-weighted adaptive shift filter. The calculation expression of the filtered output of the power-weighted adaptive shift filter is: ; Where, is the filtered output of the -th shift power-weighted adaptive shift filter, is the input sequence of the -th shift and -th order filter, is a set of integers.

[0029] The inverter output data of the submersible motor is stored through a shift storage module. The shift storage module includes N cascaded B-bit shift registers; the power coefficient is stored through a parameter storage module; the filtered output is obtained through calculation by the power-weighted adaptive shift filter; through N parallel B-bit shift accumulations, each accumulation , and then cascade summation is performed to obtain the filtered output.

[0030] The standard FIR filter is: ; Where, is the transfer function of the standard FIR filter, is the -th order input of the standard FIR filter, and the standard FIR filter uses floating-point multiplication operations.

[0031] The present invention simplifies the floating-point multiplication operation in the standard FIR filter to a shift operation of integer powers, greatly reducing the computational complexity and saving computing resources.

[0032] S3: Calculate the error sequence according to the filtered output and the inverter output data of the submersible motor; The calculation expression of the error sequence is: ; Where, is the error sequence of the -th shift, is the input sequence of the -th shift, is the filter order, is the filter weight, is the power coefficient of the -th order filter, is the -th shift and -th order filter input sequence.

[0033] S4: Construct the root mean square error criterion based on the error sequence, and calculate the gradient of the power coefficient through the root mean square error criterion to update the power coefficient; The calculation expression of the root mean square error criterion is: ; where, is the root mean square error criterion, is the mean function, is the th shifted input sequence, is the filter order, is the filter weight, is the power coefficient of the th order filter, is the th shifted th order filter input sequence.

[0034] The calculation expression for calculating the gradient of the root mean square error criterion with respect to the power coefficient and updating the power coefficient is:

[0035] where, is the updated th order power coefficient, is the previous th order power coefficient, is the compensation factor, is the error sequence of the th shift, is the th shifted th order filter input sequence, is the sign function.

[0036] In some specific embodiments of the present invention, the value range of is (0, 1), which is used to control the convergence rate.

[0037] S5: Calculate the error mean and variance based on the error sequence, and calculate the adaptive threshold according to the error mean and variance; The calculation expression of the adaptive threshold is: ; where, is the th shifted adaptive threshold, is the first forgetting factor, is the second forgetting factor, is the th shifted adaptive threshold, is the th shifted error mean, is the confidence coefficient, is the standard deviation of the error of the -th shift, is the mean value of the error of the -th shift, is the error sequence of the -th shift, is the standard deviation of the error of the -th shift.

[0038] In some specific embodiments of the present invention, and both have a value range of (0, 1), takes a value of (2, 3), the first forgetting factor , the second forgetting factor are related to the depth of the submersible electric pump and the harmonic content, and are constants less than 1; the confidence coefficient is related to the system noise characteristics and error propagation, and its initial range is between 2 and 3. Through a large number of simulation analyses and combined with the actual working conditions, when the depth of the submersible electric pump is 500m - 3000m and the different harmonic contents are between 5% - 25%, , both have an optimal value of 0.995, the optimal value of is approximately 2.8; The actual application tests in different well sites show that the above parameters can adapt to the actual working conditions of most oil wells, meet the requirements of the depth of the submersible electric pump and the development of each oil field in China, and can be fine-tuned within the range of ±5% according to the specific on-site working conditions during actual deployment.

[0039] The iterative formula for the mean value of the error is: ; The iterative formula for the variance of the error is: ; The calculation expression for the adaptive threshold is: ; S6: Adjust the power coefficient according to the adaptive threshold and adjust the filtering output of the power-weighted adaptive shift filter according to the adjusted power coefficient to achieve harmonic suppression of the long cable; ; Among them, is the updated -th order power coefficient, is the previous -th order power coefficient, is the error sequence of the -th shift, is the Adaptive threshold of the secondary shift.

[0040] As Figure 2 shown, a deployment method for deploying an FPGA-based adaptive shift long cable harmonic suppression method on a multi-channel parallel FPGA architecture includes: S100: Select the system clock frequency, which is determined by the well depth; In some specific embodiments of the present invention, the system clock frequency is 100 MHz to 500 MHz, suitable for a well depth of 500 m to 3000 m.

[0041] S200: Determine the resource occupancy of the input signal buffer module, parameter storage module, and adaptive filter module according to the filter length, data bit width, and system clock; S300: The power-law weighted adaptive shift filter adopts a two-stage pipelined structure. The first-stage pipelined structure is used to process the reading of the power-law coefficients and the shift accumulation operation of the data, and the second-stage pipelined structure is used for the adaptive update of the power-law coefficients; The two-stage pipelined structure of the present invention establishes an independent data processing path for each parallel channel, and each channel simultaneously performs shift operations, power-law calculations, and filtering operations.

[0042] S400: Perform cross-error calculation on the filtering results of each channel of the power-law weighted adaptive shift filter to obtain multiple errors, and perform weighted combination on the multiple errors; Calculate the errors by calculating the errors between the filtering outputs of multiple parallel channels and the same reference signal, and perform weighted combination on the multiple errors. The calculation expression is: ; Among them, is the cross-error, is the number of parallel channels, is the weight coefficient of the th channel, is the th shift input sequence, is the th filtering output of the power-law weighted adaptive shift filter of the S500: Perform weighted averaging on the filtering results of multiple parallel channels.

[0043] The robustness of the system can be effectively improved through reasonable allocation of weights.

[0044] The multi-channel parallel FPGA architecture includes: Input signal buffer module, which is a 20×16-bit FIFO shift register for storing the output data of the frequency converter of the submersible motor. Parameter storage module for storing the power coefficient. Adaptive filtering module, including a power-weighted adaptive shift filter, which is a cascaded 20-channel 16-bit shift adder for calculating the filtering output of the power-weighted adaptive shift filter and adjusting the power coefficient.

[0045] For a submersible motor drive system in an oilfield, the well depth is known to be 2500 meters, the rated power of the motor is 160 kW, the rated voltage is 690 V, and the switching frequency of the frequency converter is 4 kHz. The dead time , and the FPJP-3*95mm 2 cable is used. According to the measured data on the wellhead, the 5th harmonic component in the phase voltage of the cable is as high as 20% of the fundamental component, the 7th harmonic component is as high as 15% of the fundamental component, the 11th harmonic component is as high as 8% of the fundamental component, and the 13th harmonic component is as high as 4% of the fundamental component, resulting in serious deterioration of the system power factor and power quality.

[0046] According to the actual working conditions, the filter order N = 20 and the quantization bit width B = 16 are selected, and the system clock frequency . At the same time, based on a large number of experiments and expert experience, the compensation factor in the adaptive filter , in the weight update step, , .

[0047] Hardware deployment of the algorithm: Select the input signal buffer module to use a 20×16-bit FIFO shift register for storing the input voltage signal sequence ; the parameter storage module has a size of 20×4 for storing the corresponding power coefficient ; the adaptive filtering module is composed of a cascaded 20-channel 16-bit shift adder for calculating the filtering output : ; Calculating the error signal: ; The iterative formula for the error mean is: ; The iterative formula for the error variance is: ; The calculation expression for the adaptive threshold is: ; Dynamically update the power coefficient. According to the updated power coefficient, calculate the filtering output of the power-weight adaptive shift filter.

[0048] As Figure 3 shown, the timing relationship diagram between key signals when the present invention uses the FPGA parallel architecture for data transmission is detailed. The main clock (CLK) has a duty cycle characteristic of 50%. At the rising edge of the main clock, the enable signal (EN) is activated, and then the data signal (DATA) remains stable after the setup time. The update signal (UPDATE) is triggered in the next clock cycle after the data is stable to control the update timing of the weight parameters.

[0049] As Figure 4 in Figure (a) is the voltage waveform before filtering. As Figure 4 in Figure (b) in is the voltage waveform after being processed by a 20th-order adaptive shift filter. As Figure 4 shown, the distortion of the processed voltage waveform is significantly improved, and the waveform has approached a sine curve.

[0050] As Figure 5 shown, the changes in each harmonic component are quantitatively analyzed. After filtering, the content of the 5th harmonic drops from 16% to 3%, the 7th harmonic drops from 12% to 2%, the 11th harmonic drops from 7% to 1%, and the 13th harmonic drops from 4% to 0.6%. The harmonic suppression effect is significant.

[0051] Use LC passive filtering, FIR digital filtering, and the present invention to filter the harmonic data of the same long cable. The comprehensive performance indicators of different filters are shown in Table 1.

[0052] Table 1 Comprehensive performance indicators of different filters

[0053] The present invention realizes the dynamic optimization of filter coefficients by constructing a power-weight structure and introducing an adaptive threshold criterion for the mean and variance of errors, and combines a multi-channel parallel FPGA architecture to reduce the computational complexity while improving the harmonic suppression performance, solving the problems of high harmonic content, long processing delay, and high cost in the long cable system.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An FPGA-based adaptive shift long cable harmonic suppression method, characterized in that Including: S1: Construct a power - weighted adaptive shift filter; S2: Obtain the power coefficients of the power - weighted adaptive shift filter and the output data of the frequency converter of the submersible motor, and calculate the filtered output of the power - weighted adaptive shift filter according to the power coefficients and the output data of the frequency converter of the submersible motor; S3: Calculate the error sequence according to the filtered output and the output data of the frequency converter of the submersible motor; S4: Construct an error root - mean - square criterion according to the error sequence, and calculate the gradient of the power coefficients through the error root - mean - square criterion to update the power coefficients; S5: Calculate the error mean and variance according to the error sequence, and calculate the adaptive threshold according to the error mean and variance; S6: Adjust the power coefficients according to the adaptive threshold and adjust the filtered output of the power - weighted adaptive shift filter according to the adjusted power coefficients to achieve harmonic suppression of long cables.

2. The adaptive shift long cable harmonic suppression method based on FPGA according to claim 1, wherein In step S1, the calculation expression of the power - weighted adaptive shift filter is: ； Among them, is a power - weighted adaptive shift filter, is the filter order, is the filter weight, is the power coefficient of the - th order filter, is a complex variable, is a set of complex numbers.

3. The adaptive shift-length cable harmonic suppression method based on FPGA according to claim 2, wherein In step S2, take the output data of the frequency converter of the submersible motor as the input data of the power - weighted adaptive shift filter, and the calculation expression of the filtered output of the power - weighted adaptive shift filter is: ； Among them, is the filtering output of the -th shifted power-weighted adaptive shift filter, is the input sequence of the -th shifted -th order filter, is a set of integers.

4. The adaptive shift long cable harmonic suppression method based on FPGA according to claim 1, characterized in that In step S3, the calculation expression of the error sequence is: ； Among them, is the error sequence of the th shift, is the input sequence of the th shift, is the filter order, is the filter weight, is the power coefficient of the th-order filter, is the input sequence of the th shift for the th-order filter.

5. A method for suppressing harmonic waves of an adaptive shift long cable based on FPGA according to claim 1, characterized in that, The calculation expression of the error root - mean - square criterion is: ； Among them, is the root mean square error criterion, is the mean function, is the -th shifted input sequence, is the filter order, is the filter weight, is the power coefficient of the -th order filter, is the -th shifted input sequence of the -th order filter.

6. The adaptive shift long cable harmonic suppression method based on FPGA according to claim 5, characterized in that Take the gradient of the error root - mean - square criterion with respect to the power coefficients to update the power coefficients, and the calculation expression of the power coefficient update is: ； Among them, is the -th order power coefficient after update, is the -th order power coefficient before update, is the compensation factor, is the error sequence of the -th shift, is the input sequence of the -th shift and the -th order filter, is the sign function.

7. A method for suppressing harmonic waves of an adaptive shift long cable based on FPGA according to claim 1, characterized in that In step S5, the calculation expression of the adaptive threshold is: ； wherein, is the adaptive threshold for the -th shift, is the first forgetting factor, is the second forgetting factor, is the adaptive threshold for the -th shift, is the mean error for the -th shift, is the confidence coefficient, is the standard deviation of the error for the -th shift, is the mean error for the -th shift, is the error sequence for the -th shift, is the standard deviation of the error for the -th shift.

8. A method for suppressing harmonic waves of an adaptive shift long cable based on FPGA according to claim 1, characterized in that, In step S6, ； Among them, is the th power coefficient after update, is the th power coefficient before update, is the error sequence of the th shift, is the adaptive threshold of the 9. A deployment method, characterized in that, To deploy the adaptive shift long - cable harmonic suppression method based on FPGA described in any one of claims 1 to 8 on a multi - channel parallel FPGA architecture, the following steps are included: S100: Select the system clock frequency, and the system clock frequency is determined by the well depth; S200: Determine the resource occupancy of the input signal buffer module, parameter storage module, and adaptive filtering module according to the filter length, data bit - width, and system clock; S300: The power - weighted adaptive shift filter adopts a two - stage pipelined structure. The first - stage pipelined structure is used to process the reading of power coefficients and the shift - accumulation operation of data, and the second - stage pipelined structure is used for the adaptive update of power coefficients; S400: Perform cross - error calculation on the filtered results of each channel of the power - weighted adaptive shift filter to obtain multiple errors, and perform weighted combination on the multiple errors; Calculate the errors between the filtered outputs of multiple parallel channels and the same reference signal, and perform weighted combination on the multiple errors. The calculation expression is: ； Among them, is the cross error, is the number of parallel channels, is the weight coefficient of the th channel, is the th shifted input sequence, is the filtering output of the th power weight adaptive shift filter of the th channel; S500: Perform weighted averaging on the filtered results of multiple parallel channels.

10. A deployment method according to claim 9, characterized in that, The multi - channel parallel FPGA architecture includes: An input signal buffer module, which is a 20×16 - bit FIFO shift register used to store the output data of the frequency converter of the submersible motor; A parameter storage module used to store power coefficients; An adaptive filtering module, including a power - weighted adaptive shift filter. The power - weighted adaptive shift filter is a cascaded 20 - way 16 - bit shift adder used to calculate the filtered output of the power - weighted adaptive shift filter and adjust the power coefficients.

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