Overcurrent protection circuit, switching power supply and electronic equipment
By setting resistors and capacitors in flyback or forward circuits, the on-conductance and shutdown timing of the switch tube is accurately controlled, and the problem of degradation of current control accuracy under high-frequency PWM signals is solved, overcurrent protection is achieved, and the safety and response capabilities of the circuit are improved.
Patent Information
- Application Number
- CN202510411505.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-22
AI Technical Summary
In the flyback circuit or forward circuit of peak current control mode, the delay error under high-frequency PWM signal causes the current control accuracy to decrease, which may cause the starter current to lose control, resulting in the transformer saturation, abnormal circuit or damage.
By using an overcurrent protection circuit, by setting the first resistor, the second resistor and the first capacitor, the on-off timing of the switching tube is accurately controlled, the duty cycle of the PWM signal is adjusted, the abnormal current is quickly identified and the protection mechanism is triggered.
Improves the safety and reliability of the circuit, reduces the risk of potential damage, and ensures the accuracy of current control and rapid response capabilities.
Smart Images
Figure CN120357726A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of electronic circuits, and relates to, but is not limited to, an overcurrent protection circuit, a switching power supply, and an electronic device. Background Art
[0002] In a flyback circuit or a forward circuit with peak current control mode, due to the delay error of the control signal, when the switching frequency is high and the duty cycle of the Pulse-Width Modulation (PWM) signal is small, the proportion of the delay error in the PWM signal will increase significantly, resulting in a decrease in current control accuracy. Especially when the input voltage is high, the output load is a large capacitive load, or the turns ratio of the primary and secondary sides is small, this delay error may cause the startup current to get out of control, and then lead to transformer saturation, abnormal circuit operation, or even damage. Summary of the Invention
[0003] In view of this, embodiments of the present disclosure provide an overcurrent protection circuit, a switching power supply, and an electronic device.
[0004] In a first aspect, the present disclosure provides an overcurrent protection circuit, including: a control chip, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a first diode; wherein, the first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor;
[0005] The first pole of the first switching transistor is connected to the reference voltage terminal pin of the control chip through the first resistor after being connected to the third pole of the second switching transistor, and the first pole of the first switching transistor is connected to the second pole of the second switching transistor through the second resistor;
[0006] The second pole of the first switching transistor is connected to the first end of the third resistor and then connected to the current sampling terminal through the first diode; the third pole of the first switching transistor is connected to the second end of the third resistor, and the third pole of the first switching transistor is grounded through the fifth resistor;
[0007] The second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the current detection input terminal pin of the control chip;
[0008] The first end of the first capacitor is connected to the first pole of the first switching transistor; the second end of the first capacitor is connected to the first end of the fourth resistor;
[0009] The first pole of the second switching transistor is connected to the second end of the fourth resistor and then grounded through the second capacitor.
[0010] In some embodiments, the cathode of the first diode is connected to the third pole of the first switching transistor and the first end of the third resistor, and the anode of the first diode is connected to the current sampling terminal.
[0011] In some embodiments, the overcurrent protection circuit further includes a second diode, the cathode of the second diode is connected to the second pole of the first switching transistor, and the anode of the second diode is connected to the cathode of the first diode.
[0012] In some embodiments, the overcurrent protection circuit further includes a sixth resistor and a seventh resistor;
[0013] The first end of the sixth resistor is connected to the second pole of the first switching transistor, and the second end of the sixth resistor is connected to the cathode of the second diode;
[0014] The first end of the seventh resistor is connected to the first pole of the second switching transistor, and the second end of the seventh resistor is connected to the second end of the fourth resistor.
[0015] In some embodiments, the first switching transistor is an NPN-type triode, and the second switching transistor is a PNP-type triode; wherein, the first pole is the collector, the second pole is the base, and the third pole is the emitter;
[0016] Or,
[0017] The first switching transistor is an NMOS transistor, and the second switching transistor is a PMOS transistor; wherein, the first pole is the drain, the second pole is the gate, and the third pole is the source.
[0018] In some embodiments, the capacitance value of the first capacitor ranges from 10 nF to 30 nF;
[0019] The resistance value of the first resistor ranges from 10 kΩ to 20 kΩ;
[0020] The resistance value of the second resistor ranges from 3 kΩ to 5 kΩ.
[0021] In a second aspect, the present disclosure provides an overcurrent protection circuit, including: a control chip, a third switching transistor, a fourth switching transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, and a fourth capacitor; wherein, both the third switching transistor and the fourth switching transistor are N-type transistors;
[0022] After the first ends of the eighth resistor and the ninth resistor are connected, they are connected to the reference voltage pin of the control chip;
[0023] The second terminal of the eighth resistor, the first terminal of the third capacitor, and the third pole of the third switching transistor are connected and then connected to the oscillation timing pin of the control chip, and the second terminal of the third capacitor is grounded;
[0024] The first pole of the third switching transistor is connected to the second terminal of the ninth resistor; the second pole of the third switching transistor, the first terminal of the fourth capacitor, and the first pole of the fourth switching transistor are connected and then connected to the reference voltage pin of the control chip through the tenth resistor;
[0025] The second pole of the fourth switching transistor is connected to the output terminal pin of the internal error amplifier of the control chip; the third pole of the fourth switching transistor is connected to the second terminal of the fourth capacitor and then grounded;
[0026] The first terminal and the second terminal of the eleventh resistor are respectively connected to the output terminal pin of the internal error amplifier of the control chip and the second pole of the fourth switching transistor;
[0027] The first terminal and the second terminal of the twelfth resistor are respectively connected to the second pole and the third pole of the fourth switching transistor.
[0028] In some embodiments, the third switching transistor is an NMOS transistor, and the fourth switching transistor is an NPN bipolar transistor;
[0029] Wherein, the first pole of the third switching transistor is the drain, the second pole of the third switching transistor is the gate, and the third pole of the third switching transistor is the source; the first pole of the fourth switching transistor is the collector, the second pole of the fourth switching transistor is the base, and the third pole of the fourth switching transistor is the emitter.
[0030] In some embodiments, the capacitance value of the fourth capacitor ranges from 100 nF to 150 nF; the resistance value of the tenth resistor ranges from 10 kΩ to 20 kΩ.
[0031] In a third aspect, an embodiment of the present disclosure provides a switching power supply, including: a forward circuit or a flyback circuit and the overcurrent protection circuit according to any one of the first aspect or the overcurrent protection circuit according to any one of the second aspect.
[0032] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including the switching power supply as described in the third aspect.
[0033] In the embodiments of the present disclosure, by setting a first resistor, a second resistor, and a first capacitor and further setting the parameters of the first resistor, the second resistor, and the first capacitor, precise control of the on and off timing of the first switching transistor and the second switching transistor is achieved. On the one hand, the circuit can be controlled to skip the number of cycles of the PWM signal to adjust the duty cycle of the PWM signal, and the magnitude of the starting current is controlled by effectively reducing the duty cycle of the PWM signal, thereby achieving precise overcurrent protection and significantly improving the safety of the circuit. On the other hand, the setting of the first resistor, the second resistor, and the first capacitor enables the circuit to quickly identify and respond to abnormal currents, promptly trigger the protection mechanism, and reduce the potential damage risk. Description of the Drawings
[0034] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0035] Figure 1 In Figure (a), it is a schematic diagram of the sampled current changing with time. Figure 1 In Figure (b), it is a schematic diagram of the voltage of the PWM signal changing with time.
[0036] Figure 2 It is one of the specific structural diagrams of the isolation drive circuit provided by an embodiment of the present disclosure.
[0037] Figure 3 It is another specific structural diagram of the isolation drive circuit provided by an embodiment of the present disclosure.
[0038] Figure 4 In Figure (a), it is the relationship between the sampled current and time. Figure 4 In Figure (b), it is the relationship between the voltage obtained by converting the sampled current and time. Figure 4 In Figure (c), it is a schematic diagram of the voltage of the PWM signal changing with time.
[0039] Figure 5 It is the specific structural diagram of the isolation drive circuit provided by another embodiment of the present disclosure.
[0040] Figure 6 It is one of the schematic diagrams of the relationship between the gate-source voltage of the third switching transistor and time and the relationship between the voltage Vcom and time provided by another embodiment of the present disclosure.
[0041] Figure 7 It is another schematic diagram of the relationship between the gate-source voltage of the third switching transistor and time and the relationship between the voltage Vcom and time provided by another embodiment of the present disclosure.
[0042] Figure 8 The third schematic diagram showing the relationship between the gate-source voltage of the third switching transistor and time and the relationship between the voltage Vcom and time provided in another embodiment of the present disclosure;
[0043] Figure 9 The fourth schematic diagram showing the relationship between the gate-source voltage of the third switching transistor and time and the relationship between the voltage Vcom and time provided in another embodiment of the present disclosure;
[0044] Figure 10 An optional structural schematic diagram of the switching power supply provided in an embodiment of the present disclosure. Detailed implementation manners
[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will further describe the specific technical solutions of the application in detail with reference to the accompanying drawings in the embodiments of the present disclosure. The following embodiments are used to illustrate the present disclosure but are not used to limit the scope of the present disclosure.
[0046] In the following description, "some embodiments" are described, which are subsets of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.
[0047] In the following description, the terms "first / second / third" are only used to distinguish different objects and do not represent a specific order for the objects, and there is no limitation on the order of precedence. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
[0049] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.
[0050] In the related art, Figure 1 shows the possible delay problems in the current control process in a switching power supply controlled by PWM (pulse width modulation). Figure 1 Figure (a) in [reference] shows the relationship between current and time, where Icontrol is the set current limit value. Figure 1Figure (b) therein shows the variation of the voltage of the corresponding PWM signal with time.
[0051] When the conduction time of the PWM signal is very short, as Figure 1 shown in Figure (a) therein, when the current sampling signal reaches the current limit value Icontrol at time t1, ideally the PWM signal should turn off at time t1, and the actual conduction time of the PWM signal should be Δt1, that is, the time interval between time t1 and time t0. However, due to the delay in the turn-off of the PWM signal, the actual turn-off time of the PWM signal is time t2. Therefore, the actual conduction time of the PWM signal becomes Δt2, that is, the time interval between time t2 and time t0. After the time interval T1, the circuit continues to generate waves at time t3, which results in the actual duty cycle of the PWM signal being higher than the theoretical value. This delay effect will cause the current to continue to rise, possibly exceeding the set limit current value, thereby causing abnormal current control or even out-of-control. Especially when the input voltage is high, the output load is a large capacitive load, or the turns ratio of the primary and secondary windings of the transformer is small, the influence of this delay error is more significant, which may cause transformer saturation, abnormal circuit operation, or damage.
[0052] In view of this, the present disclosure proposes the following embodiments.
[0053] In a first aspect, an overcurrent protection circuit according to an embodiment of the present disclosure, as Figure 2 shown, the overcurrent protection circuit includes: a control chip IC1, a first switching transistor Q1, a second switching transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, and a first diode D1; wherein, the first switching transistor Q1 is an N-type transistor, and the second switching transistor Q2 is a P-type transistor.
[0054] Referring to Figure 2 , the first pole of the first switching transistor Q1 is connected to the third pole of the second switching transistor Q2 through the first resistor R1 and then connected to the reference voltage terminal pin of the control chip IC1 ( Figure 2 the eighth pin VREF shown in Figure 2The third pin (CS) shown in the figure is connected; the first end of the first capacitor C1 is connected to the first pole of the first switching transistor Q1; the second end of the first capacitor C1 is connected to the first end of the fourth resistor R4; the first pole of the second switching transistor Q2 is connected to the second end of the fourth resistor R4 and then grounded through the second capacitor C2.
[0055] In some embodiments, the model of the control chip IC1 is UCC28C44. Exemplarily, the control chip has 8 pins, namely the internal error amplifier output terminal pin (COMP pin), the feedback pin (FB pin), the current detection input terminal pin (CS pin), the oscillation timing pin (RT / CT pin 4), the ground pin (GND pin), the output pin (OUT pin), the power supply pin (VDD pin), and the reference voltage terminal pin (VREF pin).
[0056] In some embodiments, a current transformer CT1 can be used for current sampling. Exemplarily, as Figure 2 shown, the current transformer CT1 is a transformer. The primary winding of the current transformer CT1 is connected to the circuit to be sampled, used to sense the current flowing through the circuit to be sampled. The secondary winding of the current transformer CT1 outputs a current proportional to the primary current, and this current can be detected and processed by other parts in the circuit (such as the control chip). Specifically, the same-name end a of the secondary winding of the current transformer CT1 can be understood as the current sampling end, and the different-name end b of the secondary winding of the current transformer CT1 is grounded, which helps to provide a stable reference point, reduce noise interference, and ensure the safe operation of the circuit.
[0057] In some embodiments, as Figure 2 shown, the first end of the fifth resistor R5 is connected to the third pole of the first switching transistor Q1, and the second end of the fifth resistor R5 is grounded.
[0058] In some embodiments, as Figure 3 shown, the overcurrent protection circuit further includes a second diode D2. The cathode of the second diode D2 is connected to the second pole of the first switching transistor Q1, and the anode of the second diode D2 is connected to the cathode of the first diode D1.
[0059] In some embodiments, the second diode D2 is used to reduce the error in controlling the conduction timing of the first switching transistor Q1.
[0060] In some embodiments, as Figure 3As shown, the overcurrent protection circuit further includes a sixth resistor R6 and a seventh resistor R7; a first end of the sixth resistor R6 is connected to a second pole of the first switching transistor Q1, and a second end of the sixth resistor R6 is connected to a cathode of the second diode D2; a first end of the seventh resistor R7 is connected to a first pole of the second switching transistor Q2, and a second end of the seventh resistor R7 is connected to a second end of the fourth resistor R4.
[0061] In some embodiments, the sixth resistor R6 is used to limit the value of the current flowing through the second pole of the first switching transistor Q1. Exemplarily, when the first switching transistor Q1 is an NPN-type triode and the second switching transistor Q2 is a PNP-type triode, the sixth resistor R6 is used to limit the current flowing through the base of the first switching transistor Q1.
[0062] In some embodiments, the sixth resistor R6 is further used to limit the current flowing through the first diode D1, protecting the first diode D1 from damage caused by excessive current.
[0063] In some embodiments, as Figure 3 shown, the overcurrent protection circuit further includes a second diode D2, a cathode of the first diode D1 and an anode of the second diode D2 are connected to a first end of the third resistor R3, and an anode of the first diode D1 is connected to the current sampling terminal.
[0064] In some embodiments, the seventh resistor R7 serves as a voltage-dividing resistor and works in cooperation with the fourth resistor R4 and the fifth resistor R5 to precisely control the voltage on the second capacitor C2, ensuring that the current detection input terminal pin (CS pin) of the control chip IC1 is not damaged due to excessive voltage. This voltage-dividing strategy can protect circuit components from voltage surges, enhancing the stability and reliability of the entire system, not only improving the safety of the circuit but also helping to extend the service life of the control chip. In some embodiments, the first switching transistor Q1 is an NPN-type triode and the second switching transistor Q2 is a PNP-type triode; wherein, the first pole is the collector, the second pole is the base, and the third pole is the emitter; alternatively, the first switching transistor is an NMOS transistor and the second switching transistor is a PMOS transistor; wherein, the first pole is the drain, the second pole is the gate, and the third pole is the source.
[0065] Next, refer to Figure 3 and Figure 4 for a detailed introduction to the working principle of the overcurrent protection circuit.
[0066] Figure 4 The figure (a) in shows the variation relationship of the sampled current with time. Figure 4 The figure (b) in shows the variation relationship of the voltage obtained by converting the sampled current with time,Figure 4 Figure (c) therein shows the variation of the voltage of the corresponding PWM signal over time.
[0067] As Figure 3 and Figure 4 shown, in the overcurrent protection circuit, the current transformer CT1 detects the current signal ics of the circuit to be sampled. The current signal ics flows through the third resistor R3 and the fifth resistor R5, and after voltage division, a voltage signal Vcs is generated. After passing through the fourth resistor R4 and the second capacitor C2, a stable voltage signal Vcs is obtained and transmitted to the CS pin of the control chip IC1. The third resistor R3 and the fifth resistor R5 are used for current detection, converting the current signal into a voltage signal, while the low-pass filter jointly constructed by the fourth resistor R4 and the second capacitor C2 can effectively filter out high-frequency interference signals to ensure the stability of the voltage signal. Through the filtering process of the fourth resistor R4 and the second capacitor C2, the signal received by the CS pin of the control chip IC1 is kept stable, thus avoiding misoperations caused by current fluctuations.
[0068] At time t1, the current signal ics reaches the current limiting value Icontrol. At time t4, the current signal ics reaches the set protection threshold (such as Iset). The voltage Vset on the third resistor R3 will cause the first switching transistor Q1 to conduct. At this time, the first capacitor C1 is clamped to 0V, and then the second switching transistor Q2 is turned on, thereby pulling up the Vcs voltage and triggering the current limiting protection mechanism. This causes the PWM signal to turn off and the starting current to start to decrease. At time t2, the first switching transistor Q1 returns to the off state, but since the first capacitor C1 needs to be recharged through the first resistor R1 and the second resistor R2, the second switching transistor Q2 continues to be in the on state, and the voltage signal Vcs remains at a high voltage state, and the circuit is still in the current limiting protection state. During this period, the PWM signal cannot be issued, and the circuit skips the current cycle. Only when the first capacitor C1 is fully charged will the second switching transistor Q2 turn off at time t5, enabling the circuit to resume normal PWM signal output at time t6.
[0069] In some embodiments, the set protection threshold (such as Iset) is greater than the current limiting value Icontrol.
[0070] As Figure 4 shown, the time interval between two adjacent PWM signal pulses can be increased from T1 to T2 to reduce the duty cycle of the PWM signal.
[0071] In some embodiments, the capacitance value of the first capacitor ranges from 10 nF to 30 nF. More specifically, the capacitance value of the first capacitor can be 10 nF, 15 nF, 20 nF, 25 nF, or 30 nF.
[0072] In some embodiments, the resistance value of the first resistor ranges from 10 kΩ to 20 kΩ. More specifically, the resistance value of the first resistor can be 10 kΩ, 15 kΩ, or 20 kΩ.
[0073] In some embodiments, the resistance value of the second resistor ranges from 3 kΩ to 5 kΩ. More specifically, the resistance value of the second resistor can be 3 kΩ, 4 kΩ, or 5 kΩ. It should be noted that the capacitance value of the first capacitor, the resistance value of the first resistor, and the resistance value of the second resistor are only examples. In practical applications, on the premise of meeting the charge and discharge time requirements of the first capacitor C1, the capacitance value of the first capacitor, the resistance value of the first resistor, and the resistance value of the second resistor can be reasonably selected in combination with the specific circuit and application scenario.
[0074] In the embodiments of the present disclosure, by setting the first resistor R1, the second resistor R2, and the first capacitor C1 and further setting the parameters of the first resistor R1, the second resistor R2, and the first capacitor C1, precise control of the on and off timing of the first switching transistor Q1 and the second switching transistor Q2 is achieved. On the one hand, the number of PWM signal cycles that the circuit can skip can be controlled to adjust the duty cycle of the PWM signal, and the starting current can be controlled by effectively reducing the duty cycle of the PWM signal to achieve precise overcurrent protection, significantly improving the safety of the circuit. On the other hand, the setting of the first resistor R1, the second resistor R2, and the first capacitor C1 enables the circuit to quickly identify and respond to abnormal currents, promptly trigger the protection mechanism, and reduce the potential damage risk.
[0075] In a second aspect, the embodiments of the present disclosure provide an overcurrent protection circuit, such as Figure 5As shown, the overcurrent protection circuit includes: a control chip IC1, a third switch Q3, a fourth switch Q4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, and a fourth capacitor C4; wherein, the third switch Q3 and the fourth switch Q4 are both N-type transistors; the first ends of the eighth resistor R8 and the ninth resistor R9 are connected and then connected to the reference voltage pin (VREF pin) of the control chip IC1; the second end of the eighth resistor R8, the first end of the third capacitor C3, and the third pole of the third switch Q3 are connected and then connected to the oscillation timing pin (RT / CT pin) of the control chip IC1, and the second end of the third capacitor C3 is grounded; the first pole of the third switch Q3 is connected to the second end of the ninth resistor R9; the second pole of the third switch Q3, the first end of the fourth capacitor C4, and the first pole of the fourth switch Q4 are connected and then connected to the reference voltage pin (VREF pin) of the control chip IC1 through the tenth resistor R10; the second pole of the fourth switch Q4 is connected to the output terminal pin of the internal error amplifier of the control chip IC1; the third pole of the fourth switch Q4 is connected to the second end of the fourth capacitor C4 and then grounded; the first end and the second end of the eleventh resistor R11 are respectively connected to the output terminal pin of the internal error amplifier (COMP pin) of the control chip IC1 and the second pole of the fourth switch Q4; the first end and the second end of the twelfth resistor R12 are respectively connected to the second pole and the third pole of the fourth switch Q4.
[0076] In some embodiments, the eleventh resistor R11 and the twelfth resistor R12 form a voltage dividing circuit for controlling the voltage Vcom, and further controlling the conduction or cutoff of the fourth switch Q4 through the voltage Vcom.
[0077] Exemplarily, in the normal operating state of the circuit, the voltage Vcom is usually designed to be less than a preset threshold (e.g., 4V). However, when an abnormal situation occurs in the circuit, such as the output voltage being too low or an output short circuit occurring, the voltage Vcom will rise to be greater than the preset threshold (e.g., 4V). Utilizing the above voltage change provides a protection mechanism for the circuit, which can timely change the operating state (conduction or cutoff) of the fourth switch Q4 based on the change of the voltage Vcom to prevent circuit damage or performance degradation.
[0078] It should be noted that the preset threshold of 4V is only an exemplary illustration, and in actual applications, the preset threshold can be reasonably set according to the specific circuit.
[0079] In some embodiments, the third switching transistor is an NMOS transistor, and the fourth switching transistor is an NPN bipolar junction transistor. Among them, the first electrode of the third switching transistor is the drain, the second electrode is the gate, and the third electrode is the source; the first electrode of the fourth switching transistor is the collector, the second electrode is the base, and the third electrode is the emitter.
[0080] In some embodiments, the capacitance value of the fourth capacitor ranges from 100 nF to 150 nF; the resistance value of the tenth resistor ranges from 10 kΩ to 20 kΩ. More specifically, the capacitance value of the fourth capacitor can be 100 nF, 125 nF, or 150 nF, and the resistance value of the tenth resistor can be 10 kΩ, 15 kΩ, or 20 kΩ.
[0081] In some embodiments, Figure 5 The model number of the control chip IC1 shown is UCC28C44. In some embodiments, the power supply pin (VDD pin) of the control chip IC1 is connected to the supply voltage VCC to provide power support for the control chip IC1.
[0082] Next, refer to Figure 5 、 Figure 6 、 Figure 7 and Figure 8 to introduce the working principle of the overcurrent protection circuit in detail.
[0083] Figure 6 、 Figure 7 and Figure 8 respectively show different cases of the variation of the gate-source voltage Vgs of the third switching transistor Q3 with time and the variation of the voltage Vcom with time.
[0084] As Figure 5 shown, the eighth resistor R8 and the third capacitor C3 form the oscillation circuit of the control chip IC1.
[0085] As Figure 5 and Figure 7As shown, during the circuit startup process, when the supply voltage VDD reaches the operating voltage threshold of the chip IC1, the reference voltage Vref will gradually rise from 0V to 5V at time s1. During this process, the reference voltage Vref charges the fourth capacitor C4 through the tenth resistor R10. As the gate-source voltage Vgs of the third switching transistor Q3 rises, when the gate-source voltage Vgs of the third switching transistor Q3 reaches the turn-on voltage Vgs(on) of the third switching transistor Q3 at time s2, the third switching transistor Q3 starts to conduct, connecting the ninth resistor R9 to the oscillation circuit of the control chip IC1. In this way, the switching frequency of the PWM signal can be gradually increased (changing from frequency f1 to frequency f2), thereby dynamically adjusting the switching frequency of the PWM signal.
[0086] By reasonably setting the parameters of the tenth resistor R10 and the fourth capacitor C4, the duration of the frequency change required by the circuit can be accurately controlled (such as the duration of frequency f2 or the duration of frequency f1), and thus the magnitude of the startup current can be effectively controlled. Exemplarily, the duration of frequency f1 is the time interval between time s2 and time s1, and the duration of frequency f2 is the time interval between time s3 and time s2.
[0087] In the normal operating state of the circuit, if an output short circuit occurs, as Figure 6 and Figure 8 shown, at time s3, the voltage Vcom will be rapidly pulled up to a high voltage level above 5V from a lower voltage value. This change triggers the fourth switching transistor Q4 to conduct, and then pulls down the gate voltage Vg of the third switching transistor Q3 to 0V. At this time, the gate-source voltage Vgs of the third switching transistor Q3 becomes negative, and the third switching transistor Q3 turns off. As the third switching transistor Q3 turns off, the ninth resistor R9 is removed from the oscillation circuit, resulting in a decrease in the switching frequency. This decreased switching frequency reduces the proportion of the minimum duty cycle in the entire operating frequency, effectively reducing the maximum excitation current, thereby protecting the circuit from damage caused by the short circuit.
[0088] Compared with Figure 7 , Figure 8 shows the process of the overcurrent protection circuit of the present disclosure embodiment realizing the reduction of the switching frequency from f2 to f1 when an output short circuit occurs. As Figure 6 and Figure 8As shown, the working waveform during output short - circuit shows the change in frequency, where the frequency of f1 is lower than the normal operating frequency f2. On the one hand, it improves the safety of the circuit and also enhances the circuit's response ability to abnormal situations, ensuring that the circuit can quickly respond when facing abnormal situations such as output short - circuit and maintaining the stability and reliability of the system. By adjusting the parameters of the tenth resistor R10 and the fourth capacitor C4, the conduction time of the third switching transistor Q3 can be flexibly controlled, thereby controlling the starting current and response time to meet different application requirements.
[0089] In some embodiments, as Figure 6 shown, the duration of the frequency f2 is the time interval between time s3 and time s2, and the duration of the frequency f1 is the time interval between time s4 and time s3.
[0090] In some embodiments, as Figure 8 shown, in the first time period, the duration of the frequency f1 is the time interval between time s2 and time s1; in the second time period, the duration of the frequency f2 is the time interval between time s3 and time s2; in the third time period, the duration of the frequency f1 is the time interval between time s4 and time s3; in the fourth time period, the duration of the frequency f2 is the time interval between time s5 and time s4.
[0091] It should be noted that Figure 6 and Figure 8 the time s2 in Figure 6 and Figure 8 represents the start time of the frequency f2 or the time when the frequency changes from f1 to f2, Figure 6 and Figure 8 the time s3 in
[0092] both represent the time when the frequency changes from f2 to f1, Figure 8As shown, when the control chip IC1 receives a start signal and the supply voltage VDD reaches the start threshold, the reference voltage Vref will gradually rise from 0V to 5V at time s1. During this process, the gate-source voltage Vgs of the third switching transistor Q3 also rises slowly. Since the output voltage is approaching or has reached the preset value, or due to the effect of the soft-start circuit, the voltage Vcom signal will slowly increase until it reaches a stable state. At this time, the minimum duration (the time interval between time s2 and time s1) of the frequency f1 of the PWM signal is determined by the parameters of the tenth resistor R10 and the fourth capacitor C4. In the start-up phase, due to the large difference between the output voltage and the preset output voltage, the voltage Vcom will rise rapidly. Subsequently, as the output voltage gradually reaches the set value, the voltage Vcom begins to decline and finally stabilizes. In this way, the circuit operates at a lower frequency during start-up, reducing the start-up current and protecting the circuit from overcurrent impact. As the output voltage stabilizes, the PWM frequency gradually increases to the normal operating frequency (such as frequency f2), and at this time the circuit enters the normal operating state. By precisely controlling the parameters of the tenth resistor R10 and the fourth capacitor C4, it can be ensured that the circuit can operate stably and reliably under different loads and input conditions, while reducing energy consumption and improving the overall efficiency.
[0093] In some embodiments, the value range of the frequency f1 is 30kHz - 40kHz, and the value range of the frequency f2 is 60kHz - 70kHz. More specifically, the value range of the frequency f1 is 30kHz, 35kHz or 40kHz, and the value range of the frequency f2 is 60kHz, 65kHz or 70kHz.
[0094] In other embodiments, as Figure 9 shown, if the voltage Vcom reaches a high level before the third switching transistor Q3 is turned on, that is, at time s6, the voltage Vcom reaches a high level, but the gate-source voltage Vgs of the third switching transistor Q3 has not reached the turn-on voltage Vgs(on) of the third switching transistor Q3. At this time, the fourth switching transistor Q4 is turned on, and then the gate voltage Vg of the third switching transistor Q3 is pulled down to 0V. At this time, the gate-source voltage Vgs of the third switching transistor Q3 becomes negative, and the third switching transistor Q3 remains off, and the switching frequency remains f1.
[0095] Until at time s7, as the voltage Vcom gradually decreases, the gate-source voltage Vgs of the third switching transistor Q3 gradually rises. When the gate-source voltage Vgs of the third switching transistor Q3 reaches the turn-on voltage Vgs(on) of the third switching transistor Q3 at time s7, the third switching transistor Q3 begins to conduct, and the ninth resistor R9 is connected to the oscillation circuit of the control chip IC1. In this way, the switching frequency of the PWM signal can be gradually increased (changed from frequency f1 to frequency f2). It can be understood that in Figure 9In the example, even if the voltage Vcom reaches a high level before the third switching transistor Q3 is turned on, the duration of the frequency change required by the circuit can still be controlled (such as the duration of frequency f2 or the duration of frequency f1), thereby effectively controlling the magnitude of the starting current. Exemplarily, Figure 9 In it, the duration of frequency f1 is the time interval between time s7 and time s6, and the duration of frequency f2 is the time interval between time s8 and time s7.
[0096] According to the above two embodiments and Figure 2 and Figure 5 It can be seen that both embodiments include a first switching transistor Q1 ( Figure 5 the fourth switching transistor Q4), a second switching transistor Q2 ( Figure 5 the third switching transistor Q3), a first capacitor C1 ( Figure 5 the fourth capacitor C4), and a first resistor R1 ( Figure 5 the tenth resistor R10). And the first capacitor C1 (or the fourth capacitor C4) is connected across the first pole and the third pole of the first switching transistor Q1 (or the fourth switching transistor Q4). The first pole of the first switching transistor Q1 (or the fourth switching transistor Q4) is connected to the reference voltage terminal pin of the control chip through the first resistor R1 (or the tenth resistor R10). When the measured circuit is overcurrent, the first switching transistor Q1 (or the fourth switching transistor Q4) is turned on, and the voltage of the first capacitor C1 (or the fourth capacitor C4) is clamped to 0V. At this time, the second switching transistor Q2 is turned on (or the third switching transistor Q3 is turned off). After the control chip obtains the overcurrent protection signal, the equivalent frequency or the equivalent duty cycle output is reduced, thereby realizing overcurrent protection for the measured circuit. When the overcurrent of the measured circuit disappears, the first switching transistor Q1 (or the fourth switching transistor Q4) is turned off, and the first capacitor C1 (or the fourth capacitor C4) is charged. When the capacitor voltage satisfies the turn-off voltage of the second switching transistor Q2 (or the capacitor voltage satisfies the turn-on voltage of the third switching transistor Q3), the second switching transistor Q2 is turned off (or the third switching transistor Q3 is turned on), and the frequency or duty cycle output by the control chip returns to the normal level before protection, so that the measured circuit exits overcurrent protection.
[0097] The two states of conduction and turn-off of the switching transistor respectively correspond to inputting an overcurrent protection signal and an overcurrent exit signal to the control chip. In the above embodiments, when the measured circuit is overcurrent, the corresponding second switching transistor Q2 is in the on state or the third switching transistor Q3 is in the off state. In other embodiments, when the measured circuit is overcurrent, it can correspond to the second switching transistor Q2 being in the off state or the third switching transistor Q3 being in the on state. Similarly, those skilled in the art can also interchange the on state and the off state of the first switching transistor Q1 (or the fourth switching transistor Q4), which is not limited here.
[0098] In a third aspect, an embodiment of the present disclosure provides a switching power supply, including: a forward circuit or a flyback circuit, and the overcurrent protection circuit described in any of the foregoing embodiments.
[0099] In some embodiments, as Figure 10 shown, the switching power supply 10 includes: a flyback circuit 11 and the overcurrent protection circuit 12 described in any of the foregoing embodiments. Among them, the structure of the overcurrent protection circuit 12 can refer to the foregoing embodiments and will not be elaborated herein.
[0100] In other embodiments, the switching power supply includes: a forward circuit and the overcurrent protection circuit described in any of the foregoing embodiments.
[0101] It can be understood that since the switching power supply of this embodiment adopts the technical solution of the above overcurrent protection circuit, this switching power supply has all the beneficial effects of the above overcurrent protection circuit.
[0102] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, and this electronic device includes the switching power supply provided in the foregoing embodiment.
[0103] It should be noted here that: the description of the above device embodiments is similar to the description of the above overcurrent protection circuit embodiments, and has similar beneficial effects to the overcurrent protection circuit embodiments. For the technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the embodiments of the overcurrent protection circuit of the present disclosure for understanding.
[0104] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures, or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in some embodiments" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.
[0105] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure.
Claims
1. An overcurrent protection circuit, characterized in that, Including: A control chip, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a first diode; wherein, the first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor; The first pole of the first switching transistor is connected to the third pole of the second switching transistor through the first resistor and then connected to the reference voltage terminal pin of the control chip, and the first pole of the first switching transistor is connected to the second pole of the second switching transistor through the second resistor; The second pole of the first switching transistor is connected to the first end of the third resistor and then connected to the current sampling terminal through the first diode; the third pole of the first switching transistor is connected to the second end of the third resistor, and the third pole of the first switching transistor is grounded through the fifth resistor; The second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is connected to the current detection input terminal pin of the control chip; The first end of the first capacitor is connected to the first pole of the first switching transistor; the second end of the first capacitor is connected to the first end of the fourth resistor; The first pole of the second switching transistor is connected to the second end of the fourth resistor and then grounded through the second capacitor.
2. The overcurrent protection circuit according to claim 1, wherein The cathode of the first diode is connected to the third pole of the first switching transistor and the first end of the third resistor, and the anode of the first diode is connected to the current sampling terminal.
3. The overcurrent protection circuit according to claim 2, wherein, The overcurrent protection circuit further includes a second diode, the cathode of the second diode is connected to the second pole of the first switching transistor, and the anode of the second diode is connected to the cathode of the first diode.
4. The overcurrent protection circuit according to claim 3, wherein The overcurrent protection circuit further includes a sixth resistor and a seventh resistor; The first end of the sixth resistor is connected to the second pole of the first switching transistor, and the second end of the sixth resistor is connected to the cathode of the second diode; The first end of the seventh resistor is connected to the first pole of the second switching transistor, and the second end of the seventh resistor is connected to the second end of the fourth resistor.
5. The overcurrent protection circuit according to claim 1, characterized in that, The first switching transistor is an NPN-type triode, and the second switching transistor is a PNP-type triode; wherein, the first pole is the collector, the second pole is the base, and the third pole is the emitter; Or, The first switching transistor is an NMOS transistor, and the second switching transistor is a PMOS transistor; wherein, the first pole is the drain, the second pole is the gate, and the third pole is the source.
6. The overcurrent protection circuit according to claim 1, wherein The capacitance value of the first capacitor ranges from 10 nF to 30 nF; The resistance value of the first resistor ranges from 10 kΩ to 20 kΩ; The resistance value of the second resistor ranges from 3 kΩ to 5 kΩ.
7. An overcurrent protection circuit, characterized in that, Including: A control chip, a third switching transistor, a fourth switching transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, and a fourth capacitor; wherein, both the third switching transistor and the fourth switching transistor are N-type transistors; The first end of the eighth resistor and the first end of the ninth resistor are connected and then connected to the reference voltage pin of the control chip; The second end of the eighth resistor, the first end of the third capacitor, and the third pole of the third switching transistor are connected and then connected to the oscillation timing pin of the control chip, and the second end of the third capacitor is grounded; The first pole of the third switching transistor is connected to the second end of the ninth resistor; the second pole of the third switching transistor, the first end of the fourth capacitor, and the first pole of the fourth switching transistor are connected and then connected to the reference voltage pin of the control chip through the tenth resistor; The second pole of the fourth switching transistor is connected to the output terminal pin of the internal error amplifier of the control chip; the third pole of the fourth switching transistor is connected to the second end of the fourth capacitor and then grounded; The first end and the second end of the eleventh resistor are respectively connected to the output terminal pin of the internal error amplifier of the control chip and the second pole of the fourth switching transistor; The first end and the second end of the twelfth resistor are respectively connected to the second pole and the third pole of the fourth switching transistor.
8. The overcurrent protection circuit according to claim 7, characterized in that, The third switching transistor is an NMOS transistor, and the fourth switching transistor is an NPN bipolar transistor; Wherein, the first pole of the third switching transistor is the drain, the second pole of the third switching transistor is the gate, and the third pole of the third switching transistor is the source; the first pole of the fourth switching transistor is the collector, the second pole of the fourth switching transistor is the base, and the third pole of the fourth switching transistor is the emitter.
9. The overcurrent protection circuit according to claim 7, wherein The capacitance value of the fourth capacitor ranges from 100 nF to 150 nF; the resistance value of the tenth resistor ranges from 10 kΩ to 20 kΩ.
10. A switching power supply, characterized in that, Comprising: A forward circuit or a flyback circuit and the overcurrent protection circuit according to any one of claims 1 to 6 or the overcurrent protection circuit according to any one of claims 7 to 9.
11. An electronic device, characterized in that, Comprising a switching power supply as claimed in claim 10.