Relaxation oscillator
Through the relaxation oscillator design combining constant current charging and transistor capacitors, the problems of high current consumption and unstable operation in the prior art are solved, and a stable oscillation frequency output and low power consumption design are achieved.
Patent Information
- Application Number
- CN202410207729.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-22
- Filing Date
- 2024-02-26
- Publication Date
- 2025-07-22
AI Technical Summary
The existing relaxation oscillators require high-speed and high-precision comparators when achieving accurate and stable oscillations, resulting in large current consumption, and at the same time, the charging current becomes smaller near the trigger point, resulting in unstable operation.
The relaxation oscillator design adopts a constant current charging, and uses the combination of transistors and capacitors to control the on-off of transistors through flip-flops and output signals of specified frequency, avoiding dependence on high-speed and high-precision comparators.
It realizes a stable operation with fixed voltage gradient near the trigger point, reduces current consumption, simplifies the circuit structure, improves noise resistance and adaptability, and is suitable for miniaturization of capacitors.
Smart Images
Figure CN120357869A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a relaxation oscillator that oscillates by turning a switch on and off. Background Art
[0002] Conventionally, as one of oscillation circuits, a relaxation oscillator that generates an intermittent electrical signal by controlling the on / off timing of a switch is known. For example, a capacitor is charged, and a comparator is used to detect that the charging voltage has reached a specified value to determine the on / off timing of the switch.
[0003] [Background Art Documents]
[0004] [Non-Patent Documents]
[0005] [Non-Patent Document 1] "A 12.77-MHz 31ppm / C On-Chip RC Relaxation Oscillator With Digital Compensation Technique" IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-1:REGULAR PAPERS, VOL.63, NO.11, NOVEMBER 2016 Summary of the Invention
[0006] [Problems to be Solved by the Invention]
[0007] Here, in order to achieve accurate and stable oscillation, it is required that the comparator be high-speed and high-precision, which consumes a large current and requires a large-scale circuit.
[0008] In addition, when the comparator detects that the charging voltage of the capacitor has reached the specified value, the charging current becomes small near the trigger point, so there is a problem that the operation at the trigger point easily becomes unstable.
[0009] [Technical Means for Solving the Problems]
[0010] The relaxation oscillator of the present invention includes: a first transistor through which a constant current flows; a first capacitor charged by the current from the first transistor; a second transistor that takes away the charging charge of the first capacitor; a third transistor through which a constant current flows; a second capacitor charged by the current from the third transistor; a fourth transistor that takes away the stored charge of the second capacitor; and a flip-flop that changes its state from a first state to a second state when the charging voltage of the first capacitor reaches a specified value, and changes from the second state to the first state when the charging voltage of the second capacitor reaches the specified value. In the first state, the second transistor is turned off and the fourth transistor is turned on, and in the second state, the second transistor is turned on and the fourth transistor is turned off; and a signal of a specified frequency is output from the flip-flop.
[0011] [Advantages of the Invention]
[0012] In the relaxation oscillator of the present invention, charging is performed using a constant current, and the voltage gradient is also fixed near the trigger point, enabling stable operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a circuit diagram showing the configuration of the relaxation oscillator of the embodiment.
[0014] Figure 2 It is for explaining Figure 1 the operation of the circuit.
[0015] Figure 3 It is a circuit diagram showing the configuration of Variation 1.
[0016] Figure 4 It is a circuit diagram showing the configuration of Variation 2. DETAILED DESCRIPTION OF THE INVENTION
[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the following embodiments do not limit the present invention, and configurations formed by selectively combining multiple examples are also included in the present invention.
[0018] "Circuit Configuration"
[0019] Figure 1 It is a circuit diagram showing the configuration of the relaxation oscillator of the embodiment. In this circuit, as the transistor, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a gate as the control terminal is used.
[0020] The source of the p-channel transistor M0 is connected to the power supply Vdd, and the drain is connected to the ground GND via the resistor R0. The gate-drain of the transistor M0 is short-circuited, that is, it is diode-connected. Therefore, a fixed current Iref determined by the voltage of the power supply Vdd (Vdd) and the resistance value of the resistor R0 flows through the transistor M0 and the resistor R0.
[0021] The gate of the transistor M0 is connected to the gate of the p-channel transistor M1. The source of the transistor M1 is connected to the power supply Vdd, and the drain is connected to the ground GND via the capacitor C1. The transistor M0 and the transistor M1 form a current mirror. Therefore, by making the two transistors identical, the same current Iref as that in the transistor M0 will flow through the transistor M1, and the capacitor C1 will be charged with this current Iref. In addition, by changing the size ratio of the input-side transistor to the output-side transistor of the current mirror, the current ratio flowing through the two transistors can be changed.
[0022] In addition, the connection point between the drain of the transistor M1 and the capacitor C1 is connected to the drain of the n-channel transistor M2, and the source of the transistor M2 is connected to the ground. Therefore, as the transistor M2 is turned on, the capacitor C1 discharges.
[0023] The gate of the transistor M0 is also connected to the gate of the p-channel transistor M3. The source of the transistor M3 is connected to the power supply Vdd, and the drain is connected to the ground GND via the capacitor C2. The transistor M0 and the transistor M3 form a current mirror. Therefore, the same current Iref as that in the transistor M1 will also flow through the transistor M3, and the capacitor C2 will be charged with this current Iref.
[0024] In addition, the connection point between the drain of the transistor M3 and the capacitor C2 is connected to the drain of the n-channel transistor M4, and the source of the transistor M4 is connected to the ground. Therefore, as the transistor M4 is turned on, the capacitor C2 discharges.
[0025] The drain of the transistor M1 is connected to the gate of the transistor M5. The transistor M5 is a p-channel transistor, the source is connected to the power supply Vdd, and the drain is connected to the ground GND via the resistor R1. The transistor M5 is turned on when the difference between its gate voltage (= the charging voltage Vc1 of the capacitor C1) and the power supply voltage Vdd is a specified value, that is, above the threshold voltage Vgson, and is turned off when it is below the threshold voltage Vgson. In other words, the transistor M5 is turned off when its gate voltage Vc1 becomes above Vdd-Vgson.
[0026] The drain of transistor M3 is connected to the gate of transistor M6. Transistor M6 is a p-channel transistor, with its source connected to the power supply Vdd and its drain connected to the ground GND via resistor R2. Transistor M6 turns off when the difference between its gate voltage (=the charging voltage Vc2 of capacitor C2) and the power supply voltage Vdd becomes equal to or less than the threshold voltage Vgson. That is, transistor M6 turns off when its gate voltage Vc2 becomes equal to or greater than Vdd-Vgson.
[0027] The drain of transistor M5 is connected to the inverting set terminal Sb of an RS (Reset-Set) flip-flop FF. Additionally, the drain of transistor M6 is connected to the inverting reset terminal Rb of flip-flop FF. The output terminal Q of flip-flop FF is connected to the gate of transistor M2, and the inverted output terminal Qb is connected to the gate of transistor M4.
[0028] <Description of the operation>
[0029] Figure 2 is a timing diagram Figure 1 illustrating the operation of the circuit.
[0030] First, assume the state of flip-flop FF is "0". In this case, the output terminal Q is at the L level, transistor M2 is off, the inverted output terminal Qb is at the H level, and transistor M4 is on. Therefore, capacitor C1 is charged with a constant current, and the voltage Vc1 rises slowly. On the other hand, since transistor M4 is on, the voltage Vc2 remains at 0V.
[0031] As the voltage Vc1 of capacitor C1 rises, when the gate voltage of transistor M5 becomes equal to or greater than Vdd-Vgson, transistor M5 turns off. As a result, no current flows through resistor R1, and the voltage at the connection between resistor R1 and transistor M5 becomes 0V. Therefore, the inverting set terminal Sb of flip-flop FF changes from the H level to the L level. Consequently, the state of flip-flop FF becomes "1", the output terminal Q becomes the H level, and the inverted output terminal Qb becomes the L level.
[0032] Thereby, transistor M2 turns on and transistor M4 turns off. Therefore, capacitor C1 discharges, and the voltage Vc1 becomes 0V. On the other hand, since transistor M4 is off, capacitor C2 is charged, and the voltage Vc2 rises slowly. Additionally, since transistor M2 is on, the voltage Vc1 remains at 0V.
[0033] As the voltage Vc2 of capacitor C2 rises, when the gate voltage of transistor M6 becomes equal to or greater than the threshold voltage, transistor M6 turns off. As a result, the inverting reset terminal Rb of flip-flop FF changes from the H level to the L level, the state of flip-flop FF becomes "0", the output terminal Q becomes the L level, and the inverted output terminal Qb becomes the H level.
[0034] Accordingly, transistor M2 is turned off and transistor M4 is turned on. As a result, capacitor C2 discharges and voltage Vc2 becomes 0V. On the other hand, capacitor C1 starts to be charged and voltage Vc1 rises slowly. Since transistor M4 is turned on, voltage Vc2 remains at 0V.
[0035] In this way, by charging capacitors C1 and C2 with a constant current flowing through transistors M1 and M3, the state of flip-flop FF changes to "0" and "1" every predetermined period. Therefore, a signal with a predetermined frequency can be obtained at the output of flip-flop FF.
[0036] If transistors M1 and M3 have the same structure and capacitors C1 and C2 have the same capacitance, the charging of capacitors C1 and C2 can be made equivalent, and the time t1 in the "0" state and the time t2 in the "1" state of flip-flop FF can be made the same.
[0037] In addition, the two states of flip-flop FF are respectively referred to as the first state and the second state. It doesn't matter which of the first state and the second state is which, as long as they respectively refer to two different states of "0" or "1".
[0038] Next, the above operation will be described using formulas. Here, it is assumed that M0:M1:M3 = 1:1:1, C1 = C2 = C, and td (operation delay time) << t1 (half of the output period). Also, the charging current is set to Iref and the threshold voltage of the transistor is set to Vgson.
[0039] First, the charging charge q of the capacitor is the value obtained by multiplying the capacitance C of the capacitor by its voltage V.
[0040] q = C * V
[0041] The charging charge q of the capacitor is the value obtained by multiplying the current I by the charging time t.
[0042] I * t = q = C * V
[0043] Transistors M5 and M6 are transistors when the voltages of capacitors C1 and C2 are equal to or higher than (Vdd - Vgson).
[0044] Therefore,
[0045] Iref * t1 = C1 * (Vdd - Vgson).
[0046] So,
[0047] t1 = C1 * (vdd - vgson) / Iref.
[0048] In addition, the charging current Iref is on the downstream side of the transistor M0 and is the current flowing through the resistor R0. The voltage drop in the diode-connected transistor M0 is Vgson. Therefore,
[0049] Iref = (Vdd - Vgson) / R0.
[0050] Therefore,
[0051] t1 = C1*R0 = C*R0.
[0052] The same applies to t2.
[0053] t2 = C2*R0 = C*R0 = t1.
[0054] It can be seen therefrom that the clock timing is not related to the power supply and the duty ratio is 50%.
[0055] In the relaxation oscillator of this embodiment, a constant current is used for charging. Therefore, at the trigger points where the transistors M5 and M6 are turned off, the voltage gradient is fixed and stable operation can be obtained. For example, in a CR (Capacitor-Resistor) type relaxation oscillator, the charging current becomes small near the trigger point, so there are problems in the operation at the trigger point. However, such problems do not exist in the relaxation oscillator of the present invention.
[0056] In addition, in this embodiment, it is only necessary to control the on / off of the transistors M5 and M6 using the charging voltage of the capacitor. The current consumption can be relatively small, and high-speed operation can be achieved with a simple configuration.
[0057] In addition, switching can be performed using the charging voltage of the capacitor close to the power supply voltage. Therefore, the noise immunity is strong and it is suitable for miniaturization of the capacitor.
[0058] The charging current of the capacitor is the current flowing through the transistors M1 and M3 and is proportional to the comparison voltage (Vdd - Vgson). The voltage at which the charging stops is also (Vdd - Vgson). Therefore, the time constant of the circuit operation is not related to the power supply voltage.
[0059] "Variation 1"
[0060] Figure 3 is a circuit diagram showing the configuration of Variation 1. Compared with the Figure 1 configuration, the resistors R1 and R2 that are the loads of the transistors M5 and M6 are replaced with constant current sources.
[0061] That is, a transistor M8 with a p-channel is provided. The gate of the transistor M8 is connected to the transistor M0, and the source is connected to the power supply Vdd; a current corresponding to the current Iref flowing through the transistor M0 flows through it. The drain of the transistor M8 is connected to the drain of an n-channel transistor M9. The gate-drain of the transistor M9 is short-circuited, that is, diode-connected, and the source is connected to the ground wire.
[0062] The gate of the transistor M9 is connected to the gate of an n-channel transistor M10, and the drain of the transistor M10 is connected to the source of the transistor M5. The transistor M9 and the transistor M10 form a current mirror. When the transistor M5 is turned on, a sufficient current flows through it. However, when the transistor M5 is turned on, the current flowing through the transistor M5 will be the same as that of the transistor M10, and the drain of the transistor M5, that is, the inverting set terminal Sb of the flip-flop FF, becomes the H level. On the other hand, when the transistor M5 is turned off, in order to make the transistor M10 conduct current, the drain of the transistor M5, that is, the inverting set terminal Sb of the flip-flop FF, becomes the L level.
[0063] In addition, the transistor M11 has the opposite timing compared to the transistor M10, but the operation is the same, and the inverting reset terminal of the flip-flop FF becomes the H level when the transistor M6 is turned on and becomes the L level when the transistor M6 is turned off. In addition, Figure 3 The signal level when the flip-flop FF is in the "0" state is shown.
[0064] In this way, the same operation as that of the Figure 1 embodiment can also be achieved in this modification 1. In addition, since transistors are used instead of the resistors R1 and R2, a higher-precision oscillator can be obtained.
[0065] "Modification 2"
[0066] Figure 4 is a circuit diagram showing the configuration of Modification 2. In Modification 2, compared with the Figure 1 configuration, a selector composed of transistors M12 and M13 is added. Thus, for the charging current charged into the capacitors C1 and C2, the transistor M3 is omitted, and the capacitors C1 and C2 are alternately charged with the current from one current source, that is, the transistor M1. Thereby, power consumption can be reduced.
[0067] That is, the drain of the transistor M1 is connected to the sources of p-channel transistors M12 and M13. The drain of the transistor M12 is connected to the capacitor C1, and the drain of the transistor M13 is connected to the capacitor C2. Moreover, the gate of the transistor M12 is connected to the output terminal Q of the flip-flop FF, and the gate of the transistor M13 is connected to the inverting output terminal Qb of the flip-flop FF.
[0068] Therefore, when transistor M2 is turned off, transistor M12 is turned on and capacitor C1 is charged. When transistor M4 is turned off, transistor M13 is turned on and capacitor C2 is charged.
[0069] "Effect of the Embodiment"
[0070] According to this embodiment, an oscillator with a relatively simple circuit, simple installation, and few components can be realized. By making the charging voltages of capacitors C1 and C2 close to the voltage of power supply Vdd, the power supply voltage can be fully utilized for oscillation. By turning off transistors M5 and M6, phase noise can be reduced.
[0071] The gates and sources of transistors M5 and M6 act as the negative input and positive input of a comparator with a specified offset voltage. Therefore, transistors M5 and M6 replace the use of a conventional dual-input comparator with a voltage reference and act as a comparator.
[0072] In addition, the offset is the same as the Vgs of transistor M0 and cancels each other out. Therefore, high-precision oscillation can be achieved.
[0073] Such a simple and sufficiently accurate high-speed comparator is suitable for high-frequency oscillation.
[0074] In addition, by tuning resistor R0, the oscillation frequency can be easily adjusted.
[0075] "Others"
[0076] Capacitor C1 is referred to as the first capacitor, capacitor C2 is referred to as the second capacitor, and transistors M1 to M11 are respectively referred to as the first to eleventh transistors.
[0077] [Description of Reference Signs]
[0078] M0 to M11: Transistors
[0079] C1 to C2: Capacitors
[0080] FF: Flip-flop.
Claims
1. A relaxation oscillator, comprising: A first transistor through which a constant current flows; A first capacitor charged by the current from the first transistor; A second transistor that takes away the charging charge of the first capacitor; A third transistor through which a constant current flows; A second capacitor charged by the current from the third transistor; A fourth transistor that takes away the stored charge of the second capacitor; And A flip-flop that changes its state from a first state to a second state when the charging voltage of the first capacitor reaches a specified value, and changes from the second state to the first state when the charging voltage of the second capacitor reaches a specified value. In the first state, the second transistor is turned off and the fourth transistor is turned on. In the second state, the second transistor is turned on and the fourth transistor is turned off; and A signal of a specified frequency is output from the flip-flop.
2. The relaxation oscillator according to claim 1, further comprising: A fifth transistor that turns on and off with its control terminal receiving the charging voltage of the first capacitor; and A sixth transistor that turns on and off with its control terminal receiving the charging voltage of the second capacitor; and As the fifth transistor and the sixth transistor turn on and off, the state of the flip-flop changes.
3. The relaxation oscillator according to claim 2, Comprises a first resistor that is connected in series with the fifth transistor, and as the fifth transistor turns on and off, the voltage at the connection point between it and the fifth transistor changes; As the voltage at the connection point between the first resistor and the fifth transistor changes, the state of the flip-flop changes, and Comprises a second resistor that is connected in series with the sixth transistor, and as the sixth transistor turns on and off, the voltage at the connection point between it and the sixth transistor changes; As the voltage at the connection point between the second resistor and the sixth transistor changes, the state of the flip-flop changes.
4. The relaxation oscillator according to claim 2, Comprises a tenth transistor through which a constant current flows, which is connected in series with the fifth transistor, and as the fifth transistor turns on and off, the voltage at the connection point between it and the fifth transistor changes; As the voltage at the connection point between the tenth transistor and the fifth transistor changes, the state of the flip-flop changes, and Comprises an eleventh transistor through which a constant current flows, which is connected in series with the sixth transistor, and as the sixth transistor turns on and off, the voltage at the connection point between it and the sixth transistor changes; As the voltage at the connection point between the eleventh transistor and the sixth transistor changes, the state of the flip-flop changes.
5. The relaxation oscillator according to claim 2, wherein The first transistor and the second transistor alternately conduct the constant current from one constant current source in a switched manner.
6. The relaxation oscillator according to claim 1, comprising: A zero-th transistor whose diode-connected control terminal is connected to the control terminals of the first transistor and the third transistor; and A zero-th resistor connected in series with the zero-th transistor; and The magnitudes of the constant currents flowing through the first transistor and the second transistor are adjusted by the resistance value of the 0th resistor.