Non-polar wide voltage range sampling circuit

Abstract

The invention relates to a non-polar wide-voltage-range sampling circuit, which comprises a polarity switching circuit (NMOS (N-channel Metal Oxide Semiconductor) transistors Q1 and Q2 are respectively connected with detection voltages T1 and T2, and source electrodes are in common ground); the base electrode of a PNP triode Q3 is connected with the output end of the voltage comparator U1, the collector electrode of the PNP triode Q3 is connected with the grid electrode of Q1 through R8, and the output end of U1 is connected with the grid electrode of Q2 through R10); the voltage comparison circuit (U1, R1-R4 voltage dividers, T1 and T2 are connected with the in-phase end and the anti-phase end of U1 after voltage division); and an output switching circuit. When T1 is positive and T2 is negative, Q2 is conducted, otherwise Q1 is conducted; the U1 outputs high and low levels to control the states of the Q3, the Q1 and the Q2; the U2 of the output switching circuit switches CH1 or CH0 to be connected with COM according to SEL. Resistance values of R1 and R3 and R2 and R4 are equal, and the resistor of the voltage divider can be adjusted to adapt to different voltages. According to the invention, non-polar wide voltage sampling is realized, and sampling accuracy and circuit stability are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuit design, and particularly relates to a wide-range voltage sampling circuit for the analog-to-digital conversion (ADC) port of a single-chip microcomputer, which is particularly suitable for non-polar detection of positive and negative voltages and wide-voltage signal conditioning. Background Art

[0002] In modern electronic systems, the analog-to-digital conversion (ADC) port of a single-chip microcomputer can only sample positive voltage signals. When negative voltage sampling is required, additional circuit processing is usually needed. However, there are many defects in the existing technologies. On the one hand, conventional circuits cannot achieve simultaneous sampling of positive and negative voltages, especially for a relatively high range of positive and negative voltages, and it is difficult to achieve accurate and reliable sampling. On the other hand, when the voltage polarity of a unipolar sampling circuit is reversed, the entire system may be damaged, posing a safety hazard. For example, in application scenarios such as power monitoring systems and electrical equipment fault detection, it is impossible to accurately and safely sample and monitor positive and negative voltages in a wide voltage range, which limits the functions and application scope of the system.

[0003] Therefore, there is an urgent need for a non-polar wide-voltage range sampling circuit to solve the problems in the existing technologies that positive and negative voltages cannot be sampled simultaneously and the system may be damaged when the voltage polarity is reversed. Summary of the Invention

[0004] The object of the present invention is to provide a non-polar wide-voltage range sampling circuit for the problems existing in the prior art, and realize non-polar sampling in a wide voltage range by the coordinated operation of circuits such as MOSFET polarity switching, PNP transistor inverting drive, voltage comparison, and analog switch output switching.

[0005] To achieve the above application object, the present invention adopts the following technical solutions: The non-polar wide-voltage range sampling circuit includes: Polarity switching circuit: including NMOS transistor Q1 and NMOS transistor Q2, the drain of NMOS transistor Q1 is connected to the detection voltage T1, the drain of NMOS transistor Q2 is connected to the detection voltage T2, and the sources of NMOS transistor Q1 and NMOS transistor Q2 are grounded together; Inverting drive circuit: including PNP transistor Q3, the base of PNP transistor Q3 is connected to the output end of voltage comparator U1, the collector of PNP transistor Q3 is connected to the gate of NMOS transistor Q1 through resistor R8, and the output end of voltage comparator U1 is also connected to the gate of NMOS transistor Q2 through resistor R10; Voltage comparison circuit: including voltage comparator U1 and a voltage divider composed of resistors R1-R4, the voltages of the detection voltage T1 terminal are divided by resistors R1 and R2 and then connected to the non-inverting terminal of voltage comparator U1, and the voltages of the detection voltage T2 terminal are divided by resistors R3 and R4 and then connected to the inverting terminal of voltage comparator U1; Output switching circuit: It includes a single-pole double-throw analog switch U2. The input terminal CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage-dividing point A of resistors R1 and R2, the input terminal CH0 is connected to the voltage-dividing point B of resistors R3 and R4, and the common port COM outputs to the MCU for sampling. The output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2.

[0006] Further, when the detected voltage T1 is positive and the detected voltage T2 is negative, the gate of the NMOS transistor Q2 is at a high level, the NMOS transistor Q2 conducts, and the detected voltage T2 terminal conducts to the ground; when the detected voltage T1 is negative and the detected voltage T2 is positive, the gate of the NMOS transistor Q1 is at a high level, the NMOS transistor Q1 conducts, and the detected voltage T1 terminal conducts to the ground.

[0007] Further, when the voltage comparator U1 outputs a high level, the PNP transistor Q3 is cut off, the NMOS transistor Q1 is cut off, and the NMOS transistor Q2 conducts; when the voltage comparator U1 outputs a low level, the PNP transistor Q3 conducts, the NMOS transistor Q1 conducts, and the NMOS transistor Q2 is cut off.

[0008] Further, when the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 is at a high level, the input terminal CH1 is connected to the common port COM; when the control terminal SEL is at a low level, the input terminal CH0 is connected to the common port COM.

[0009] Further, the resistance value of resistor R1 is equal to that of resistor R3, and the resistance value of resistor R2 is equal to that of resistor R4.

[0010] Further, by adjusting the resistance value ratio of the resistors in the voltage divider, different input voltage ranges can be adapted.

[0011] Further, resistors R9 and R8 are provided between the NMOS transistor Q1 and the NMOS transistor Q2.

[0012] Further, the base of the PNP transistor Q3 is also connected to a resistor R7, and the other end of the resistor R7 is grounded.

[0013] Further, the power supply terminals of the voltage comparator U1 are connected to +5V and ground respectively.

[0014] Further, the output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 through a resistor R5.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. It realizes non-polar sampling in a wide voltage range (-80V to +80V), solves the problem of positive and negative voltage polarity conversion of the single-chip microcomputer ADC sampling port, breaks through the limitations of the prior art, and greatly expands the sampling voltage range.

[0016] 2. The circuit structure is simple and consists only of conventional devices such as MOSFETs, triodes, voltage comparators, and analog switches. The number of devices is small, reducing the circuit complexity and fault points and improving the reliability.

[0017] 3. It has low cost and is easy to implement, facilitating its popularization and application in various electronic systems requiring voltage sampling, and improving the overall performance and safety of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the circuit diagram of the present invention; Figure 2 is Figure 1 a schematic diagram of the conduction of the polarity switching circuit Q2 in Figure 3 is Figure 1 a schematic diagram of the conduction of the polarity switching circuit Q1 in Figure 4 is Figure 1 an enlarged view of the inverting drive circuit in Figure 5 is Figure 1 an enlarged view of the voltage comparison circuit in Figure 6 is Figure 1 an enlarged view of the output switching circuit in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0020] Those skilled in the art should understand that in the disclosure of the present invention, the orientation or positional relationships indicated by the terms "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the present invention.

[0021] As Figure 1 shown, this non-polar wide voltage range sampling circuit includes a MOSFET polarity switching circuit 1, a PNP triode inverting drive circuit 2, a voltage comparison circuit 3, and an output switching circuit 4.

[0022] As Figure 2and Figure 3 As shown in Figure 3 , in the MOSFET polarity switching circuit 1, the drain of NMOS transistor Q1 is connected to the detection voltage T1, the drain of NMOS transistor Q2 is connected to the detection voltage T2, the sources of NMOS transistors Q1 and Q2 are grounded together, and a resistor R9 and a resistor R8 are provided between NMOS transistors Q1 and Q2. Here, both NMOS transistors Q1 and Q2 are N-channel MOSFETs.

[0023] When the detection voltage T1 is positive and the detection voltage T2 is negative, the gate of NMOS transistor Q2 is at a high level, NMOS transistor Q2 conducts, and the detection voltage T2 terminal conducts to the ground; when the detection voltage T1 is negative and the detection voltage T2 is positive, the gate of NMOS transistor Q1 is at a high level, NMOS transistor Q1 conducts, and the detection voltage T1 terminal conducts to the ground.

[0024] As Figure 4 shown in Figure 4 , in the PNP transistor inverting drive circuit 2, it includes a PNP transistor Q3. The base of PNP transistor Q3 is connected to the output terminal of voltage comparator U1. The collector of PNP transistor Q3 is connected to the gate of NMOS transistor Q1 through resistor R8. The output terminal of voltage comparator U1 is also connected to the gate of NMOS transistor Q2 through resistor R10. A resistor R7 is also connected to the base of PNP transistor Q3, and the other end of this resistor R7 is grounded. Among them, voltage comparator U1 (model TL331) is paired with resistors R1 (150.0KΩ), R2 (10.0KΩ), R3 (150.0KΩ), and R4 (10.0KΩ) to form a voltage dividing network.

[0025] When the voltage comparator U1 outputs a high level, PNP transistor Q3 is cut off, NMOS transistor Q1 is cut off, and NMOS transistor Q2 conducts; when the voltage comparator U1 outputs a low level, PNP transistor Q3 conducts, NMOS transistor Q1 conducts, and NMOS transistor Q2 is cut off. In this way, the inverting drive of Q1 and Q2 can be realized through PNP transistor Q3.

[0026] As Figure 5 shown in Figure 5 , in the voltage comparison circuit 3, it includes a voltage comparator U1 and a voltage divider composed of resistors R1 - R4. After the voltages of the detection voltage T1 terminal are divided by resistors R1 and R2, they are connected to the non-inverting terminal of voltage comparator U1. After the voltages of the detection voltage T2 terminal are divided by resistors R3 and R4, they are connected to the inverting terminal of voltage comparator U1. The power supply terminals of voltage comparator U1 are respectively connected to +5V and grounded.

[0027] The resistance values of resistor R1 and resistor R3 are equal, and the resistance values of resistor R2 and resistor R4 are equal. The voltage division ratio is selected according to the measurement voltage range ( Figure 5The resistance voltage division ratio in it can sample voltages from -80V to +80V. The voltages at point A or point B after voltage division are the sampled voltages. When voltage A > B, the voltage comparator outputs a high level; when A < B, the voltage comparator outputs a low level. The output terminal of voltage comparator U1 is connected to the gate of NMOS transistor Q2 through resistor R10 to drive NMOS transistor Q2, and is connected to the base of PNP transistor Q3 through resistor R6. After being inverted by PNP transistor Q3, it drives NMOS transistor Q1, and is connected to the control terminal SEL of single-pole double-throw analog switch U2 through resistor R5.

[0028] As Figure 6 Shown in the figure, the output switching circuit 4 includes a single-pole double-throw analog switch U2 (model CH443K). The input terminal CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage division point A of resistors R1 and R2, and the input terminal CH0 is connected to the voltage division point B of resistors R3 and R4. The common port COM outputs to the MCU for sampling. The output terminal of voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 through resistor R5.

[0029] The output signal of voltage comparator U1 controls the control terminal SEL pin of the double-throw analog switch U2. When the voltage comparator U1 outputs a high level, SEL is driven, and the single-pole double-throw analog switch U2 selects to connect CH1 and COM, and the voltage at point A is output to the ADC. When the voltage comparator U1 outputs a low level, the single-pole double-throw analog switch U2 selects to connect CH0 and COM, and the voltage at point B is output to the ADC. In this way, regardless of the polarity of the input voltage, the voltage signal output to the ADC port of the MCU is always a positive voltage signal, realizing non-polar sampling and ensuring that the single-chip microcomputer can accurately collect voltage signals in a wide range.

[0030] The parts not detailed in the present invention are prior art, so the present invention does not elaborate on them.

[0031] It can be understood that the term "one" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, while in other embodiments, the number of this element can be multiple. The term "one" cannot be understood as a limitation on the number.

[0032] Although this article uses more professional terms, the possibility of using other terms is not excluded. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

[0033] The present invention is not limited to the above-mentioned best implementation manner. Anyone can obtain various other forms of products under the inspiration of the present invention. However, no matter what changes are made in its shape or structure, as long as it has a technical solution identical or similar to that of the present invention, it falls within the protection scope of the present invention.

Claims

1. Non-polar wide voltage range sampling circuit, characterized in that, Comprising: Polarity switching circuit: including NMOS transistor Q1 and NMOS transistor Q2. The drain of the NMOS transistor Q1 is connected to the detection voltage T1, the drain of the NMOS transistor Q2 is connected to the detection voltage T2, and the sources of the NMOS transistor Q1 and the NMOS transistor Q2 are grounded together. Inverting drive circuit: including PNP transistor Q3. The base of the PNP transistor Q3 is connected to the output terminal of the voltage comparator U1. The collector of the PNP transistor Q3 is connected to the gate of the NMOS transistor Q1 through a resistor R8. The output terminal of the voltage comparator U1 is also connected to the gate of the NMOS transistor Q2 through a resistor R10. Voltage comparison circuit: including a voltage comparator U1 and a voltage divider composed of resistors R1 - R4. The voltages of the detection voltage T1 terminal are divided by the resistors R1 and R2 and then connected to the non-inverting input terminal of the voltage comparator U1. The voltages of the detection voltage T2 terminal are divided by the resistors R3 and R4 and then connected to the inverting input terminal of the voltage comparator U1. Output switching circuit: including a single-pole double-throw analog switch U2. The input terminal CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage division point A of the resistors R1 and R2, the input terminal CH0 is connected to the voltage division point B of the resistors R3 and R4, and the common port COM outputs to the MCU for sampling. The output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2.

2. The non-polar wide voltage range sampling circuit according to claim 1, wherein When the detection voltage T1 is positive and the detection voltage T2 is negative, the gate of the NMOS transistor Q2 is at a high level, the NMOS transistor Q2 conducts, and the detection voltage T2 terminal conducts to the ground. When the detection voltage T1 is negative and the detection voltage T2 is positive, the gate of the NMOS transistor Q1 is at a high level, the NMOS transistor Q1 conducts, and the detection voltage T1 terminal conducts to the ground.

3. The non-polar wide voltage range sampling circuit according to claim 1, characterized in that, When the voltage comparator U1 outputs a high level, the PNP transistor Q3 is cut off, the NMOS transistor Q1 is cut off, and the NMOS transistor Q2 conducts. When the voltage comparator U1 outputs a low level, the PNP transistor Q3 conducts, the NMOS transistor Q1 conducts, and the NMOS transistor Q2 is cut off.

4. The non-polar wide voltage range sampling circuit according to claim 1, wherein When the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 is at a high level, the input terminal CH1 is connected to the common port COM. When the control terminal SEL is at a low level, the input terminal CH0 is connected to the common port COM.

5. The non-polar wide voltage range sampling circuit according to claim 1, characterized in that The resistance values of the resistor R1 and the resistor R3 are equal, and the resistance values of the resistor R2 and the resistor R4 are equal.

6. The non-polar wide voltage range sampling circuit according to claim 1, wherein By adjusting the resistance value ratio of the resistors in the voltage divider, different input voltage ranges can be adapted.

7. The non-polar wide voltage range sampling circuit according to claim 1, wherein A resistor R9 and a resistor R8 are provided between the NMOS transistor Q1 and the NMOS transistor Q2.

8. The non-polar wide voltage range sampling circuit according to any one of claims 1-7, characterized in that A resistor R7 is also connected to the base of the PNP transistor Q3, and the other end of the resistor R7 is grounded.

9. The non-polar wide voltage range sampling circuit according to any one of claims 1-7, characterized in that, The power supply terminals of the voltage comparator U1 are respectively connected to +5V and the ground.

10. The non-polar wide voltage range sampling circuit according to any one of claims 1-7, characterized in that, The output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 through a resistor R5.

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