Successive approximation type analog-to-digital converter with stable PVT

Abstract

The invention discloses a successive approximation type analog-to-digital converter with stable PVT, and belongs to the technical field of analog-to-digital converter design, the analog-to-digital converter is composed of a switched capacitor DAC module, a comparator, a successive approximation logic circuit and a delay adjusting circuit; wherein the switched capacitor DAC module IDAC receives differential input signals Vip and Vin and reference levels Vrefp and Vrefn; capacitor top plate output voltages Vcp and Vcn of the switched capacitor DAC module are connected to the positive input end and the negative input end of the comparator ICMP respectively. According to the method, the fastest and slowest conditions of PVT (process angle, power supply voltage and temperature) are compatible by automatically detecting residual conversion time and adjusting time delay, and the problem that the slowest condition is just used for the whole conversion time in order to be compatible with the fastest and slowest conditions in the traditional design can be solved. Extra power consumption is integrally added to the drive of the switched capacitor DAC and a reference level generation circuit, and the problem of establishment time of the switched capacitor DAC under the fastest decoupling compensation condition is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converter design, and particularly relates to a successive approximation analog-to-digital converter with PVT stability. Background Art

[0002] With the process evolution, successive approximation analog-to-digital converters have been increasingly important in high-speed scenarios. Their successive approximation timing uses asynchronous logic timing to improve the conversion speed and avoid high-speed clocks. However, since the delay of asynchronous timing is realized through logic circuits, there are significant timing differences under PVT (process corner, power supply voltage, temperature). The difference in conversion time between the slowest and fastest cases can be up to 1 times, which easily leads to insufficient total conversion time in the slowest case and overly wide logic delay in the fastest case, resulting in insufficient setup time for the switched-capacitor DAC (digital-to-analog converter) in the analog-to-digital converter. Summary of the Invention

[0003] The purpose of the present invention is to provide a successive approximation analog-to-digital converter with PVT stability. By automatically detecting the remaining conversion time and adjusting the delay, it can accommodate both the fastest and slowest cases. It can solve the problem in traditional designs that in order to accommodate the fastest and slowest cases, the slowest case just uses up the entire conversion time, adding extra power consumption and decoupling capacitors to the drive of the switched-capacitor DAC and the reference level generation circuit to compensate for the setup time of the switched-capacitor DAC in the fastest case, as well as the problem of significant increase in the area and power consumption of the entire analog-to-digital converter.

[0004] To achieve the above purpose, the present invention provides the following technical solution: A successive approximation analog-to-digital converter with PVT stability, which is composed of a switched-capacitor DAC module, a comparator, a successive approximation logic circuit, and a delay adjustment circuit;

[0005] Among them, the switched-capacitor DAC module IDAC receives differential input signals Vip, Vin and reference levels Vrefp, Vrefn; the capacitor top plate output voltages Vcp, Vcn of the switched-capacitor DAC module are respectively connected to the positive and negative input terminals of the comparator ICMP; the positive and negative output signals Q, QB of the comparator are used as input signals and connected to the successive approximation logic circuit; the delay circuit module of the successive approximation logic circuit generates the input clock CMP_CK of the comparator and inputs it to the input terminal of the comparator, and the successive approximation logic circuit gradually outputs the control signal Dac_ctl of the switched-capacitor array according to the result of the comparator. <n-1:0>; Meanwhile, the successive approximation logic circuit outputs a reset signal rst_syn and a delayed conversion completion signal finish_dly to the delay adjustment circuit; the delay adjustment circuit outputs an adjusted comparator clock delay control signal dly_out<2:0> to the delay circuit of the successive approximation logic circuit to control the delay gear of the comparison clock; the successive approximation logic circuit outputs the final analog-to-digital conversion digital signal Dout <n-1:0>。

[0006] Preferably, the delay adjustment circuit compares the delayed conversion completion signal finish_dly output by the successive approximation logic circuit with the input clock ckdff.

[0007] Among them, the input clock ckdff has the same frequency and phase as the sampling clock of the entire analog-to-digital converter. During the sampling phase, the input clock ckdff is at a high level, and during the conversion phase, the input clock ckdff is at a low level.

[0008] When there is enough redundant time after the successive approximation conversion is completed, the delay adjustment circuit will increase the gear of the input delay control signal dly_out<2:0>, utilize this redundant time, so as to relieve the establishment pressure of the switched capacitor DAC in the fast PVT situation, thereby reducing the driving pressure of the switched capacitor DAC and the power consumption of the reference level generation circuit.

[0009] Preferably, the successive approximation logic circuit includes a delay circuit IDLY, a NAND gate I1, successive approximation units I5, I6, I7, and I8, a delay unit I9, an AND gate I10, a D flip-flop I3, and an inverter I4.

[0010] Among them, the positive and negative output signals of the comparator are Q and QB, which are connected to the two input terminals of the NAND gate I1 in the successive approximation logic circuit as input signals; the output signal of the NAND gate I1 is a valid signal, and the output terminal of the NAND gate I1 is respectively connected to the input terminal cki of the delay circuit IDLY and the CK terminals of the successive approximation units I5, I6, I7, and I8; the positive and negative output signals Q and QB of the comparator are also simultaneously connected to the positive data input D terminals and the negative data input DB terminals of the successive approximation units I5, I6, I7, and I8; the enable input terminal EN of the successive approximation unit I5 is connected to the input clock ckdff through the inverter I2; the next-level enable output terminal EN_N of the successive approximation unit I5 is connected to the EN terminal of the successive approximation unit I6; the output terminal EN_N of the successive approximation unit I6 is connected to the EN terminal of the successive approximation unit I7; the output terminal EN_N of the successive approximation unit I7 is connected to the line EN<3> to connect to the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the (n - 1)th successive logic unit; the output terminal EN_N of the successive approximation unit I8 is connected to the input A terminal of the delay unit I9, and after being delayed by the delay unit I9, it is input to one of the input terminals of the AND gate I10 through its O terminal, and the output terminal EN_N of the successive approximation unit I8 is directly connected to the other input terminal of the AND gate I10; the output terminal line name of the AND gate I10 is finish_dly; the data input Q terminal of the D flip-flop I3 is connected to the logic high level "1", the CK terminal is connected to the input clock ckdff, the reset input R terminal is connected to the input reset signal sar_rst, and the output D terminal obtains the synchronous de-reset signal rst_syn through the inverter I4.

[0011] The RST terminals of the successive approximation units I5, I6, I7, and I8 are all connected to rst_syn; the output CTL terminals of the successive approximation units I5, I6, I7, and I8 respectively output n-bit control signals Dac_ctl <n-1>To Dac_ctl<0> to the IDAC, used to control the capacitor lower plate switches of the switched capacitor DAC; the output Q terminals of the successive approximation cells I5, I6, I7, and I8 are data output terminals, respectively outputting the output data D of n out <n-1:0>As the output data of the entire analog-to-digital converter; the input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the enable clock line CMP_CK of the comparator and connected to the ck terminal of the comparator ICMP.

[0012] Preferably, the delay adjustment circuit includes D flip-flops I11, I13, I15, I17, I20, I21, I25, I27, I29, I31 and I33, inverters I12, I14, I16, I18, I26, I28, I30, I32 and I34, nor gates I19, I39, nand gates I37, I38, an and gate I40, or gates I36, I41, I42, I43, adders I22, I23, I24 and a delay unit I35;

[0013] Among them, the finish_dly line is connected to the CK terminal of the D flip-flop I11, and the output D terminal of the D flip-flop I11 is connected to the input Q terminal of I11 and the CK terminal of the D flip-flop I13 through the inverter I12; the output D terminal of the D flip-flop I13 is connected to the input Q terminal of I13 and the CK terminal of the D flip-flop I15 through the inverter I14; the output D terminal of the D flip-flop I15 is connected to the input Q terminal of the D flip-flop I15, the CK terminal of the D flip-flop I17 and one input terminal of the nor gate I19 through the inverter I16; the output D terminal of the D flip-flop I17 is connected to the input Q terminal of the D flip-flop I17 and the other input terminal of the nor gate I19 through the inverter I18.

[0014] Preferably, the reset terminals R of the D flip-flops I11, I13, I15, and I17 are all connected to cnt_rst; the input clock ckdff line is connected to the CK terminal of the D flip-flop I25, the D terminal of the D flip-flop I25 is connected to the signal ckcnt0, which is connected to the Q terminal of the D flip-flop I25 and the CK terminal of the D flip-flop I27 through the inverter I26; the output D terminal of the D flip-flop I27 is connected to the signal ckcnt1, which is connected to the Q terminal of the D flip-flop I27 and the CK terminal of the D flip-flop I29 through the inverter I28; the output D terminal of the D flip-flop I29 is connected to the signal ckcnt2, which is connected to the Q terminal of the D flip-flop I29 and the CK terminal of the D flip-flop I31 through the inverter I30; the output D terminal of the D flip-flop I31 is connected to the signal ckcnt3, which is connected to the Q terminal of the D flip-flop I31 and the CK terminal of the D flip-flop I33 through the inverter I32; the output D terminal of the D flip-flop I33 is connected to the signal ckcnt4, which is connected to the Q terminal of the D flip-flop I33 through the inverter I34; the signals ckcnt0 and ckcnt1 are respectively connected to the two input terminals of the NAND gate I37; the signals ckcnt2 and ckcnt3 are respectively connected to the two input terminals of the NAND gate I38; the output terminals of the NAND gates I37 and I38 are respectively connected to the two input terminals of the NOR gate I39; the output terminal of the NOR gate I39 and the input clock ckdff are respectively connected to the two input terminals of the AND gate I40; the reset terminals of the D flip-flops I25, I27, I29, I31, and I33 are all connected to the cnt_rst signal; the signal ckcnt4 is connected to the input terminal A of the delay unit I35, and the output terminal O of the logic unit I35 is connected to one of the input terminals of the OR gate I36. The other input terminal of the OR gate I36 is connected to rst_syn, and the output terminal of the OR gate I36 is connected to the signal cnt_rst.

[0015] Preferably, the output of the NOR gate I19 is connected to the Q terminal of the D flip-flop I20; the output terminal of the AND gate I40 is connected to the CK terminal of the D flip-flop I20; the output terminal D of the D flip-flop I20 is connected to the Q terminal of the D flip-flop I21; the D terminal of the D flip-flop I21 is connected to the A terminal of the adder I22, and the CK terminal of the D flip-flop I21 is connected to the input signal ck terminal; the reset terminals R of the D flip-flops I20 and I21 are both connected to rst_syn; the B terminals of the adders I22, I23, and I24 respectively input the original delay control signal dly_in<2:0>; the CO terminal of the adder I22 is connected to the A terminal of the adder I23, and the CO terminal of the adder I23 is connected to the CO terminal of the adder I24; the S terminals of the adders I22, I23, and I24 are respectively connected to the input terminals of the OR gates I41, I42, and I43; the CO terminal of the adder I24 is connected to the other input terminals of the OR gates I41, I42, and I43; the output terminals of the OR gates I41, I42, and I43 respectively output the delay control signals dly_out<2:0>.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] In the present invention, the delay adjustment circuit that works in the background automatically detects the redundant time after each successive approximation conversion is completed. When the redundant time is large enough, the delay adjustment circuit will count. When the redundant times at the end of most conversions are sufficient, the delay adjustment circuit will increase the gear of the delay control signal, so that the redundant time after the conversion is completed is reduced. By this method, the establishment pressure of the switched-capacitor DAC in the fast PVT case is alleviated, thereby reducing the driving pressure of the switched-capacitor DAC and the power consumption of the reference level generation circuit. Description of the Drawings

[0018] Figure 1 It is a block diagram of a traditional comparator amplifier.

[0019] Figure 2 It is a block diagram of the successive approximation analog-to-digital converter circuit with PVT stability of the present invention. Detailed Embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] In traditional designs, in order to be compatible with the fastest and slowest cases, the slowest case just uses up the entire conversion time. Extra power consumption and decoupling capacitors are added to the drive of the switched-capacitor DAC and the reference level generation circuit as a whole to make up for the problem of the settling time of the switched-capacitor DAC in the fastest case. This will lead to a significant increase in the area and power consumption of the entire analog-to-digital converter. The present invention proposes a PVT-stable successive approximation analog-to-digital converter, which is compatible with the fastest and slowest cases by automatically detecting the remaining conversion time and adjusting the delay.

[0022] Figure 1 FIG. is a block diagram of a traditional successive approximation analog-to-digital converter, mainly composed of a switched-capacitor DAC (Digital to Analog converter) array, a comparator, and a successive approximation logic circuit.

[0023] As Figure 2 shown, the analog-to-digital converter of the present invention is composed of a switched-capacitor DAC, a comparator, a successive approximation logic circuit, and a delay adjustment circuit. The differential input signals Vip, Vin and the reference levels Vrefp, Vrefn are input into the switched-capacitor DAC module IDAC. The capacitor top plate output voltages Vcp and Vcn of the switched-capacitor DAC are respectively connected to the positive and negative input terminals of the comparator ICMP. The positive and negative output signals of the comparator are Q and QB. Among them, the switched-capacitor DAC and the comparator are of traditional structures.

[0024] The positive and negative output signals of the comparator, Q and QB, are connected to the two input terminals of the NAND gate I1 in the successive approximation logic circuit as input signals. The output signal of I1 is a valid signal. The output terminal of the NAND gate I1 is respectively connected to the input terminal cki of the delay circuit IDLY and the CK terminals of the successive approximation units I5 - I8. The positive and negative output signals of the comparison, Q and QB, are simultaneously connected to the positive data input D terminals and the negative data input DB terminals of the successive approximation units I5 - I8. The input clock ckdff is connected to the enable input EN terminal of I5 after passing through the inverter I2; the next-level enable output terminal EN_N of I5 is connected to the EN terminal of I6; the output terminal EN_N of I6 is connected to the EN terminal of I7; the output terminal EN_N of I7 is connected to the line EN<3> to connect the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the (n - 1)th logic unit; the output terminal EN_N of I8 is connected to the input A terminal of the delay unit I9. After the delay of the delay unit, it is input to one of the input terminals of the AND gate I10 via the O terminal of I9. The output terminal EN_N of I8 is directly connected to the other input terminal of the AND gate I10. The output terminal line name of I10 is finish_dly. The data input Q terminal of the D flip-flop I3 is connected to the logic high level "1", the CK terminal is connected to the input clock ckdff, the reset input R terminal is connected to the input reset signal sar_rst, and the output D terminal obtains the synchronous reset signal rst_syn after passing through the inverter I4. The RST terminals of I5 - I8 are all connected to rst_syn. The output CTL terminals of I5 - I8 respectively output n-bit control signals Dac_ctl <n-1>To Dac_ctl<0> to the IDAC, which is used to control the capacitor lower plate switch of the switched capacitor DAC. The output Q terminals of I5 - I8 are data output terminals, respectively outputting the output data D of n out <n-1:0>As the output data of the entire analog-to-digital converter. The input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the enable clock line CMP_CK of the comparator and is connected to the ck terminal of the comparator ICMP.

[0025] The connection of the delay adjustment circuit is as follows: The finish_dly line is connected to the CK terminal of D flip-flop I11. The output D terminal of I11 is connected to the input Q terminal of I11 and the CK terminal of D flip-flop I13 through inverter I12. The output D terminal of I13 is connected to the input Q terminal of I13 and the CK terminal of D flip-flop I15 through inverter I14. The output D terminal of I15 is connected to the input Q terminal of I15, the CK terminal of D flip-flop I17, and one of the input terminals of nor gate I19 through inverter I16. The output D terminal of I17 is connected to the input Q terminal of I17 and the other input terminal of nor gate I19 through inverter I18. The reset terminals R of I11, I13, I15, and I17 are all connected to cnt_rst. The input clock ckdff line is connected to the CK terminal of D flip-flop I25. The D terminal of I25 is connected to signal ckcnt0, which is connected to the Q terminal of I25 and the CK terminal of D flip-flop I27 through inverter I26. The output D terminal of I27 is connected to signal ckcnt1, which is connected to the Q terminal of I27 and the CK terminal of D flip-flop I29 through inverter I28. The output D terminal of I29 is connected to signal ckcnt2, which is connected to the Q terminal of I29 and the CK terminal of D flip-flop I31 through inverter I30. The output D terminal of I31 is connected to signal ckcnt3, which is connected to the Q terminal of I31 and the CK terminal of D flip-flop I33 through inverter I32. The output D terminal of I33 is connected to signal ckcnt4, which is connected to the Q terminal of I33 through inverter I34. Signals ckcnt0 and ckcnt1 are respectively connected to the two input terminals of nand gate I37. Signals ckcnt2 and ckcnt3 are respectively connected to the two input terminals of nand gate I38. The output terminals of I37 and I38 are respectively connected to the two input terminals of nor gate I39. The output terminal of I39 and the input clock ckdff are respectively connected to the two input terminals of and gate I40. The reset terminals of I25, I27, I29, I31, and I33 are all connected to the cnt_rst signal. Ckcnt4 is connected to the input terminal A of delay unit I35. The output terminal O of delay unit I35 is connected to one of the input terminals of or gate I36. The other input terminal of I36 is connected to rst_syn. The output terminal of I36 is connected to signal cnt_rst. The output of I19 is connected to the Q terminal of D flip-flop I20. The output terminal of I40 is connected to the CK terminal of I20. The output terminal D of I20 is connected to the Q terminal of D flip-flop I21. The D terminal of I21 is connected to the A terminal of adder I22. The CK terminal of I21 is connected to the input signal ck. The reset terminals R of I20 and I21 are both connected to rst_syn. The B terminals of adders I24, I23, and I22 respectively input the original delay control signal dly_in<2:0>. The CO terminal of I22 is connected to the A terminal of I23. The CO terminal of I23 is connected to the CO terminal of I24.The S terminals of I22, I23, and I24 are respectively connected to the input terminals of OR gates I41, I42, and I43. The CO terminal of I24 is connected to the other input terminals of I41, I42, and I43. The output terminals of I43, I42, and I41 respectively output delay control signals dly_out<2:0>.

[0026] The timing is as follows: The frequency and phase of the input clock ckdff are the same as those of the analog-to-digital converter sampling clock. The input clock ckdff is at a high level during the sampling phase and at a low level during the conversion phase. The entire successive approximation conversion process is the same as that of the traditional structure, and n successive comparison results are respectively obtained from I5 to I8. The output signal EN of EN_N of the last successive approximation unit I8 <n>The transition from 0 to 1 indicates the end of the successive approximation conversion. Since EN is under different PVTs <n>The time from the high level to the next sampling is different. In most PVT cases, EN <n>There is still a certain amount of redundant time until the next sampling clock high level. When there is time from the rising edge of finish_dly to the next sampling high level, it means that the redundant time is still sufficient in this PVT case. Through the delay adjustment circuit, the original input delay control signal dly_in<2:0> is increased in gear. In the present invention, it is increased by 1 gear, and it can also be increased by 2 gears or more. Similarly, the input delay control signal dly_in<2:0> can also be increased to more than 3 bits or decreased to 2 bits or even 1 bit. The delay control signal dly_out<2:0> after increasing the gear is input into the delay circuit IDLY to increase the time of each conversion. Ensure that the total delay time increased by n times is less than the delay of I9. At the same time, the delay adjustment circuit adjusts based on the sampling result of the analog-to-digital converter, so it can work in the background of the analog-to-digital converter without affecting the normal operation of the analog-to-digital converter.

[0027] In the present invention, the delay adjustment circuit that works in the background automatically detects the redundant time after each successive approximation conversion is completed. When the redundant time is large enough, it will count in the delay adjustment circuit. When the redundant time at the end of most conversions is sufficient, the delay adjustment circuit will increase the gear of the delay control signal, so that the redundant time after the conversion is completed is reduced. By this method, the establishment pressure of the switched-capacitor DAC in the fast PVT case is alleviated, thereby reducing the driving pressure of the switched-capacitor DAC and the power consumption of the reference level generation circuit.

[0028] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0029] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.< / n> < / n> < / n>

Claims

1. A PVT-stable successive approximation analog-to-digital converter, characterized in that, The analog-to-digital converter is composed of a switched-capacitor DAC module, a comparator, a successive approximation logic circuit, and a delay adjustment circuit; Among them, the switched-capacitor DAC module IDAC receives differential input signals Vip, Vin, and reference levels Vrefp, Vrefn; the capacitor top plate output voltages Vcp, Vcn of the switched-capacitor DAC module are respectively connected to the positive and negative input terminals of the comparator ICMP; the positive and negative output signals Q, QB of the comparator are used as input signals and connected to the successive approximation logic circuit; the delay circuit of the successive approximation logic circuit generates the input clock CMP_CK of the comparator and inputs it to the input terminal of the comparator, and the successive approximation logic circuit gradually outputs the control signal Dac_ctl of the switched-capacitor array according to the result of the comparator <n-1:0>; Meanwhile, the successive approximation logic circuit outputs a reset signal rst_syn and a delayed conversion completion signal finish_dly to the delay adjustment circuit; the delay adjustment circuit outputs an adjusted comparator clock delay control signal dly_out<2:0> to the delay circuit of the successive approximation logic circuit to control the delay stage of the comparison clock; the successive approximation logic circuit outputs the final analog-to-digital conversion digital signal Dout <n-1:0> 。< / n-1:0> 2. The PVT-stable successive approximation analog-to-digital converter according to claim 1, wherein, The delay adjustment circuit compares the delayed conversion completion signal finish_dly output by the successive approximation logic circuit with the input clock ckdff; Among them, the input clock ckdff is of the same frequency and phase as the sampling clock of the entire analog-to-digital converter. The input clock ckdff is at a high level during the sampling phase and at a low level during the conversion phase; When there is redundant time after the successive approximation conversion is completed, the delay adjustment circuit will increase the gear of the input delay control signal dly_out<2:0>, and utilize the above-mentioned redundant time to relieve the establishment pressure of the switched-capacitor DAC in the fast PVT situation, thereby reducing the driving pressure of the switched-capacitor DAC and the power consumption of the reference level generation circuit.

3. The PVT-stable successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that, The successive approximation logic circuit includes a delay circuit IDLY, a NAND gate I1, successive approximation units I5, I6, I7, and I8, a delay unit I9, an AND gate I10, a D flip-flop I3, and an inverter I4; Among them, the positive and negative output signals of the comparator, Q and QB, are connected to the two input terminals of the NAND gate I1 in the successive approximation logic circuit as input signals; the output signal of the NAND gate I1 is a valid signal, and the output terminal of the NAND gate I1 is respectively connected to the input terminal cki of the delay circuit IDLY and the CK terminals of the successive approximation units I5, I6, I7, and I8; the positive and negative output signals Q and QB of the comparator are also simultaneously connected to the positive data input D terminals and the negative data input DB terminals of the successive approximation units I5, I6, I7, and I8; the enable input terminal EN of the successive approximation unit I5 is connected to the input clock ckdff through an inverter I2; the next-level enable output terminal EN_N of the successive approximation unit I5 is connected to the EN terminal of the successive approximation unit I6; the output terminal EN_N of the successive approximation unit I6 is connected to the EN terminal of the successive approximation unit I7; the output terminal EN_N of the successive approximation unit I7 is connected to the line EN<3> to connect the next successive approximation unit; the EN terminal of the nth successive approximation unit I8 is connected to the EN_N terminal of the (n - 1)th successive logic unit; the output terminal EN_N of the successive approximation unit I8 is connected to the input A terminal of the delay unit I9, and after being delayed by the delay unit I9, it is input to one of the input terminals of the AND gate I10 through its O terminal, and the output terminal EN_N of the successive approximation unit I8 is directly connected to the other input terminal of the AND gate I10; the output terminal line name of the AND gate I10 is finish_dly; the data input Q terminal of the D flip-flop I3 is connected to the logic high level "1", the clock input CK terminal is connected to the input clock ckdff, the reset input R terminal is connected to the input reset signal sar_rst, and the output D terminal obtains the synchronous de-reset signal rst_syn through an inverter I4; The RST terminals of the successive approximation units I5, I6, I7, and I8 are all connected to rst_syn; the output CTL terminals of the successive approximation units I5, I6, I7, and I8 respectively output n-bit control signals Dac_ctl <n-1>To Dac_ctl<0> to the IDAC, which is used to control the capacitor lower plate switches of the switched-capacitor DAC; the output Q terminals of the successive approximation units I5, I6, I7, and I8 are data output terminals, respectively outputting the output data D of n out <n-1:0>As the output data of the entire analog-to-digital converter; the input terminal dly of the delay circuit IDLY is connected to the delay control signal dly_out<2:0>; the output terminal cko of the delay circuit IDLY is connected to the enable clock line CMP_CK of the comparator and is connected to the ck terminal of the comparator ICMP.

4. The PVT-stable successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that The delay adjustment circuit includes D flip-flops I11, I13, I15, I17, I20, I21, I25, I27, I29, I31 and I33, inverters I12, I14, I16, I18, I26, I28, I30, I32 and I34, NOR gates I19, I39, NAND gates I37, I38, AND gate I40, OR gates I36, I41, I42, I43, adders I22, I23, I24 and delay unit I35; Among them, the finish_dly line is connected to the CK terminal of D flip-flop I11, and the output D terminal of D flip-flop I11 is connected to the input Q terminal of I11 and the CK terminal of D flip-flop I13 through inverter I12; the output D terminal of D flip-flop I13 is connected to the input Q terminal of I13 and the CK terminal of D flip-flop I15 through inverter I14; the output D terminal of D flip-flop I15 is connected to the input Q terminal of D flip-flop I15, the CK terminal of D flip-flop I17 and one input terminal of NOR gate I19 through inverter I16; the output D terminal of D flip-flop I17 is connected to the input Q terminal of D flip-flop I17 and the other input terminal of NOR gate I19 through inverter I18.

5. The PVT-stable successive approximation analog-to-digital converter according to claim 4, wherein, The reset terminals R of the D flip-flops I11, I13, I15 and I17 are all connected to cnt_rst; the input clock ckdff line is connected to the CK terminal of D flip-flop I25, and the D terminal of D flip-flop I25 is connected to signal ckcnt0 and is connected to the Q terminal of D flip-flop I25 and the CK terminal of D flip-flop I27 through inverter I26; The output D terminal of D flip-flop I27 is connected to signal ckcnt1 and is connected to the Q terminal of D flip-flop I27 and the CK terminal of D flip-flop I29 through inverter I28; The output D terminal of D flip-flop I29 is connected to signal ckcnt2 and is connected to the Q terminal of D flip-flop I29 and the CK terminal of D flip-flop I31 through inverter I30; The output D terminal of D flip-flop I31 is connected to signal ckcnt3 and is connected to the Q terminal of D flip-flop I31 and the CK terminal of D flip-flop I33 through inverter I32; The output D terminal of D flip-flop I33 is connected to signal ckcnt4 and is connected to the Q terminal of D flip-flop I33 through inverter I34; The signals ckcnt0 and ckcnt1 are respectively connected to the two input terminals of the NAND gate I37; the signals ckcnt2 and ckcnt3 are respectively connected to the two input terminals of the NAND gate I38; the output terminals of the NAND gates I37 and I38 are respectively connected to the two input terminals of the NOR gate I39; the output terminal of the NOR gate I39 and the input clock ckdff are respectively connected to the two input terminals of the AND gate I40; the reset terminals of the D flip-flops I25, I27, I29, I31 and I33 are all connected to the cnt_rst signal; The signal ckcnt4 is connected to the input terminal A of the delay unit I35, and is connected to one of the input terminals of the OR gate I36 through the output terminal O of the logic unit I35. The other input terminal of the OR gate I36 is connected to rst_syn, and the output terminal of the OR gate I36 is connected to the signal cnt_rst.

6. The PVT-stable successive approximation analog-to-digital converter according to claim 5, wherein The output of the NOR gate I19 is connected to the Q terminal of the D flip-flop I20; The output terminal of the AND gate I40 is connected to the CK terminal of the D flip-flop I20; The output terminal D of the D flip-flop I20 is connected to the Q terminal of the D flip-flop I21; The D terminal of the D flip-flop I21 is connected to the A terminal of the adder I22, and the CK terminal of the D flip-flop I21 is connected to the input signal ck; The reset terminals R of the D flip-flops I20 and I21 are both connected to rst_syn; the B terminals of the adders I22, I23 and I24 respectively input the original delay control signal dly_in<2:0>; the CO terminal of the adder I22 is connected to the A terminal of the adder I23, and the CO terminal of the adder I23 is connected to the CO terminal of the adder I24; the S terminals of the adders I22, I23 and I24 are respectively connected to the input terminals of the OR gates I41, I42 and I43; the CO terminal of the adder I24 is connected to the other input terminals of the OR gates I41, I42 and I43; the output terminals of the OR gates I41, I42 and I43 respectively output the delay control signals dly_out<2:0>.

Images