Protocol layer data sending method and device for FPGA (Field Programmable Gate Array) data transmission

Abstract

The embodiment of the invention provides a protocol layer data sending method and device for FPGA data transmission, and the method comprises the steps: obtaining to-be-sent data, and carrying out the packaging of the to-be-sent data, and determining a packaging result; storing the packaging result to a sending cache region; wherein the number of the sending cache regions is at least two, and the sending cache regions are in one-to-one correspondence with the types of the data to be sent; sending a judgment request to a judgment device, wherein the judgment device judges the priority of the packet result based on the judgment request; and the sending module receives a sending instruction of the resolver, and sends the packaging result to the sending module based on the sending instruction. According to the method, a resolver mode is used for solving the problem of use of competitive resources of a plurality of processes, a dichotomy priority resolver algorithm is provided and realized, the speed of the resolver algorithm is improved, and the method is more suitable for high-speed data transmission communication.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of FPGA programming, and particularly to a method for sending protocol layer data for FPGA data transmission. Background Art

[0002] With the development of communication technologies, the speed of data communication is getting higher and higher. High-speed data communication is applied in more and more fields. Data exchange can be achieved through high-speed communication between different data devices, between different boards of the same device, and even between different components of the same board. The protocols for data exchange have become more and more perfect and complex. The protocol layer is an independent layer in the international standard data communication model and is a very important part of data communication. The technical level achieved by the protocol layer has a significant impact on the performance of the entire data communication product.

[0003] For customized projects to achieve certain unique performances or special technical requirements, some non-generalized design schemes and non-standard interface modes are usually adopted. It is very difficult to use general data communication components or chips for such design schemes. Such schemes can only use general functional chips (FPGA or CPU) as the hardware carrier, and then implement the functions of the scheme through firmware / software programming of these chips. Due to the extremely high data throughput rate of high-speed data communication (up to dozens of Gb / s or even hundreds of Gb / s), FPGA is almost the only optional chip for such schemes. The GTX interface configured by FPGA is the physical layer interface for data communication. The protocol layer for high-speed communication is implemented by programming the general logic array of FPGA.

[0004] The programming language of FPGA (Verilog or VHDL) is a hardware description language, a parallel processing program statement, and is suitable for the implementation of high-speed signal processing flows. FPGA uses a state machine to describe the states of various stages in the process, and realizes state transitions based on various signal quantities to implement a specific function of the signal processing flow. Traditional protocol layer programming uses a state machine to describe complex communication protocols, resulting in a large number of states in the state machine, complex and variable state jump branches, and chaotic and complicated execution flows of the state machine. Such programming leads to low program development efficiency, long development cycles, chaotic program code structures, easy errors, and poor maintainability and scalability.

[0005] Therefore, there is an urgent need for a better solution. Summary of the Invention

[0006] In view of this, the embodiments of this specification provide a method for sending protocol layer data for FPGA data transmission. One or more embodiments of this specification simultaneously relate to a device for sending protocol layer data for FPGA data transmission, a computing device, a computer-readable storage medium, and a computer program to solve the technical defects existing in the prior art.

[0007] According to the first aspect of the embodiments of the present specification, a protocol layer data sending method for FPGA data transmission is provided, including: Obtain the data to be sent, packetize the data to be sent to determine the packetization result; Store the packetization result in the transmission buffer; wherein, there are at least two transmission buffers, and the transmission buffers correspond one-to-one to the types of the data to be sent; Send a arbitration request to the arbiter, and the arbiter arbitrates the priority of the packetization result based on the arbitration request; Receive the transmission instruction from the arbiter, and send the packetization result to the transmission module based on the transmission instruction.

[0008] In a possible implementation manner, obtaining the data to be sent, packetizing the data to be sent to determine the packetization result includes: Determine the task characteristics and the packetization protocol; Determine the packetization process based on the task characteristics and the packetization protocol; Packetize the data to be sent based on the packetization process to determine the packetization result.

[0009] In a possible implementation manner, storing the packetization result in the transmission buffer includes: Determine the type corresponding to the packetization result; Send the packetization result to the buffer based on the type.

[0010] In a possible implementation manner, the arbiter arbitrates the priority of the packetization result based on the arbitration request, including: The arbiter arbitrates the priority of the packetization result by the binary method based on the arbitration request.

[0011] In a possible implementation manner, the arbiter arbitrates the priority of the packetization result by the binary method based on the arbitration request, including: Determine the number of input signals; Determine the number of iterations based on the number of input signals; Arbitrate the priority of the packetization result based on the number of iterations.

[0012] In a possible implementation manner, it further includes: Determine the input quantity, sort the priorities based on the input quantity to determine the sorting result; Determine the transmission instruction based on the sorting result.

[0013] In a possible implementation manner, it further includes: After receiving the acknowledgement number in the receiving process, set the handshake signal Axis_tData to the acknowledgement number and set Axis_tValid to 1; Sample Axis_tReady. After sending a frame of data in the data sending process, set Axis_tReady to 1 and sample Axis_tValid. If both Axis_tValid and Axis_tReady are 1, the sending process reads Axis_tData and releases the sending buffer based on the read data as the baseline. When the receiving process samples that both Axis_tValid and Axis_tReady are 1, it determines that the handshake is successful and resets Axis_tValid.

[0014] According to the second aspect of the embodiments of this specification, a protocol layer data sending device for FPGA data transmission is provided, including: A packet encapsulation module, configured to obtain data to be sent and perform packet encapsulation on the data to be sent to determine the packet encapsulation result; A buffer module, configured to store the packet encapsulation result in a sending buffer; wherein, there are at least two sending buffers, and the sending buffers correspond one-to-one to the types of data to be sent; An arbitration module, configured to send an arbitration request to an arbiter, and the arbiter arbitrates the priority of the packet encapsulation result based on the arbitration request; A sending module, configured to receive the sending instruction from the arbiter and send the packet encapsulation result to the sending module based on the sending instruction.

[0015] According to the third aspect of the embodiments of this specification, a computing device is provided, including: A memory and a processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data sending method for FPGA data transmission are implemented.

[0016] According to the fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided, which stores computer-executable instructions. When the instructions are executed by a processor, the steps of the above-mentioned protocol layer data sending method for FPGA data transmission are implemented.

[0017] According to the fifth aspect of the embodiments of this specification, a computer program is provided. When the computer program is executed on a computer, the computer is made to execute the steps of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0018] The embodiments of this specification provide a protocol layer data sending method and apparatus for FPGA data transmission. The protocol layer data sending method for FPGA data transmission includes: obtaining data to be sent, performing packet encapsulation on the data to be sent to determine the packet encapsulation result; storing the packet encapsulation result in a sending buffer; where there are at least two sending buffers, and the sending buffers correspond one-to-one to the types of data to be sent; sending a arbitration request to an arbiter, and the arbiter arbitrates the priority of the packet encapsulation result based on the arbitration request; receiving a sending instruction from the arbiter, and sending the packet encapsulation result to a sending module based on the sending instruction. The arbiter method is used to solve the problem of multiple processes competing for resource usage, and the binary priority arbitration algorithm is proposed and implemented, which improves the speed of the arbitration algorithm and makes it more suitable for high-speed data transmission communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a flowchart of a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 2 is a schematic diagram of parallel processing of a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 3 is a schematic diagram of packet encapsulation in the sending process of a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 4 is a schematic diagram of a sending module based on an arbiter in a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 5 is a schematic diagram of a priority algorithm based on the binary method in a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 6 is a schematic diagram of the data sending module process in a protocol layer data sending method for FPGA data transmission provided by an embodiment of this specification; Figure 7 is a schematic diagram of the structure of a protocol layer data sending apparatus for FPGA data transmission provided by an embodiment of this specification; Figure 8 is a block diagram of the structure of a computing device provided by an embodiment of this specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Many specific details are set forth in the following description in order to provide a thorough understanding of this specification. However, this specification can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of this specification. Therefore, this specification is not limited by the specific embodiments disclosed below.

[0021] The terms used in one or more embodiments of this specification are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of this specification. The singular forms "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0022] It should be understood that although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0023] In this specification, a method for sending protocol layer data for FPGA data transmission is provided. This specification also relates to a device for sending protocol layer data for FPGA data transmission, a computing device, and a computer-readable storage medium, which will be described in detail one by one in the following embodiments.

[0024] See Figure 1 , Figure 1 which shows a flowchart of a method for sending protocol layer data for FPGA data transmission according to an embodiment of this specification, specifically including the following steps.

[0025] Step 101: Obtain the data to be sent, and packetize the data to be sent to determine the packetization result; In a possible implementation, obtaining the data to be sent and packetizing the data to be sent to determine the packetization result includes: determining the task characteristics and the packetization protocol; determining the packetization process based on the task characteristics and the packetization protocol; and packetizing the data to be sent based on the packetization process to determine the packetization result.

[0026] In practical applications, in the data reception process of the FPGA, based on the programming characteristics of the FPGA, it can be designed to achieve as Figure 2The parallel processing shown, in which the protocol input data can be sent to the function 1 module processing module, function 2 module processing module... function n module processing module, as well as data processing module 1, data processing module 2... data processing module m. Correspondingly, the function 1 module processing module, function 2 module processing module... function n module processing module respectively generate reply data frame 1, reply data frame 2... reply data frame n or jump to other processes, and the data processed by data processing module 1, data processing module 2... data processing module m are respectively stored in data buffer 1, data buffer 2... data buffer m. FPGA programming essentially combines some discrete logic gates into user-specified functional units. Parallel processing is to form multiple functional units at one time. These functional units are physically independent and independently execute their own program flows under the drive of the clock. In FPGA programming, the program flow is the design and implementation of the state machine. The state machine realizes each step of the functional flow through state jumps.

[0027] Furthermore, in the data sending process of the FPGA, data frame sending is divided into two categories: active sending and response. The active sending program is an active data or control transmission process. Such as the first sending during link establishment, broadcast addressing before sending, the first packet of data sent, etc. The response data is the response to the received data. Such as the response to addressing, the response to link establishment, data confirmation response, etc.

[0028] See Figure 3 , whether it is active sending or passive response of data frames, the present invention sets an independent processing process for their transmission tasks in the firmware implementation. The main task of each process is to packet according to the characteristics of the task. For example, active task 0, active task 1, active task p, passive task p, passive task q respectively correspond to a packet process and a sending buffer. The level of the packet hierarchy is determined by the specific protocol. Such an architecture is designed based on the characteristics of parallel execution of FPGA firmware. Assigning an independent sending process to each sending task avoids the coupling between processes, makes the process execution as simple as possible, and avoids complex tree-like bifurcations.

[0029] Step 102: Store the packet result in the sending buffer; wherein, there are at least two sending buffers, and the sending buffers correspond one by one to the types of data to be sent; In a possible implementation manner, storing the packet result in the sending buffer includes: determining the type corresponding to the packet result; and sending the packet result to the buffer based on the type.

[0030] In practical applications, the packet results of all sending processes are stored in their own exclusive sending buffers and wait to be sent. All sendings can only be sent through one physical channel and must be sent in sequence. The sending order is determined by the priority of each sending process in the arbitration module.

[0031] Step 103: Send a ruling request to the arbiter, and the arbiter rules on the priority of the packet result based on the ruling request; In a possible implementation, the arbiter rules on the priority of the packet result based on the ruling request, including: the arbiter rules on the priority of the packet result by means of the dichotomy method based on the ruling request.

[0032] In practical applications, refer to Figure 4 , if there is data to be sent in transmission buffer 0, transmission buffer 1... transmission buffer g, a arbiter is set to rule on which buffer's data is sent first. Among them, the arbiter accepts a ruling query (Ack) and returns a ruling result (Apply). Compared with the traditional state machine-based mode and arbiter-based programming mode, the setting of the transmission order priority is more intuitive and flexible. Without changing the program framework, by changing the position of the application line of the transmission pipeline, the priority of the transmission unit can be changed. And a multi-level and multi-mode priority arbiter architecture can be designed.

[0033] Specifically, the arbiter is one of the core modules of the sending program, and its performance has a significant impact on the performance of the entire sending program. The embodiment of this specification proposes a basic arbiter design method based on the dichotomy method. It is specifically described as follows.

[0034] In a possible implementation, the arbiter rules on the priority of the packet result by means of the dichotomy method based on the ruling request, including: determining the number of input signals; determining the number of iterations based on the number of input signals; ruling on the priority of the packet result based on the number of iterations.

[0035] In practical applications, refer to Figure 5 , the basic arbiter design mode includes: there are 0 to N-1 input signals, N = 2 n , the smaller the input number, the higher the priority. Thus, an algorithm can be designed to quickly find the signal with the highest priority.

[0036] From the above Figure 5 it can be seen that the number of iterations of the flowchart based on the dichotomy method is , for example: the number of iterations of the priority algorithm for 16 input sources is 4 times, which is better than the 16 times of the traditional sequential comparison method.

[0037] In the actual FPGA implementation, the priority algorithm is implemented by combinational circuits. The smaller number of iterations results in less delay and is suitable for high-speed data transmission projects.

[0038] In a possible implementation, it further includes: determining the input quantity, sorting the priorities based on the input quantity to obtain a sorting result; determining a sending instruction based on the sorting result.

[0039] In practical applications, if an input quantity is added to the basic priority arbitration algorithm, the original priority inputs are re-sorted based on this input quantity, the priority of the input quantity is set to the highest, and the remaining priorities are decreased in turn (cyclically included when greater than the maximum input), and then the basic priority algorithm is called, the Round-Robin sequential priority sorting algorithm can be obtained.

[0040] By combining priority sorting and Round-Robin, a comprehensive and flexible priority arbitration method can be obtained. In practical high-speed data transmission applications, flow control short frame information has a higher priority, and the priority of data transmission is lower. If the same data transmission priority is used, then Round-Robin cyclic sequential transmission is adopted.

[0041] In a possible implementation, it further includes: after receiving the acknowledgement sequence number in the receiving process, setting the handshake signal Axis_tData to the acknowledgement sequence number and setting Axis_tValid to 1; sampling Axis_tReady, in the data sending process, after sending a frame of data, setting Axis_tReady to 1 and sampling Axis_tValid, if both Axis_tValid and Axis_tReady are 1, the sending process reads in Axis_tData and releases the sending buffer based on the read data as the baseline; in the receiving process, when sampling that both Axis_tValid and Axis_tReady are 1, it is determined that the handshake is successful and Axis_tValid is reset.

[0042] In practical applications, the communication between individual functional modules in the payload data sending process is completed through the Valid / Ready handshake mechanism. The sending of payload data packets and the receiving of acknowledgment packets are two independent processes. There is no clear temporal association between the end of data frame transmission and the receipt of the acknowledgment data frame sequence number. However, the data frame sending process must handle data acknowledgment information at the end of the frame. To address the issue of asynchronous timing between the sending and receiving processes, the Valid / Ready handshake synchronization mechanism is adopted in the program. After the receiving program receives the acknowledgment sequence number, it sets the handshake signal Axis_tData to the received acknowledgment sequence number and sets Axis_tValid to 1 simultaneously. Then it continuously samples Axis_tReady. After the data sending process finishes sending a frame of data, it sets Axis_tReady to 1 and samples Axis_tValid at the same time. If both Axis_tValid and Axis_tReady are 1, the sending process reads Axis_tData and releases the sending buffer based on the read data. When the data receiving process samples that both Axis_tValid and Axis_tReady are 1, it considers the handshake successful, resets Axis_tValid, and waits for the next reception. The receiving process is in a waiting state from the receipt of the valid data acknowledgment frame number to the receipt of the handshake signal. This is the Valid / Ready waiting handshake mechanism in asynchronous mode.

[0043] Step 104: Receive the sending instruction from the arbitration unit and send the packet result to the sending module based on the sending instruction.

[0044] In practical applications, after the arbitration unit completes the arbitration, the packet result can be sent to the sending module based on the sending instruction of the arbitration unit.

[0045] In an overall embodiment, refer to Figure 6 , the data sending process includes: applying for data from the data source, writing it into the buffer to be transmitted, framing, writing it into the sending buffer, applying for data sending, sending data, processing the response signal, and releasing the buffer.

[0046] Figure 6It is a schematic diagram of the data sending process. When the application layer determines to send data and places the data to be sent in the app data source, when the link establishment is completed or the data sending condition is met, the data application module applies to the data source for sending data, and the amount of data applied for is half of the capacity of the sending buffer; frame assembly is performed, the data frame contains a data frame number, and the frames are sequentially sent in a sending window according to the command of the sending control module. During the frame interval of the sent frames, it is judged whether a reply message is received. If a reply frame is received, the data in the app data source before the acknowledgment frame number in the reply frame is marked as "sent and acknowledged state", and the acknowledged sending part in the sending buffer is released. When the amount of data in the sending buffer is less than 1 / 4 of the buffer capacity, the data source application module applies for sending data again, performs frame assembly, and sends it, and so on in a cycle until all data is sent completely.

[0047] The embodiments of this specification provide a protocol layer data sending method and device for FPGA data transmission. The protocol layer data sending method for FPGA data transmission includes: obtaining data to be sent, performing packet encapsulation on the data to be sent to determine the packet encapsulation result; storing the packet encapsulation result in a sending buffer; where there are at least two sending buffers, and the sending buffers correspond one-to-one to the types of data to be sent; sending a arbitration request to an arbiter, and the arbiter arbitrates the priority of the packet encapsulation result based on the arbitration request; receiving the sending instruction from the arbiter, and sending the packet encapsulation result to a sending module based on the sending instruction. The arbiter method is used to solve the problem of multiple processes competing for resource usage, and the binary priority arbitration algorithm is proposed and implemented, which improves the speed of the arbitration algorithm and makes it more suitable for high-speed data transmission communication.

[0048] Corresponding to the above method embodiments, this specification also provides embodiments of a protocol layer data sending device for FPGA data transmission. Figure 7 The structure diagram of a protocol layer data sending device provided by an embodiment of this specification is shown. As Figure 7 shown, the device includes: A packet encapsulation module 701, configured to obtain data to be sent and perform packet encapsulation on the data to be sent to determine the packet encapsulation result; A caching module 702, configured to store the packet encapsulation result in a sending buffer; where there are at least two sending buffers, and the sending buffers correspond one-to-one to the types of data to be sent; An arbitration module 703, configured to send an arbitration request to an arbiter, and the arbiter arbitrates the priority of the packet encapsulation result based on the arbitration request; A sending module 704, configured to receive the sending instruction from the arbiter and send the packet encapsulation result to the sending module based on the sending instruction.

[0049] In a possible implementation, obtain the data to be sent, and packetize the data to be sent to determine the packetization result, including: Determine the task characteristics and the packetization protocol; Determine the packetization process based on the task characteristics and the packetization protocol; Packetize the data to be sent based on the packetization process to determine the packetization result.

[0050] In a possible implementation, store the packetization result in the transmission buffer, including: Determine the type corresponding to the packetization result; Send the packetization result to the buffer based on the type.

[0051] In a possible implementation, the arbiter arbitrates the priority of the packetization result based on an arbitration request, including: The arbiter arbitrates the priority of the packetization result by the binary search method based on the arbitration request.

[0052] In a possible implementation, the arbiter arbitrates the priority of the packetization result by the binary search method based on the arbitration request, including: Determine the number of input signals; Determine the number of iterations based on the number of input signals; Arbitrate the priority of the packetization result based on the number of iterations.

[0053] In a possible implementation, it further includes: Determine the input quantity, sort the priorities based on the input quantity to determine the sorting result; Determine the transmission indication based on the sorting result.

[0054] In a possible implementation, it further includes: After receiving the acknowledgement sequence number in the receiving process, set the handshake signal Axis_tData to the acknowledgement sequence number and set Axis_tValid to 1; Sample Axis_tReady. After the data transmission process finishes sending a frame of data, set Axis_tReady to 1 and sample Axis_tValid. If both Axis_tValid and Axis_tReady are 1, the transmission process reads Axis_tData and releases the transmission buffer based on the read data as the baseline; When the receiving process samples that both Axis_tValid and Axis_tReady are 1, determine that the handshake is successful and reset Axis_tValid.

[0055] The embodiments of this specification provide a protocol layer data sending method and device for FPGA data transmission. The protocol layer data sending device for FPGA data transmission includes: obtaining data to be sent, performing packet encapsulation on the data to be sent to determine the packet encapsulation result; storing the packet encapsulation result in a sending buffer; wherein, there are at least two sending buffers, and the sending buffers correspond one-to-one to the types of data to be sent; sending a arbitration request to an arbiter, and the arbiter arbitrates the priority of the packet encapsulation result based on the arbitration request; receiving a sending instruction from the arbiter, and sending the packet encapsulation result to a sending module based on the sending instruction. The arbiter method is used to solve the problem of multiple processes competing for resource usage, and the binary priority arbitration algorithm is proposed and implemented, improving the speed of the arbitration algorithm and making it more suitable for high-speed data transmission communication.

[0056] The above is a schematic solution of a protocol layer data sending device for FPGA data transmission in this embodiment. It should be noted that the technical solution of the protocol layer data sending device for FPGA data transmission and the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission belong to the same concept. For the details not described in the technical solution of the protocol layer data sending device for FPGA data transmission, reference can be made to the description of the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0057] Figure 8 The structural block diagram of a computing device 800 provided according to an embodiment of this specification is shown. The components of the computing device 800 include but are not limited to a memory 810 and a processor 820. The processor 820 is connected to the memory 810 through a bus 830, and a database 850 is used to store data.

[0058] The computing device 800 also includes an access device 840 that enables the computing device 800 to communicate via one or more networks 860. Examples of such networks include the Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or a combination of communication networks such as the Internet. The access device 840 may include one or more of any type of wired or wireless network interface (e.g., a network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, Worldwide Interoperability for Microwave Access (Wi-MAX) interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth interface, Near Field Communication (NFC).

[0059] In one embodiment of the present specification, the above components of the computing device 800, as well as Figure 8 other components not shown, may also be connected to each other, for example, via a bus. It should be understood that Figure 8 the block diagram of the computing device shown is for illustrative purposes only and is not a limitation on the scope of the present specification. Those skilled in the art may add or replace other components as needed.

[0060] The computing device 800 can be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, personal digital assistant, laptop computer, notebook computer, netbook, etc.), a mobile phone (e.g., a smartphone), a wearable computing device (e.g., a smartwatch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or a Personal Computer (PC). The computing device 800 can also be a mobile or stationary server.

[0061] Among them, the processor 820 is used to execute the following computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data sending method for FPGA data transmission are implemented. The above is a schematic solution of a computing device in this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission belong to the same concept. For the details not described in the technical solution of the computing device, reference can be made to the description of the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0062] An embodiment of this specification also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned protocol layer data sending method for FPGA data transmission are implemented.

[0063] The above is a schematic solution of a computer-readable storage medium in this embodiment. It should be noted that the technical solution of this storage medium and the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission belong to the same concept. For the details not described in the technical solution of the storage medium, reference can be made to the description of the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0064] An embodiment of this specification also provides a computer program. When the computer program is executed on a computer, the computer is made to execute the steps of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0065] The above is a schematic solution of a computer program in this embodiment. It should be noted that the technical solution of this computer program and the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission belong to the same concept. For the details not described in the technical solution of the computer program, reference can be made to the description of the technical solution of the above-mentioned protocol layer data sending method for FPGA data transmission.

[0066] The specific embodiments of this specification are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be executed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0067] The computer instructions include computer program code, which may be in the form of source code, object code, executable files or some intermediate forms, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, mobile hard disks, magnetic disks, optical disks, computer memories, read-only memories (ROMs), random access memories (RAMs), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0068] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of this specification are not limited by the described action sequence, because according to the embodiments of this specification, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this specification.

[0069] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The alternative embodiments do not elaborate on all the details and do not limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the embodiments of this specification, so that those skilled in the art can well understand and utilize this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A protocol layer data sending method for FPGA data transmission, characterized in that, Including: Obtain the data to be sent, packetize the data to be sent to determine the packetization result; Store the packetization result in the transmission buffer; wherein, there are at least two transmission buffers, and the transmission buffers correspond one-to-one to the types of the data to be sent; Send a arbitration request to the arbiter, and the arbiter arbitrates the priority of the packetization result based on the arbitration request; Receive the transmission instruction from the arbiter, and send the packetization result to the transmission module based on the transmission instruction.

2. The method according to claim 1, wherein Obtain the data to be sent, packetize the data to be sent to determine the packetization result, including: Determine the task characteristics and the packetization protocol; Determine the packetization process based on the task characteristics and the packetization protocol; Packetize the data to be sent based on the packetization process to determine the packetization result.

3. The method according to claim 1, wherein Store the packetization result in the transmission buffer, including: Determine the type corresponding to the packetization result; Send the packetization result to the buffer based on the type.

4. The method according to claim 1, characterized in that The arbiter arbitrates the priority of the packetization result based on the arbitration request, including: The arbiter arbitrates the priority of the packetization result by the dichotomy method based on the arbitration request.

5. The method according to claim 4, wherein The arbiter arbitrates the priority of the packetization result by the dichotomy method based on the arbitration request, including: Determine the number of input signals; Determine the number of iterations based on the number of input signals; Arbitrate the priority of the packetization result based on the number of iterations.

6. The method according to claim 1 or 5, characterized in that Also including: Determine the input quantity, sort the priorities based on the input quantity to determine the sorting result; Determine the transmission instruction based on the sorting result.

7. The method according to claim 1, wherein Also including: After receiving the acknowledgement number in the receiving process, set the handshake signal Axis_tData to the acknowledgement number and set Axis_tValid to 1; Sample Axis_tReady. After the data sending process sends a frame of data, set Axis_tReady to 1 and sample Axis_tValid. If both Axis_tValid and Axis_tReady are 1, then the sending process reads Axis_tData, and releases the transmission buffer based on the read data as the baseline; When the receiving process samples that both Axis_tValid and Axis_tReady are 1, determine that the handshake is successful and reset Axis_tValid.

8. A protocol layer data sending device for FPGA data transmission, characterized in that, Including: A packetization module, configured to obtain the data to be sent, and packetize the data to be sent to determine the packetization result; A cache module, configured to store the packetization result in the transmission buffer; wherein, there are at least two transmission buffers, and the transmission buffers correspond one-to-one to the types of the data to be sent; An arbitration module, configured to send an arbitration request to the arbiter, and the arbiter arbitrates the priority of the packetization result based on the arbitration request; A transmission module, configured to receive the transmission instruction from the arbiter, and send the packetization result to the transmission module based on the transmission instruction.

9. A computing device, characterized in that, Including: A memory and a processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the protocol layer data sending method for FPGA data transmission described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the steps of the protocol layer data sending method for FPGA data transmission described in any one of claims 1 to 7 are implemented.

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