MOSFET device and manufacturing method thereof
By forming a second Schottky metal layer at the bottom of the trench of the SiC Trench MOSFET, the problem of electric field concentration at the corners of the gate oxide layer is solved, and the reliability and switching speed of the device are improved.
Patent Information
- Application Number
- CN202510559878.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-07-22
AI Technical Summary
SiC Trench MOSFET devices tend to concentrate a large electric field at the corners of the gate oxide layer, resulting in reliability problems.
A second Schottky metal layer is formed at the bottom of the trench, and the metal silicide is formed by rapid thermal annealing treatment to reduce the electric field strength at the bottom of the gate trench.
Improves device reliability, reduces Miller capacitor Cgd, and increases switching speed.
Smart Images
Figure CN120358768A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor power devices, and particularly relates to a MOSFET device and a manufacturing method thereof. Background Art
[0002] The third-generation semiconductor material silicon carbide (SiC) is a crystal formed by the stable combination of carbon and silicon elements, and has unique physical and chemical properties. With superior properties such as a wide bandgap, high thermal conductivity, and high carrier saturation mobility, it has unique advantages and broad prospects in the fields of high power, high frequency, and high voltage. Currently, SiC MOSFETs have been widely applied in automotive electronics, photovoltaics, energy storage, etc.
[0003] The trench MOSFET developed in recent years, compared with the planar MOSFET, not only eliminates the JFET effect, reduces the internal impedance and makes the on-resistance closer to the ideal value; but also can reduce the cell size, increase the cell density, thereby increasing the current density and effectively saving the chip area. Therefore, the SiC Trench MOSFET has become one of the research hotspots of SiC power devices due to its advantages of small specific on-resistance and large cell density. However, the critical breakdown field strength of SiC is particularly high and the quality of the gate oxide is poor. Therefore, due to the structural characteristics of the SiC Trench MOSFET, this will cause a large electric field to concentrate at the corner of the gate oxide layer, resulting in the breakdown of the gate oxide layer and serious reliability problems.
[0004] It should be noted that the information disclosed in this background art section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art already known to those of ordinary skill in the art. Summary of the Invention
[0005] To solve the problems of the prior art, the present invention provides a new manufacturing method for SiC Trench MOSFET to effectively reduce the electric field strength at the bottom of the gate trench and improve the reliability of the device.
[0006] The present invention provides a manufacturing method of a MOSFET device, which includes the following steps: growing an N-type drift region on a substrate; etching the N-type drift region to form a trench; disposing a P-type base region on the N-type drift region; disposing an N+ source region on the P-type base region; disposing a P+ ohmic contact region on the P-type base region, and the P+ ohmic contact region is connected to the N+ source region; first depositing a first Schottky metal layer on the surfaces of the N-type drift region, the P-type base region, the N+ source region and the P+ ohmic contact region, and then filling the trench with an oxide layer, and the oxide layer is located above the first Schottky metal layer; etching the oxide layer and the first Schottky metal layer to make the oxide layer and the first Schottky metal layer lower than the P-type base region; performing a rapid thermal annealing process to form a second Schottky metal layer between the first Schottky metal layer and the N-type drift region, and then etching and removing the oxide layer and the first Schottky metal layer.
[0007] Further, the material of the first Schottky metal layer includes Ti, Mo, Pt or Ni.
[0008] Further, the manufacturing method of the MOSFET device further includes the following steps: Depositing a polysilicon layer in the trench, then performing gate oxidation to form a gate oxide layer, and then depositing polysilicon again to form a gate; Growing an interlayer dielectric layer on the surfaces of the gate oxide layer, the N+ source region and the P+ ohmic contact region, then depositing Ni through photolithography and etching, annealing to form a contact region, and then depositing metal, performing photolithography and etching to form a source electrode.
[0009] Further, the thickness range of the N-type drift region is 5 - 15 μm.
[0010] Further, the doping concentration range of the N-type drift region is 7×10 15 / cm 3 ~1.1×10 16 / cm 3 。
[0011] Further, the material of the substrate includes silicon carbide.
[0012] Further, before depositing the first Schottky metal layer, a carbon film is first deposited on the surfaces of the N-type drift region, the P-type base region, the N+ source region and the P+ ohmic contact region as a protective layer, and then a high-temperature annealing process is performed at a temperature of 1800 - 2000 °C for a time of 10 min - 30 min, and the carbon film is removed after annealing.
[0013] Further, after etching the oxide layer and the first Schottky metal layer, the distance from the oxide layer to the bottom of the trench accounts for 1 / 4 of the depth of the trench.
[0014] Further, the second Schottky metal layer is disposed on the sidewalls and bottom of the trench.
[0015] The present invention also provides a MOSFET device, which is fabricated by using the manufacturing method of the MOSFET device described in any one of the foregoing.
[0016] A MOSFET device and a manufacturing method thereof provided by the present invention reduce the electric field concentration at the bottom of the trench gate by forming a second Schottky metal layer at the bottom of the trench, thereby improving the reliability of the device.
[0017] Other features and beneficial effects of the present invention will be described in the subsequent specification, and some of the technical features and beneficial effects can be obviously obtained from the specification, or can be understood by implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, some of the drawings in the following description are embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0019] Figure 1 is a schematic flowchart of a manufacturing method of a MOSFET device provided by an embodiment of the present invention; Figures 2 to 5 is a schematic structural diagram of each stage during the manufacturing process of a MOSFET device provided by an embodiment of the present invention.
[0020] Reference Numerals: 12 - Substrate; 14 - N-type drift region; 16 - Trench; 18 - P-type base region; 20 - N+ source region; 22 - P+ ohmic contact region; 24 - First Schottky metal layer; 26 - Oxide layer; 28 - Second Schottky metal layer; 30 - Polysilicon layer; 32 - Gate; 34 - Gate oxide layer; 36 - Drain; H1 - Distance from the oxide layer to the bottom of the trench; H2 - Depth of the trench. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them; the technical features designed in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0022] In the description of the present invention, it should be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, the term "comprising" and any deformation thereof mean "at least including".
[0023] Please refer to Figures 1 to 5 。 Figure 1 is a schematic flow chart of a method for manufacturing a MOSFET device provided by an embodiment of the present invention, Figures 2 to 5 is a schematic structural diagram of each stage in the manufacturing process of a MOSFET device provided by an embodiment of the present invention.
[0024] As shown in the figure, a method for manufacturing a MOSFET device provided by an embodiment of the present invention includes the following steps: S100: Grow an N-type drift region 14 on the substrate 12. The thickness range of the N-type drift region 14 is 5-15 μm.
[0025] S200: Etch the N-type drift region 14 to form a trench 16.
[0026] S300: Set a P-type base region 18 on the N-type drift region 14.
[0027] S400: Set an N+ source region 20 on the P-type base region 18.
[0028] S500: A P+ ohmic contact region 22 is disposed on the P-type base region 18, and the P+ ohmic contact region 22 is connected to the N+ source region 20.
[0029] S600: First, a first Schottky metal layer 24 is deposited on the surfaces of the N-type drift region 14, the P-type base region 18, the N+ source region 20, and the P+ ohmic contact region 22, and then the trench 16 is filled with an oxide layer 26, and the oxide layer 26 is located above the first Schottky metal layer 24. The material of the first Schottky metal layer 24 may include Ti, Mo, Pt, or Ni.
[0030] S700: The oxide layer 26 and the first Schottky metal layer 24 are etched so that the oxide layer 26 and the first Schottky metal layer 24 are lower than the P-type base region 18. This facilitates the subsequent formation of a via.
[0031] S800: A rapid thermal annealing process is performed to form a second Schottky metal layer 28 between the first Schottky metal layer 24 and the N-type drift region 14, and then the oxide layer 26 and the first Schottky metal layer 24 are etched away. The material of the second Schottky metal layer 28 includes metal silicide, which is formed by the reaction of Schottky metal and silicon in a high-temperature annealing environment. The metal silicide can form a depletion layer at the interface, generate a built-in electric field, reduce the electric field intensity at the bottom of the trench 16 gate, and improve the reliability of the device.
[0032] Further, the manufacturing method of the MOSFET device further includes the following steps: Deposit a polysilicon layer 30 in the trench 16, then oxidize the gate 32 to form a gate oxide layer 34, and then deposit polysilicon again to form the gate 32; Grow an interlayer dielectric layer on the surfaces of the gate oxide layer 34, the N+ source region 20, and the P+ ohmic contact region 22, then deposit Ni by photolithography and etching, form a contact region after annealing, and then deposit metal by photolithography and etching to form a source electrode.
[0033] Before depositing the first Schottky metal layer 24, a carbon film is first deposited on the surfaces of the N-type drift region 14, the P-type base region 18, the N+ source region 20, and the P+ ohmic contact region 22 as a protective layer, and then a high-temperature annealing process is performed at a temperature of 1800 - 2000 °C for a time of 10 min - 30 min, and the carbon film is removed after annealing. By this step, the surface morphology of the device can be protected and the increase in surface roughness can be suppressed. During the high-temperature activation annealing process of SiC ion implantation, the carbon film covers the wafer surface as a protective layer. By suppressing the sublimation and re-deposition processes of Si at the surface, the carbon film effectively prevents the degradation of the SiC surface morphology.
[0034] Combined Figures 2 to 5 Looking at it, first as Figure 2As shown, an N-type drift region 14 with a thickness of 10 μm and a doping concentration of 7×10 15 / cm 3 ~1.1×10 16 / cm 3 is grown on a substrate 12 of silicon carbide material. Then, a new mask is deposited according to the pattern of the trench 16, the trench 16 is etched to form, and then the surface mask is removed. Next, a new mask is deposited according to the pattern of the P-type base region 18, and Al ions with a dose of 4E12 are implanted to form the P-type base region 18. Then the surface mask is removed again. A new mask is deposited according to the pattern of the N+ source region 20, and N ions with a dose of 6E14 are implanted to form the N+ source region 20. After removing the surface mask again, a new mask is deposited according to the pattern of the P+ ohmic contact region 22, and Al ions with a dose of 8E14 are implanted to form the ohmic contact region, and then the surface mask is removed. A carbon film is deposited on the surface as a protective layer to reduce surface degradation caused by Si desorption and surface atom migration. Then, high-temperature annealing treatment is carried out at a temperature of 1800~2000 °C for a time of 10 min~30 min, and the carbon film is removed after annealing. Then, after depositing the first Schottky metal layer 24 on the surface, an oxide layer 26 is deposited to fill the trench 16.
[0035] As Figure 3 shown, the oxide layer 26 is etched back to 1 / 4 of the distance from the bottom of the trench 16. That is to say, the distance H1 from the etched-back oxide layer 26 to the bottom of the trench 16 accounts for 1 / 4 of the depth H2 of the trench 16. Then, the Schottky metal is wet-etched to 1 / 4 of the distance from the bottom of the trench 16.
[0036] As Figure 4 shown, rapid thermal annealing treatment is carried out under high temperature and nitrogen conditions to form a second Schottky metal layer 28 on the surface of the N-type drift region 14 of the silicon carbide for the first Schottky metal layer 24, and then the oxide layer 26 and the first Schottky metal layer 24 are etched and removed. The second Schottky metal layer 28 formed at this time is disposed on the sidewall and bottom of the trench 16, and the second Schottky metal layer 28 is continuous and complete, covering the bottom corner of the trench 16.
[0037] As Figure 5 shown, a polysilicon layer 30 is deposited in the trench 16, and the thickness of the polysilicon layer 30 accounts for about 1 / 4 of the depth H2 of the trench 16. Then, gate 32 oxidation is carried out to form a gate oxide layer 34, and then polysilicon deposition is carried out to form the gate 32. An interlayer dielectric layer (ILD) is grown on the surfaces of the gate oxide layer 34, the N+ source region 20, and the P+ ohmic contact region 22. Then, Ni is deposited through photolithography etching, and after annealing, a contact region (Contact) is formed. Then, metal deposition photolithography etching is carried out to form a source electrode. The finally formed cell region structure is as Figure 5 shown.
[0038] The passivation layer can be redeposited and passivation is formed by photolithography etching. After the front process is completed, the back surface is ground to the required thickness, and then polished, cleaned, evaporated, and alloyed to form the back metal as the drain 36.
[0039] The present invention also provides a MOSFET device, which is prepared by using the manufacturing method of the MOSFET device in any one of the foregoing.
[0040] In summary, for a MOSFET device and its manufacturing method provided by the present invention, by forming the second Schottky metal layer 28 at the bottom of the trench 16, the electric field concentration at the bottom of the gate of the trench 16 is reduced, and the reliability of the device is improved. Moreover, since the bottom of the gate 32 is the Schottky metal and the polysilicon layer 30, the Miller capacitance Cgd can be made smaller, increasing the switching speed.
[0041] In addition, those skilled in the art should understand that although there are many problems in the prior art, each embodiment or technical solution of the present invention can be improved only in one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or the background art at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be regarded as a limitation to that claim.
[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A manufacturing method of a MOSFET device, characterized in that: The manufacturing method of the MOSFET device includes the following steps: Growing an N-type drift region on a substrate; Etching the N-type drift region to form a trench; Setting a P-type base region on the N-type drift region; Setting an N+ source region on the P-type base region; Setting a P+ ohmic contact region on the P-type base region, and the P+ ohmic contact region is connected to the N+ source region; First depositing a first Schottky metal layer on the surfaces of the N-type drift region, the P-type base region, the N+ source region and the P+ ohmic contact region, and then filling the trench with an oxide layer, and the oxide layer is located above the first Schottky metal layer; Etching the oxide layer and the first Schottky metal layer to make the oxide layer and the first Schottky metal layer lower than the P-type base region; Performing a rapid thermal annealing process to form a second Schottky metal layer between the first Schottky metal layer and the N-type drift region, and then etching and removing the oxide layer and the first Schottky metal layer.
2. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The material of the first Schottky metal layer includes Ti, Mo, Pt or Ni.
3. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The manufacturing method of the MOSFET device further includes the following steps: Depositing a polysilicon layer in the trench, then performing gate oxidation to form a gate oxide layer, and then performing polysilicon deposition to form a gate; Growing an interlayer dielectric layer on the surfaces of the gate oxide layer, the N+ source region and the P+ ohmic contact region, then depositing Ni by photolithography etching, annealing to form a contact region, and then performing deposition metal photolithography etching to form a source electrode.
4. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The thickness range of the N-type drift region is 5-15 μm.
5. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The doping concentration range of the N-type drift region is 7×10 15 / cm 3 ~1.1×10 16 / cm 3 .
6. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The material of the substrate includes silicon carbide.
7. The manufacturing method of the MOSFET device according to claim 1, characterized in that: Before depositing the first Schottky metal layer, first depositing a carbon film on the surfaces of the N-type drift region, the P-type base region, the N+ source region and the P+ ohmic contact region as a protective layer, and then performing a high-temperature annealing process at a temperature of 1800-2000 °C for a time of 10 min-30 min, and removing the carbon film after annealing.
8. The manufacturing method of the MOSFET device according to claim 1, characterized in that: After etching the oxide layer and the first Schottky metal layer, the distance from the oxide layer to the bottom of the trench accounts for 1 / 4 of the depth of the trench.
9. The manufacturing method of the MOSFET device according to claim 1, characterized in that: The second Schottky metal layer is disposed on the sidewall and bottom of the trench.
10. A MOSFET device, characterized in that: The MOSFET device is prepared by using the manufacturing method of the MOSFET device according to any one of claims 1-9.