MOSFET transistor

Abstract

The invention relates to a MOSFET transistor. The present specification relates to a transistor including a channel region extending in a first direction between a drain region and a source region of a semiconductor layer; the gate structure is located on the top of the channel forming region, and the gate structure comprises a gate insulator with the top covered with a gate region; a channel formation region including a first epitaxial channel region having a first length in the first direction and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator includes a first portion having a first thickness on the second channel region on either side of the first channel region, and a second portion having a second thickness over the first channel region, the second thickness being less than the first thickness.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to French Application No. 2400490, filed on January 18, 2024, which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to electronic components and, more particularly, to field-effect transistors of the MOSFET (metal-oxide-semiconductor field-effect transistor) type. Background Art

[0004] A MOSFET-type transistor is a field-effect transistor that includes a conductive gate that is electrically insulated from a semiconductor substrate by a dielectric layer called a gate insulator.

[0005] Various MOSFET transistor designs have been provided.

[0006] It is desirable to at least partially overcome certain drawbacks of known MOSFET transistor designs.

[0007] Improvements in the electrical performance of MOSFET transistors, such as for applications in fields such as radio frequency (RF) signal switching, advanced analog, embedded non-volatile memory, etc. Summary of the Invention

[0008] One embodiment overcomes all or part of the drawbacks of known MOSFET transistors.

[0009] One embodiment provides a transistor that includes a drain region and a source region in a semiconductor layer; a channel formation region that extends in a first direction between the drain region and the source region; and a gate structure that is located on top of the channel formation region and includes a gate insulator with a gate region on top, the gate region being insulated from the channel formation region by the gate insulator; the channel formation region includes a first channel region that has a first length in the first direction and is an epitaxial region, and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator includes a first portion having a first thickness on each side of the first channel region, and a second portion having a second thickness above the first channel region, the second thickness being less than the first thickness.

[0010] According to one embodiment, the second portion is located between the first portions in the first direction.

[0011] According to one embodiment, the transistor further includes a lightly doped drain region in the semiconductor layer, located between the second channel region and each of the drain region and the source region.

[0012] One embodiment provides a method of manufacturing a transistor, the method comprising: forming a first insulator layer having a third thickness on a semiconductor layer; forming an opening in the first insulator layer, the opening having a first length in a first direction; epitaxially forming a first channel region of a channel formation region in the opening; forming a second insulator layer having a second thickness at least over the first channel region; a portion of the first insulator layer remaining on either side of the opening forms a first portion of a gate insulator, the first portion having a first thickness greater than or equal to the third thickness and greater than the second thickness, and a portion of the second insulator layer located on top of the first channel region forms a second portion of the gate insulator; forming a gate region on the gate insulator; and forming a drain region and a source region in the semiconductor layer, a second channel region of the channel formation region extending in the first direction between the drain region and the source region.

[0013] According to one embodiment, the method further comprises forming lightly doped drain regions in the semiconductor layer, between the second channel region and each of the drain region and the source region.

[0014] According to one embodiment, forming the opening includes etching the first insulator layer through the third thickness along the first length in the first direction, the etching stopping at the semiconductor layer, and the etching being, for example, wet etching.

[0015] According to one embodiment, the first thickness is substantially equal to the third thickness.

[0016] The following embodiments are applicable to transistors and transistor manufacturing methods.

[0017] According to one embodiment, the first thickness is in the range of 5 to 10 nm, such as 6 to 9 nm, and the second thickness is in the range of 1 to 4.5 nm, such as 2 to 4 nm.

[0018] According to one embodiment, the gate region has a second length in the first direction, the first length being less than the second length.

[0019] According to one embodiment, the gate region extends above and on either side of the first channel region in the first direction.

[0020] According to a particular embodiment, the gate region is centered with respect to the first channel region.

[0021] According to one embodiment, a non-zero distance separates the sidewall of the gate region and the second gate insulator portion, for example, the distance is in the range of 70 to 100 nm or 80 to 90 nm.

[0022] According to one embodiment, the distance is greater than the overlap length of the lightly doped drain region below the gate region.

[0023] According to one embodiment, the first epitaxial channel region is made of silicon.

[0024] According to another embodiment, the first epitaxial channel region is made of a silicon-germanium alloy.

[0025] According to one embodiment, the gate insulator is made of silicon oxide (e.g., silicon dioxide), and / or the semiconductor layer is made of silicon.

[0026] One embodiment provides an electronic device including at least one transistor as described above.

[0027] One embodiment provides a radio frequency switch including at least one transistor as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of the specific embodiments, which are illustrated by way of example and not limitation with reference to the accompanying drawings, in which:

[0029] Figure 1 An example of an electronic device including a MOSFET transistor is shown in a longitudinal cross-sectional view;

[0030] Figure 2A A longitudinal cross-sectional view of an electronic device including a MOSFET transistor according to one embodiment is shown;

[0031] Figure 2B Is shown in a top cross-sectional view Figure 2A of the electronic device;

[0032] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are longitudinal cross-sectional views that partially and schematically illustrate successive steps of an example method of manufacturing a MOSFET transistor similar to the Figure 2A transistor; and

[0033] Figure 4A and Figure 4B show curves representing drain current values as a function of gate voltage for a reference transistor and a transistor according to an embodiment. DETAILED DESCRIPTION

[0034] In the figures, like features are denoted by like reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0035] For clarity, only the steps and elements that contribute to an understanding of the described embodiments are shown and described in detail. In particular, the steps of the MOSFET transistor manufacturing method are not all described, as they can be performed with current microelectronic methods. Similarly, not all details of the MOSFET transistor are described. In addition, the applications of the described transistors may not all be detailed.

[0036] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected or may be coupled via one or more other elements.

[0037] In the following description, when referring to absolute position qualifiers such as "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as "top", "bottom", "upper", "lower", etc., or orientation qualifiers such as "horizontal", "vertical", etc., the orientation of the accompanying drawings is referred to unless otherwise stated.

[0038] Unless otherwise stated, the expressions "about", "approximately", "substantially", and "in the order of" mean plus or minus 10%, preferably plus or minus 5%.

[0039] In the following description, the length corresponds to the dimension in the first lateral direction (direction X indicated in the figure) of the MOSFET transistor, corresponding to the direction parallel to the conductive direction of the transistor, the width corresponds to the dimension in the second lateral direction (direction Y indicated in the figure) orthogonal to the first direction, and the thickness or depth corresponds to the dimension in the third direction (vertical direction Z indicated in the figure) perpendicular to the first and second directions. Thus, the dimension of the channel formation region of the transistor along the X direction is referred to as the transistor channel length, which substantially corresponds to the distance between the source region and the drain region of the transistor.

[0040] In the following description, the MOSFET may be designated as a transistor to make it lighter.

[0041] The transistor shown in the following description is, for example, an N-channel MOS transistor (NMOS), that is, a transistor having N-type doped source and drain regions (e.g., doped with arsenic or phosphorus atoms), while the body region is P-type doped (e.g., doped with boron atoms).

[0042] As a variant, the transistor shown may be a P-channel MOS transistor (PMOS), that is, a transistor having P-type doped source and drain regions (for example, doped with boron atoms), while the body region is N-type doped (for example, doped with arsenic or phosphorus atoms).

[0043] Figure 1 An example of an electronic device including a MOSFET transistor 100 is shown in a longitudinal cross-sectional view.

[0044] The MOSFET transistor 100 is formed inside and on top of a semiconductor layer 120. The electronic device includes a buried insulator layer 110 below the semiconductor layer 120. Layers 110 and 120 correspond to a stack of, for example, the SOI (semiconductor-on-insulator) type, and the electronic device includes a substrate (not shown) that contacts and is located below the buried insulator layer 110. The semiconductor layer 120 is, for example, on top of and in contact with the buried insulator layer 110.

[0045] The semiconductor layer 120 is made of, for example, silicon, for example, made of single-crystalline silicon, and the buried insulator layer 110 is made of, for example, silicon dioxide (SiO2).

[0046] The transistor 100 includes a drain region 121 and a source region 122 formed in a region of the semiconductor layer 120 called the body region 123.

[0047] The upper portion 124 of the body region 123 between the drain region 121 and the source region 122 forms the channel-forming region 124, or "channel region", of the transistor 100. For example, the drain region 121, the source region 122, and the body region 123 are flush with the upper surface of the semiconductor layer 120.

[0048] The transistor 100 further includes a gate structure 130 located above the body region 123, preferably above the channel region 124. The gate structure 130 typically includes a conductive gate region 132, which, for example, includes polysilicon and / or metal, and an insulator layer 131 called a gate insulator, which insulates the gate region 132 from the semiconductor layer 120.

[0049] For example, the length CD of the gate region 132 is greater than or equal to 50 nm, or even greater than or equal to 100 nm.

[0050] For example, the gate insulator 131 is made of silicon dioxide (SiO2).

[0051] For example, the thickness of the gate insulator 131 is about 1 nm to 10 nm. For a transistor called GO1 ("gate oxide 1"), that is, a transistor with a gate insulator of small thickness, the thickness of the gate insulator can be in the range of about 1 to 4.5 nm, or for a transistor GO2 ("gate oxide 2"), that is, a transistor with a gate insulator of strong thickness, its thickness is in the range of about 5 to 10 nm, or even in the range of about 5 to 7.5 nm.

[0052] For example, in Figure 1 , the gate insulator 131 is on top of and in contact with the semiconductor layer 120, and the gate region 132 is on top of and in contact with the gate insulator 131.

[0053] The gate region 132 may be covered with a conductive contact layer 133, which may be made of silicide. The drain region and the source region may also each be covered with a conductive contact layer 126, which may be made of silicide, which can, for example, reduce the access resistance.

[0054] On either side of the gate region 132, on the part of the semiconductor layer 120 not covered by the gate region, and on the sidewalls (sides) of the gate region 132, the transistor 100 generally includes a thin protective oxide layer 134, such as a SiO2 layer. The thickness of the thin oxide layer 134 is, for example, in the range of 2 to 10 nm, or even in the range of 2 to 5 nm.

[0055] In addition, the transistor 100 includes insulating spacers 135 that cover the sides of the gate region 132 covered by the thin oxide layer 134 and extend above the part of the semiconductor layer 120 covered by the thin oxide layer 134. Each insulating spacer 135 is made of, for example, silicon nitride (SiN).

[0056] An extension region 125 or an LDD (lightly doped drain) region may be formed at each junction between the channel region 124 and the drain region 121 and the source region 122, which is doped slightly less than the doping of the drain region and the source region, for example, to limit the lateral electric field in the MOS transistor.

[0057] The LDD region 125, and sometimes also the drain region 121 and the source region 122, generally exhibit an overlap under the gate region 132. In fact, during the doping operation for forming the LDD region 125 or even for forming the drain region 121 and the source region 122, the dopant may diffuse a certain length under the gate region. This overlap is in Figure 1It is represented by the overlap length Xj between the sidewall 132A of the gate region 132 and the inner edge of the LDD region 125 (this inner edge corresponds to the junction of the LDD region 125 and the channel region 124). This overlap reduces the effective length Leff of the channel formation region 124, and this effective length is substantially equal to the length CD of the gate region 132 minus twice the overlap length Xj. In addition, this overlap can form a parasitic overlap capacitance between the gate region and the LDD region, or even between the drain region and the source region, which can cause a reduction in transistor performance. Figure 1 The same overlap length Xj is shown on the drain region 121 side and the source region 122 side, but it is possible for this overlap to be unequal on both sides.

[0058] Although Figure 1 not shown in the figure, an etch stop layer, such as made of SiN (or SiN 34 ) and covered on top by a region called "PMD" (pre-metal dielectric) made of a dielectric material (which can be silicon dioxide (SiO2)) can be located on the transistor 100, and the contacts can pass through the etch stop layer and the PMD region all the way to the drain region, source region, and gate region of the transistor 100, for example, all the way to the conductive contact layers of these regions.

[0059] In some applications, better control of the overlap capacitance is sought, and the overlap capacitance can be expressed by the term "Miller capacitance". A reduction in these capacitances can be sought, especially to avoid too much deviation in the performance of MOSFET transistors. One solution to reduce the Miller capacitance is to increase the thickness of the gate insulator. However, thereby, all other conditions being the same, this can cause an increase in the threshold voltage of the transistor and reduce certain performances of the transistor, such as its switching speed.

[0060] The inventors provide a MOSFET transistor that can meet the above improvement requirements and overcome all or part of the above-mentioned disadvantages of MOSFET transistors. In particular, the inventors provide a MOSFET transistor that can reduce the overlap capacitance or Miller capacitance without reducing transistor performance, especially without increasing the threshold voltage of the transistor. It is desirable to have such a MOSFET transistor without complicating the transistor manufacturing method. For embodiments, it would be advantageous not to reduce the effective length of the channel formation region.

[0061] Embodiments of the MOSFET transistor will be described below. The described embodiments are non-limiting, and based on the indications of the present disclosure, those skilled in the art will think of various variations.

[0062] Figure 2AA longitudinal cross-sectional view of an electronic device including a MOSFET 200 according to one embodiment is shown. Figure 2B The MOSFET transistor 200 is shown in a top-down cross-sectional view Figure 2A thereof. Figure 2B The cross-sectional view thereof is obtained along the cross-section AA indicated in Figure 2A .

[0063] Figure 2A and Figure 2B The MOSFET transistor 200 of and Figure 1 differs from the MOSFET transistor 100 of mainly in that: the channel region 224 includes a first channel region 224A as an epitaxial region and a second channel region 224B in the semiconductor layer 120, and the second channel region can be similar to Figure 1 the channel region 124 of , the first channel region 224A is located between the second channel region 224B and the gate structure 230; the gate insulator 231 of the gate structure 230 includes a first portion 231A located on either side of the first channel region 224A and a second portion 231B located on the first channel region 224A.

[0064] The second channel region 224B extends below the first channel region 224A and partially extends below the first gate insulator portion 231A.

[0065] The gate insulator 231 can be made of silicon oxide (e.g., SiO2).

[0066] The first portion 231A of the gate insulator 231 has a first thickness e1, and the second portion 231B of the gate insulator 231 has a second thickness e2 smaller than the first thickness e1.

[0067] For example, the first portion 231A is of the GO2 type, and the second portion 231B is of the GO1 type.

[0068] For example, the first thickness e1 is in the range of 5 to 10 nm, or even in the range of 6 to 9 nm, and the second thickness e2 is in the range of 1 to 4.5 nm, or even in the range of 2 to 4 nm.

[0069] Preferably, the length L1 (first length) of the first channel region 224A is smaller than the length CD (second length) of the gate region 132, and the length of the first channel region substantially corresponds to the length of the second gate insulator portion 231B.

[0070] For example, the length L1 is in the range of 1 to 2.5 μm, for example, equal to about 1.8 μm.

[0071] The thickness of the first channel region 224A is preferably less than or equal to the first thickness e1. For example, the thickness of the first channel region 224A is in the range of 6 to 9 nm.

[0072] The first epitaxial channel region 224A may be made of silicon (Si). As a variant, the first epitaxial channel region 234A may be made of a silicon-germanium (SiGe) alloy, enabling a stressed channel region 224 to be obtained and increasing the charge mobility.

[0073] Preferably, the gate region 132 is located above the first channel region 224A or the second part 231B in the X direction and is suspended on either side thereof, such that the non-zero distance Ov separates the sidewall 132A of the gate region 132 from the second gate insulator part 231B. This distance Ov corresponds to the length by which the gate region 132 is separated from the semiconductor region 120 (in particular from the LDD region and from the drain and source regions) by the maximum thickness (first thickness e1) of the gate insulator, which maximum thickness corresponds to the thickness of the first gate insulator part 231A.

[0074] For example, the gate region 132 is centered with respect to the first channel region 224A and / or the second gate insulator part 231B.

[0075] Preferably, the distance Ov is greater than the overlap length Xj of the LDD region 125 and / or the drain region 121 and source region 122 below the gate region 132, such that this overlap occurs below the maximum gate insulator thickness (thickness e1). Thus, the overlap capacitance can be reduced.

[0076] Furthermore, since the gate insulator thickness (thickness e2) between the gate region 132 and the first channel region 224A is small, the threshold voltage can be reduced.

[0077] It should be noted that, in order to reduce the overlap capacitance, the overlap distance Xj can be reduced. A known solution is to form offset spacers on the sidewalls of the gate region 132 and on the thin protective oxide layer 134, enabling an offset to be provided during the formation of the LDD region 125 before the formation of the insulating spacers 135 and the drain region 121 and source region 122. Such offset spacers form a protective mask that continues the mask formed by the gate region 132 and the thin oxide layer 134 during the operation of doping the LDD region to limit the diffusion of dopants below the gate region. These embodiments can advantageously obviate the need for such offset spacers and, in particular, can simplify the manufacturing method.

[0078] For example, the overlap distance Xj is in the range of 40 to 80 nm, for example equal to approximately 60 nm.

[0079] For example, the distance Ov is in the range of 70 to 100 nm, for example 80 to 90 nm, for example equal to approximately 85 nm.

[0080] Figure 2A and Figure 2B shows the same overlap length Xj on the drain region 121 side and on the source region 122 side, but this overlap length may not be equal on both sides. Similarly, Figure 2A and Figure 2B shows the same distance Ov on the drain region 121 side and on the source region 122 side, but this distance may not be equal on both sides.

[0081] The inventors have determined that there is a step in the gate insulator 231 between the first part 231A and the second part 231B, which can modify the current path, particularly concentrating the current at the interface between the first channel region 224A and the second gate insulator part 231B, and the second gate insulator part 231B has a smaller thickness (thickness e2), which is beneficial to current conduction at this interface, thereby possibly reducing the transistor threshold voltage. In addition, as described above, due to the greater gate insulator thickness (thickness e1 of the first gate insulator part 231A), the overlap capacitance can be reduced. Therefore, the embodiment can reduce the overlap capacitance without increasing the threshold voltage, or even while reducing the threshold voltage.

[0082] The inventors have also determined that the embodiment can improve the long-term reliability of the transistor, particularly by reducing charge carrier phenomena.

[0083] In fact, the presence of the step in the gate insulator 231 can, in particular, modify the current path as described above, slow down the speed of the charge carriers, causing the charge carriers to stay in a limited region between each first gate insulator part 231A and each LDD region 125. Therefore, fewer charge carriers can accumulate between the gate structure 230 and each LDD region.

[0084] Figure 2A and Figure 2B Other characteristics of the MOSFET transistor 200 of Figure 1 are the same as those in Figure 1 and can be similar to the MOSFET transistor 100 in

[0085] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are longitudinal cross-sectional views, partially and schematically illustrating successive steps of an example of a method for manufacturing a MOSFET transistor similar to the transistor of Figure 2A .

[0086] Figure 3AShows an initial structure including a semiconductor layer 120. The initial structure may include a buried insulator layer in contact with and below the semiconductor layer 120, or even include a substrate (the substrate and the buried insulator layer are not shown) in contact with and below the buried insulator layer, corresponding to, for example, an SOI-type stack.

[0087] Figure 3A The structure further includes a first insulator layer 301 on top of the semiconductor layer 320. The first insulator layer 301 is intended to form a first gate insulator portion 231A and has a third thickness e3, which may be less than or equal to the first thickness e1.

[0088] The first insulator layer 301 may be formed by oxidizing the semiconductor layer 120. The first insulator layer 301 may be formed by oxidizing the semiconductor layer 120 at an initial thickness greater than the third thickness e3 (e.g., about 20 nm), and then removing a portion of that thickness to obtain the third thickness e3. For example, the semiconductor layer 120 is made of silicon and the first insulator layer 301 is made of silicon oxide (e.g., SiO2).

[0089] Furthermore, an etch mask 302 is formed on the first insulator layer 301. The etch mask 302 includes an opening 303 corresponding to a desired opening in the first insulator layer 301 in the next step.

[0090] Figure 3B Shows the structure obtained at the end of the step of etching the first insulator layer 301 through the etch mask 302. During this step, the first insulator layer 301 is etched from the upper surface of the first insulator layer 301, only the central portion of the first insulator layer 301 located below the opening 303 of the etch mask 302 is removed, an opening 304 is formed in the first insulator layer 301, and the portion of the first insulator layer 301 located below the etch mask 302 is retained to form all or part of the first gate insulator portion 231A.

[0091] The etching is preferably wet etching. For example, this etching step is carried out with hydrofluoric acid for a duration in the range of, for example, 150 to 400 seconds.

[0092] The etching stops at the semiconductor layer 120.

[0093] Then the etch mask 302 is removed.

[0094] Figure 3BIn the illustrated embodiment, a portion of the first insulator layer 301 remaining after etching forms a first gate insulator portion 231A, and the third thickness e3 is substantially equal to the first thickness e1. However, those skilled in the art can envision other embodiments. For example, the formation of the second gate insulator portion 231B described below can increase the thickness e3 of the second gate insulator portion 231A to obtain the first thickness e1.

[0095] Figure 3C Corresponding to the structure obtained when forming a semiconductor layer (e.g., made of silicon) in the opening 304 of the first insulator layer 301 by epitaxial growth, thereby forming a first channel region 224A.

[0096] A second channel region 224B is intended to be formed below the first channel region 224A.

[0097] The thickness of the first epitaxial channel region 224A is, for example, substantially equal to the third thickness e3. In this case, the first channel region 224A can be flush with the first gate insulator portion 231A. As a variant, the thickness of the first epitaxial channel region 224A can be less than the third thickness e3, for example, the first channel region 224A does not completely fill the opening 304.

[0098] Figure 3D The structure obtained when forming a second insulator layer with a thickness of e2 (second thickness) on the first channel region 224A is shown, corresponding to the second gate insulator portion 231B. The second thickness e2 is preferably less than the third thickness e3.

[0099] This second gate insulator portion 231B can be formed by oxidizing the first channel region 224A. For example, the first channel region 224A is made of silicon, and the second gate insulator portion 231B is made of silicon oxide (e.g., made of SiO2). On the first gate insulator portion 231A, oxidation can occur to a lesser extent, that is, generally more slowly, and thus across a thickness less than the second thickness e2. In this case, the thickness of the first gate insulator portion 231A can increase slightly during the oxidation to form the second gate insulator region 231B, such that the first thickness e1 is greater than the third thickness e3 and greater than the second thickness e2.

[0100] The second gate insulator portion 231B can be raised relative to the horizontal plane of the first portion 231A, as Figure 3D shown. As a variant, the second gate insulator portion 231B can be flush with the first portion 231A, as Figure 2A shown.

[0101] As a variant, the second gate insulator portion 231B can be formed by depositing a second insulator layer on the second channel region 224A and optionally also on the first gate insulator portion 231A.

[0102] For example, the third thickness e3 is in the range of 4.5 to 9.5 nm, the first thickness e1 is in the range of 5 to 10 nm, or even in the range of 6 to 9 nm, and the second thickness e2 is in the range of 1 to 4.5 nm, or even in the range of 2 to 4 nm.

[0103] Figure 3E Corresponding to a structure of the transistor 200 similar to Figure 2A obtained at the end of standard steps of forming a gate region 132 on the gate insulator 231, forming a protective oxide layer 134 on the sides of the gate region 132, forming LDD regions by doping the semiconductor layer 120 on either side of the gate region 132 covered with the oxide layer 134, forming insulating spacers 135 on the oxide layer 134, and then forming drain regions 121 and source regions 122 by doping the semiconductor layer 120 on either side of the gate region 132 covered with the insulating spacers 135.

[0104] During the formation of the gate structure 230, a stack of one or more layers of material(s) intended to form the gate region 132 can be deposited on the gate insulator 231, and thereafter, the stack is etched transversely according to the desired length CD of the gate region to form the gate region 132. This etching is preferably chosen such that the length CD is greater than the length L1 of the first channel region 224A. Preferably, the etching of the stack is chosen such that the gate region 132 is suspended on either side of the second gate insulator portion 231B at a non-zero distance Ov in the X direction. For example, the gate region 132 is centered with respect to the second portion 231B.

[0105] In Figure 3E the length CD of the gate region 132 is greater than Figure 2A the length CD, and the distance Ov is substantially the same. This can be simply achieved by increasing the opening 303 in the etching mask 302 to increase the length of the opening 304 in the first insulator layer 301. More generally, those skilled in the art will know how to modify the values of the length CD and the distance Ov by simply adjusting the manufacturing method.

[0106] For NMOS transistors, the source and drain regions and the LDD regions can be doped using an N-type dopant such as arsenic (As) or phosphorus (P). For PMOS transistors, the source region, the drain region, and the LDD regions can be doped using a P-type dopant such as boron (B).

[0107] Thus, the fabrication of the MOSFET transistor according to the embodiments can be carried out by implementing standard MOSFET transistor fabrication methods.

[0108] Figure 4A and Figure 4B shows curves of gate voltage versus drain current values for a reference transistor (similar to the transistor in Figure 1 ) and a transistor according to an embodiment (similar to the transistor in Figure 2A and Figure 2B ). Except for the gate insulator and the epitaxial channel region, the fabrication characteristics of the reference transistor and the transistor according to the embodiment are similar, in particular the lengths CD and Leff and the doping are similar.

[0109] Curves 401 and 403 correspond to the reference transistor. Curves 402 and 404 correspond to the transistor in Figure 2A and Figure 2B .

[0110] In Figure 4A , the current values are on a decimal scale, while in Figure 4B , the current values are on a logarithmic scale.

[0111] As can be seen from these curves, the embodiments are able to reduce the threshold voltage VT of the transistor, which is indicated by the horizontal arrow in Figure 4A . They are also able to increase the saturation current, which is indicated by the vertical arrow in Figure 4A . Thus, this can increase the transistor speed, such as the switching speed for applications such as switching of radio frequency (RF) signals.

[0112] A transistor according to an embodiment can be embedded in an electronic device, which may also include one or more reference transistors, that is, without a stepped gate insulator and without an epitaxial channel region under the step.

[0113] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0114] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A transistor, the transistor comprising: A drain region and a source region, disposed in a semiconductor layer; A channel formation region, extending in a first direction between the drain region and the source region, and A gate structure, disposed above the channel formation region and including a gate insulator having a gate region at the top, the gate region being insulated from the channel formation region by the gate insulator; The channel formation region includes A first channel region, having a first length in the first direction and being an epitaxial region, and A second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and The gate insulator includes a first portion having a first thickness on the second channel region on either side of the first channel region, and a second portion having a second thickness above the first channel region, the second thickness being less than the first thickness.

2. The transistor according to claim 1, wherein the second portion is located between the first portions in the first direction.

3. The transistor according to claim 1, further comprising a lightly doped drain region in the semiconductor layer, the lightly doped drain region being located between the second channel region and each of the drain region and the source region.

4. The transistor according to claim 1, wherein the first thickness is in the range of 5 to 10 nm, and the second thickness is in the range of 1 to 4.5 nm.

5. The transistor according to claim 1, wherein the gate region has a second length in the first direction, the first length being less than the second length.

6. The transistor according to claim 1, wherein the gate region extends above and on either side of the first channel region in a first direction.

7. The transistor according to claim 1, wherein an overlap distance separates a sidewall of the gate region and a sidewall of the first portion of the gate insulator.

8. The transistor according to claim 7, further comprising a lightly doped drain region in the semiconductor layer, the lightly doped drain region being located between the second channel region and each of the drain region and the source region, wherein the overlap distance is greater than an overlap length of the lightly doped drain region below the gate region.

9. The transistor according to claim 1, wherein the first channel region is made of silicon or a silicon-germanium alloy.

10. The transistor according to claim 1, wherein the gate insulator includes a silicon oxide layer, and the semiconductor layer includes a silicon layer.

11. An electronic device, comprising at least one transistor according to claim 1.

12. A radio frequency switch, comprising at least one transistor according to claim 1.

13. A method of manufacturing a transistor, comprising: Forming a first insulator layer having a third thickness on a semiconductor layer; Forming an opening in the first insulator layer, the opening having a first length in a first direction; Forming a first channel region of a channel formation region by epitaxy in the opening; Forming a second insulator layer having a second thickness above the first channel region; The portion of the first insulator layer that remains on the second channel region on either side of the opening forms a first part of the gate insulator, the first part having a first thickness that is greater than or equal to the third thickness and greater than the second thickness, and the portion of the second insulator layer that is directly above the first channel region forms a second part of the gate insulator; Forming a gate region on the gate insulator; And Forming a drain region and a source region in the semiconductor layer, with the second channel region of the channel formation region extending in the first direction between the drain region and the source region.

14. The method according to claim 13, further comprising forming a lightly doped drain region in the semiconductor layer between the second channel region and each of the drain region and the source region.

15. The method according to claim 13, wherein forming the opening includes etching the first insulator layer along the first length in the first direction and through the third thickness, the etching stopping at the semiconductor layer.

16. The method according to claim 13, wherein the first thickness is equal to the third thickness.

17. A method of manufacturing a transistor, the method comprising: Forming a first insulator layer above a semiconductor layer; Patterning the first insulator layer to form an opening in the first insulator layer and a remaining portion, the opening having a first length in a first direction; Epitaxially forming a first channel region of a channel formation region in the opening; Forming a second insulator layer above the first channel region; the remaining portion of the first insulator layer forms a first part of the gate insulator, the second insulator layer is thinner than the remaining portion, and the portion of the second insulator layer that is formed above the first channel region forms a second part of the gate insulator; Forming a gate region on the gate insulator; And Forming a drain region and a source region in the semiconductor layer, with the second channel region of the channel formation region extending in the first direction between the drain region and the source region.

18. The method according to claim 17, the method further comprising forming a lightly doped drain region in the semiconductor layer between the second channel region and each of the drain region and the source region.

19. The method according to claim 17, wherein the first channel region is made of a silicon-germanium alloy.

20. The method according to claim 17, wherein the gate region has a second length in the first direction, the first length being less than the second length.

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