Silicon carbide MOSFET device and electronic equipment

Abstract

According to the silicon carbide MOSFET device and the electronic equipment provided by the invention, the N + type 4H-SiC substrate with a large inclination angle is used as the epitaxial substrate, the conventional epitaxial growth of the N-type 4H-SiC drift layer can be realized, the periodic grooves are etched in the N-type 4H-SiC drift layer, and then the growth of the N-type 4H-SiC JFET layer is carried out, so that the performance of the silicon carbide MOSFET device is improved. In the growth process, the grooves induce atomic steps on the surface of the N-type 4H-SiC JFET layer with the inclination angle of 4 degrees to be combined to form a large-area atomic step beam, so that a large-area (0001) crystal face is obtained on the surface of the N-type 4H-SiC JFET layer, a high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal face, and finally the redundant atomic step beam is ground to be flat. And the device with the N-type 3C-SiC channel layer with high mobility, the N-type 4H-SiC JFET layer with high voltage resistance and the N-type 4H-SiC drift layer is obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a silicon carbide MOSFET device and an electronic device. Background Art

[0002] Silicon carbide (SiC) field effect transistors (MOSFETs) have significant advantages in power electronic systems, making them stand out among traditional silicon (Si) and wide bandgap semiconductors and being widely used as power electronic control switch structures. There are various crystal forms of SiC. For example, 3C and 4H are common and stable SiC crystal forms. However, due to the existence of natural acceptor-like deep-level defects in the channel region of commonly used 4H-SiC MOSFETs, the channel mobility is significantly reduced (usually less than 20 cm 2 / Vs), such that the proportion of the channel resistance in the overall device on-resistance is much greater than that of traditional silicon-based devices. Using 3C-SiC-based MOSFETs can reduce the acceptor-like deep-level defects in the channel, thereby obtaining MOSFETs with high channel mobility (greater than 150 cm 2 / Vs). However, since the bandgap of 3C-SiC is narrower than that of 4H-SiC (3C: 2.36, 4H: 3.26), its critical breakdown electric field is lower than that of 4H-SiC (3C: 1.3 MV / cm, 4H: 2.8 MV / cm). At the same drift region thickness, the breakdown voltage tolerated by 3C-SiC is lower.

[0003] Therefore, it is particularly important to provide a silicon carbide MOSFET device with a high-mobility and high-voltage-resistant channel. Summary of the Invention

[0004] Embodiments of the present disclosure provide a silicon carbide MOSFET device and an electronic device, realizing a MOSFET device that combines a 3C-SiC channel with high mobility and a 4H-SiC JFET region with high voltage resistance, which can effectively improve the channel mobility of the device, reduce the channel resistance, and thus reduce the specific on-resistance of the device.

[0005] A silicon carbide MOSFET device and an electronic device provided by embodiments of the present disclosure are specifically as follows: On the one hand, embodiments of the present disclosure provide a silicon carbide MOSFET device, including a cell structure, and the cell structure includes: An N+-type 4H-SiC substrate, and the first included angle between the [11-20] crystal axis of the N+-type 4H-SiC substrate and its thickness direction is 80° to 89°; An N-type 4H-SiC drift layer is located on one side of the N+-type 4H-SiC substrate. The surface of the N-type 4H-SiC drift layer away from the N+-type 4H-SiC substrate has periodically arranged grooves. The second included angle between the [11-20] crystal axis of the N+-type 4H-SiC substrate and the interface between the N-type 4H-SiC drift layer and the N+-type 4H-SiC substrate is 1° to 10°; An N-type 4H-SiC JFET layer is located on the side of the N-type 4H-SiC drift layer away from the N+-type 4H-SiC substrate. The side of the N-type 4H-SiC JFET layer close to the N+-type 4H-SiC substrate fills the grooves. The surface of the N-type 4H-SiC JFET layer away from the N+-type 4H-SiC substrate includes a plurality of (0001) crystal planes; An N-type 3C-SiC channel layer is located on the side of the N-type 4H-SiC JFET layer away from the N+-type 4H-SiC substrate. The surface of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate is a flat surface.

[0006] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the included angle between the (0001) crystal plane and the interface between the N-type 4H-SiC drift layer and the N+-type 4H-SiC substrate is the third included angle, and the third included angle is the same as the second included angle.

[0007] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the positive projection of the (0001) crystal plane on the N+-type 4H-SiC substrate overlaps with the positive projection of the groove on the N+-type 4H-SiC substrate.

[0008] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the thickness of the N-type 4H-SiC drift layer is 1 μm to 100 μm, and the doping concentration of the N-type 4H-SiC drift layer is 1×10 14 ~1×10 17 cm -3 。

[0009] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the depth of the groove is 1 nm to 1 μm, the width of the groove is 100 nm to 10 μm, and the spacing between adjacent grooves is 100 nm to 100 μm.

[0010] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the thickness of the N-type 4H-SiC JFET layer is 100 nm to 100 μm, and the doping concentration of the N-type 4H-SiC JFET layer is 1×10 14 ~1×10 19 cm -3 。

[0011] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the thickness at the minimum thickness of the N-type 3C-SiC channel layer is 10 nm to 5 μm, and the doping concentration of the N-type 3C-SiC channel layer is 1×10 14 ~1×10 19 cm -3 。

[0012] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, an N+-type well region is further included at the interface between the N-type 3C-SiC channel layer and the N-type 4H-SiC JFET layer.

[0013] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, it further includes: two P-type well regions located in and spaced apart from the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer, and the N-type 4H-SiC drift layer, and an N+-type source contact region and a P+-type source contact region arranged laterally and in contact with each other within the P-type well region; wherein, the P-type well region is located in the N-type 4H-SiC drift layer near the lower surface of the N+-type 4H-SiC substrate, the upper surface of the P-type well region far from the N+-type 4H-SiC substrate is flush with the upper surface of the N-type 3C-SiC channel layer far from the N+-type 4H-SiC substrate, and the P+-type source contact region is arranged near the side surface of the N-type 3C-SiC channel layer; It further includes: a gate dielectric layer located on the side of the N-type 3C-SiC channel layer far from the N+-type 4H-SiC substrate, a gate electrode located on the side of the gate dielectric layer far from the N+-type 4H-SiC substrate, and an isolation dielectric layer located on the side of the gate electrode far from the N+-type 4H-SiC substrate; wherein, the gate dielectric layer is in contact with the N-type 3C-SiC channel layer, the P-type well region, and a part of the N+-type source contact region, the gate electrode covers the gate dielectric layer, and the isolation dielectric layer wraps the gate electrode and the gate dielectric layer and is in contact with the N+-type source contact region; It further includes a source electrode located on the side of the isolation dielectric layer, the N+ source contact region, and the P+ source contact region away from the N+-type 4H-SiC substrate. The source electrode wraps the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region. It further includes a drain electrode located on the side of the N+-type 4H-SiC substrate away from the N--type 4H-SiC drift layer.

[0014] On the other hand, an embodiment of the present disclosure further provides an electronic device, including the above-mentioned silicon carbide MOSFET device provided by the embodiment of the present disclosure.

[0015] The beneficial effects of the present disclosure are as follows: A silicon carbide MOSFET device and an electronic device provided by an embodiment of the present disclosure adopt an N+-type 4H-SiC substrate with a first included angle of 80° to 89° between the [11-20] crystal axis and its thickness direction, such as a 4° inclined N+-type 4H-SiC substrate. Therefore, a longitudinal N--type 4H-SiC drift layer can be used as a breakdown voltage region, improving the area utilization rate of the device. Moreover, the present disclosure uses a large-inclination N+-type 4H-SiC substrate as an epitaxial substrate, which can realize the conventional epitaxial growth of an N--type 4H-SiC drift layer. By etching periodic grooves on the N--type 4H-SiC drift layer and then growing an N-type 4H-SiC JFET layer, the periodic grooves during this growth process can induce the atomic steps on the surface of the 4° inclined N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, so as to obtain a large-area (0001) crystal plane on the surface of the N-type 4H-SiC JFET layer. A high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the redundant atomic step bundle is polished flat by chemical mechanical polishing to obtain a 3C / 4H-SiC heterogeneous MOSFET device with a high-mobility N-type 3C-SiC channel layer (mobility up to 150 cm 2 / Vs), a high-breakdown voltage N-type 4H-SiC JFET layer, and an N--type 4H-SiC drift layer, which can reduce the on-resistance of the SiC MOSFET device. Description of the Drawings

[0016] Figure 1 It is a schematic structural diagram of a silicon carbide MOSFET device provided by an embodiment of the present disclosure; Figure 2 It is Figure 1 a partially enlarged schematic structural diagram of Figure 3 It is another schematic structural diagram of a silicon carbide MOSFET device provided by an embodiment of the present disclosure; Figure 4Flow chart of a preparation method for a silicon carbide MOSFET device provided by an embodiment of the present disclosure; Figure 5 Flow chart of another preparation method for a silicon carbide MOSFET device provided by an embodiment of the present disclosure; Figure 6 For Figure 1 Schematic diagram of a structure during the preparation of the silicon carbide MOSFET device shown; Figure 7 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 8 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 9 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 10 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 11 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 12 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 13 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 14 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 15 For Figure 1 Schematic diagram of another structure during the preparation of the silicon carbide MOSFET device shown; Figure 16 Schematic diagram of the formation of atomic step bundle A2 induced by groove U; Figure 17 Schematic diagram of 3D nucleation epitaxial growth and step-flow epitaxial growth. Detailed implementation manners

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are enlarged for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of idealized embodiments. As such, deviations from the shapes of the figures can be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features; sharp corners illustrated may be rounded, etc. Thus, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the exact shapes of the illustrated regions, do not reflect true proportions, and are intended only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals throughout the specification denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0018] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "comprising", "including", or similar terms mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" or similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "inner", "outer", "upper", "lower", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0019] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" another element or layer or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] Embodiments of the present disclosure provide a silicon carbide MOSFET device, including a cell structure, as Figure 1 and Figure 2 shown, Figure 2 is Figure 1 a schematic enlarged view of a partial structure thereof. The cell structure includes: An N+-type 4H-SiC substrate 1, the first included angle between the [11-20] crystal axis of the N+-type 4H-SiC substrate 1 and its thickness direction (vertical direction) is 80 to 89°, that is, the included angle θ between the [11-20] crystal axis of the N+-type 4H-SiC substrate 1 and the horizontal direction is 1 to 10°; for example, the N+-type 4H-SiC substrate 1 with an inclination angle of 4° is used in the present disclosure; An N-type 4H-SiC drift layer 2, located on one side of the N+-type 4H-SiC substrate 1, the surface of the N-type 4H-SiC drift layer 2 far from the N+-type 4H-SiC substrate 1 has periodically arranged grooves U, and the second included angle (i.e., the included angle θ) between the [11-20] crystal axis of the N+-type 4H-SiC substrate and the interface between the N-type 4H-SiC drift layer 2 and the N+-type 4H-SiC substrate 1 is 1 to 10°; for example, the periodically arranged grooves U can be arranged in an array; An N-type 4H-SiC JFET layer 3, located on the side of the N-type 4H-SiC drift layer 2 far from the N+-type 4H-SiC substrate 1, the side of the N-type 4H-SiC JFET layer 3 close to the N+-type 4H-SiC substrate 1 fills the grooves U, and the surface of the N-type 4H-SiC JFET layer 3 far from the N+-type 4H-SiC substrate 1 includes a plurality of (0001) crystal planes A1 (i.e., silicon planes), and the plurality of (0001) crystal planes A1 are separated by atomic step bundles A2; An N-type 3C-SiC channel layer 4, located on the side of the N-type 4H-SiC JFET layer 3 far from the N+-type 4H-SiC substrate 1, the surface of the N-type 3C-SiC channel layer 4 far from the N+-type 4H-SiC substrate 1 is a flat surface.

[0021] The above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure uses an N+-type 4H-SiC substrate with a first included angle of 80-89° between the [11-20] crystal axis and its thickness direction, such as a 4° inclined N+-type 4H-SiC substrate. Therefore, a longitudinal N-type 4H-SiC drift layer can be used as the breakdown voltage region, improving the area utilization rate of the device. Moreover, the present disclosure uses a large-inclination N+-type 4H-SiC substrate as the epitaxial substrate, which can achieve the conventional epitaxial growth of an N-type 4H-SiC drift layer. By etching periodic grooves on the N-type 4H-SiC drift layer and then growing an N-type 4H-SiC JFET layer, the periodic grooves during this growth process can induce the atomic steps on the surface of the 4° inclined N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, thereby obtaining a large-area (0001) crystal plane on the surface of the N-type 4H-SiC JFET layer. A high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the excess atomic step bundle is polished flat by chemical mechanical polishing to obtain a 3C / 4H-SiC heterogeneous MOSFET device with a high-mobility N-type 3C-SiC channel layer (mobility up to 150 cm 2 / Vs), a high-breakdown voltage N-type 4H-SiC JFET layer, and an N-type 4H-SiC drift layer, which can reduce the on-resistance of the SiC MOSFET device.

[0022] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 2 shown, the included angle between the (0001) crystal plane A1 of the N-type 4H-SiC JFET layer 3 and the interfaces of the N-type 4H-SiC drift layer 2 and the N+-type 4H-SiC substrate 1 is the third included angle, and the third included angle is the same as the second included angle θ. For example, the 4° inclined N+-type 4H-SiC substrate 1 used in the present disclosure is such that the included angle between the (0001) crystal plane A1 of the N-type 4H-SiC JFET layer 3 and the interfaces of the N-type 4H-SiC drift layer 2 and the N+-type 4H-SiC substrate 1 is 4°.

[0023] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 2 shown, the present disclosure etches periodic grooves U on the N-type 4H-SiC drift layer 2 and then grows the N-type 4H-SiC JFET layer 3. The periodic grooves U during this growth process can induce the atomic steps on the surface of the 4° inclined N-type 4H-SiC JFET layer 3 to merge to form a large-area atomic step bundle A2, thereby obtaining a large-area (0001) crystal plane. The orthographic projection of this (0001) crystal plane on the N+-type 4H-SiC substrate 1 overlaps with the orthographic projection of the groove U on the N+-type 4H-SiC substrate 1.

[0024] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 and Figure 2 shown, the thickness of the N-type 4H-SiC drift layer 2 can be 1 to 100 μm, such as 1 μm, 2 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc.; the doping concentration of the N-type 4H-SiC drift layer 2 can be 1×10 14 ~1×10 17 cm -3 , such as 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 etc.

[0025] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 2 shown, the depth of the groove U can be 1 nm to 1 μm, such as 1 nm, 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, etc.; the width of the groove U can be 100 nm to 10 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, etc.; the spacing between adjacent grooves U can be 100 nm to 100 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 10 μm, 50 μm, 100 μm, etc.

[0026] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 2 shown, the thickness of the N-type 4H-SiC JFET layer 3 can be 100 nm to 100 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, etc.; the doping concentration of the N-type 4H-SiC JFET layer 3 can be 1×10 14 ~1×10 19 cm -3 , such as 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18cm -3 , 1×10 19 cm -3 etc.

[0027] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 2 shown, at the minimum thickness of the N-type 3C-SiC channel layer 4 (i.e., the connection between the (0001) crystal plane A1 and the atomic step bundle A2), the thickness d can be 10 nm to 5 μm, such as 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.; the doping concentration of the N-type 3C-SiC channel layer 4 can be 1×10 14 ~1×10 19 cm -3 , such as 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 etc.

[0028] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, it further includes: two P-type well regions 5 located in and spaced apart from the N-type 3C-SiC channel layer 4, the N-type 4H-SiC JFET layer 3, and the N-type 4H-SiC drift layer 2, and an N+ source contact region 6 and a P+ source contact region 7 that are arranged horizontally and in contact with each other within the P-type well region 5; wherein, the P-type well region 5 is located in the N-type 4H-SiC drift layer 2 near the lower surface of the N+-type 4H-SiC substrate 1, the upper surface of the P-type well region 5 away from the N+-type 4H-SiC substrate 1 is flush with the upper surface of the N-type 3C-SiC channel layer 4 away from the N+-type 4H-SiC substrate 1, and the P+ source contact region 7 is arranged close to the side surface of the N-type 3C-SiC channel layer 4; specifically, the P-type well region 5, the N+ source contact region 6, and the P+ source contact region 7 are all formed by ion implantation on the upper surface of the N-type 3C-SiC channel layer 4, and the depth of ion implantation needs to be controlled for each region.

[0029] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1As shown, it further includes: a gate dielectric layer 8 on the side of the N-type 3C-SiC channel layer 4 away from the N+-type 4H-SiC substrate 1, a gate electrode 9 on the side of the gate dielectric layer 8 away from the N+-type 4H-SiC substrate 1, and an isolation dielectric layer 10 on the side of the gate electrode 9 away from the N+-type 4H-SiC substrate 1; wherein, the gate dielectric layer 8 is in contact with the N-type 3C-SiC channel layer 4, the P-type well region 5, and a part of the N+ source contact region 6, the gate electrode 9 covers the gate dielectric layer 8, and the isolation dielectric layer 10 wraps the gate electrode 9 and the gate dielectric layer 8 and is in contact with the N+ source contact region 6; specifically, the materials of the gate dielectric layer 8 and the isolation dielectric layer 10 can be dielectric materials such as silicon dioxide and silicon nitride; the material of the gate electrode 9 can be metals and their alloys such as titanium, aluminum, gold, silver, and copper, or conductive materials such as heavily doped polysilicon, titanium nitride, and indium tin oxide.

[0030] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, it further includes a source electrode 11 on the side of the isolation dielectric layer 10, the N+ source contact region 6, and the P+ source contact region 7 away from the N+-type 4H-SiC substrate 1. The source electrode 11 wraps the isolation dielectric layer 10 and is in contact with the N+ source contact region 6 and the P+ source contact region 7; specifically, the material of the source electrode 11 can be metals and their alloys such as titanium, aluminum, gold, silver, and copper, or conductive materials such as heavily doped polysilicon, titanium nitride, and indium tin oxide. Different cells in the active region of the device are interconnected through the source electrode 11 and interconnected with the gate electrode 9.

[0031] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, it further includes a drain electrode 12 on the side of the N+-type 4H-SiC substrate 1 away from the N-type 4H-SiC drift layer 2. The material of the drain electrode 12 can be metals and their alloys such as nickel, aluminum, titanium, and tungsten.

[0032] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, the N-type 4H-SiC JFET layer 3 takes the side part wrapping the P-type well region 5 as an example. Of course, the N-type 4H-SiC JFET layer 3 can also completely wrap the P-type well region 5.

[0033] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, when the device operates, electrons first flow through the N+ source contact region 6 from the source electrode 11, and then enter the N-type 4H-SiC JFET layer 3 and the N-type 4H-SiC drift layer 2 through the N-type channel induced by the gate electrode 9 in the N-type 3C-SiC channel layer 4 and the P-type well region 5, and finally reach the drain electrode 12 to form a current.

[0034] The above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure uses a MOSFET configuration, which can achieve normally-off operation and meet the requirements of power devices for power-off safety shutdown; and the present disclosure uses a P-type well region 5, an N-type 4H-SiC JFET layer 3 and an N-type 4H-SiC drift layer 2 as a voltage-resistant structure, which has avalanche breakdown ability in the reverse bias state, improving the reliability of the device.

[0035] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 1 shown, due to the difference in the energy band gap between 3C-SiC and 4H-SiC, there is a heterojunction barrier at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3; in order to reduce this heterojunction barrier, as Figure 3 shown, Figure 3 is another silicon carbide MOSFET device structure provided by the embodiments of the present disclosure, Figure 3 is basically the same as the structure of Figure 1 , the difference is that Figure 3 further includes an N+-type well region 13 located at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3, and the N+-type well region 13 can reduce or eliminate the influence of the heterojunction barrier. Specifically, when the present disclosure forms the P-type well region 5, the N+ source contact region 6 and the P+ source contact region 7 by ion implantation, the N+-type well region 13 is simultaneously formed by ion implantation at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3.

[0036] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the planar structure of the cell structure can be strip-shaped, rectangular or hexagonal, etc. After the gate electrode and the source electrode are completed, the device can be formed into a complete device by forming different cells such as strip cells, square cells, hexagonal cells, etc. The embodiments of the present disclosure Figure 1 and Figure 3 take the planar structure of the cell structure as a rectangle as an example.

[0037] Based on the same inventive concept, the embodiments of the present disclosure provide a preparation method of the above-mentioned silicon carbide MOSFET device. Since the principle of solving problems by this preparation method is similar to that of the above-mentioned silicon carbide MOSFET device, therefore, the implementation of the preparation method provided by the embodiments of the present disclosure can refer to the implementation of the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0038] In some embodiments, the preparation method of the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, as Figure 4As shown, it may include: S401. Epitaxially grow an N-type 4H-SiC drift layer on one side of an N+-type 4H-SiC substrate by using step-flow epitaxy; S402. Pattern the surface of the N-type 4H-SiC drift layer away from the N+-type 4H-SiC substrate to form periodically arranged grooves; S403. Clean the wafer surface of the N-type 4H-SiC drift layer, and then epitaxially grow an N-type 4H-SiC JFET layer on the side of the N-type 4H-SiC drift layer away from the N+-type 4H-SiC substrate by using step-flow epitaxy; S404. Epitaxially grow an N-type 3C-SiC channel layer on the side of the N-type 4H-SiC JFET layer away from the N+-type 4H-SiC substrate by using 3D nucleation epitaxy; S405. Polish the surface of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate by chemical mechanical polishing.

[0039] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, as Figure 5 shown, it further includes: S501. Perform ion implantation in the N-type 3C-SiC channel layer, N-type 4H-SiC JFET layer, and N-type 4H-SiC drift layer to form a P-type well region, an N+ source contact region, and a P+ source contact region; S502. Sequentially form a gate dielectric layer, a gate electrode, and an isolation dielectric layer on the side of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate; S503. Form a source electrode on the side of the gate dielectric layer away from the N+-type 4H-SiC substrate, and the source electrode wraps the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region; S504. Form a drain electrode on the side of the N+-type 4H-SiC substrate away from the N-type 4H-SiC drift layer.

[0040] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, when performing ion implantation in the N-type 3C-SiC channel layer, N-type 4H-SiC JFET layer, and N-type 4H-SiC drift layer in step S501, it further includes: injecting N-type ions at the interface between the N-type 3C-SiC channel layer and the N-type 4H-SiC JFET layer to form an N+-type well region.

[0041] To better understand the above preparation method provided by the embodiments of the present disclosure, the present disclosure takes the Figure 1 shown silicon carbide MOSFET device as an example to detail the preparation process of the silicon carbide MOSFET device.

[0042] In some embodiments, Figure 1 the preparation process of the shown silicon carbide MOSFET device may specifically include the following steps: (1) As shown in Figure 6 , epitaxially grow an N-type 4H-SiC drift layer 2 on one side of the N+-type 4H-SiC substrate 1 by step-flow epitaxy. Preferably, the thickness of the N-type 4H-SiC drift layer 2 can be 1 to 100 μm, such as 1 μm, 2 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc.; the doping concentration of the N-type 4H-SiC drift layer 2 can be 1×10 14 ~1×10 17 cm -3 , such as 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , etc. Preferably, the inclination angle θ between the [11-20] crystal axis of the N+-type 4H-SiC substrate 1 and the tangent of the wafer surface is 1 to 10°, such as 4°.

[0043] (2) As shown in Figure 7 , perform photolithographic masking on the surface of the N-type 4H-SiC drift layer 2 away from the N+-type 4H-SiC substrate 1, and then perform plasma etching to form periodically arranged grooves U. Preferably, the depth of the grooves U can be 1 nm to 1 μm, such as 1 nm, 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, etc.; the width of the grooves U can be 100 nm to 10 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, etc.; the spacing between adjacent grooves U can be 100 nm to 100 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 10 μm, 50 μm, 100 μm, etc.

[0044] (3) As shown in Figure 8As shown, after etching the groove U, the wafer surface of the N-type 4H-SiC drift layer is thoroughly cleaned, and then the N-type 4H-SiC JFET layer 3 is epitaxially grown on the side of the N-type 4H-SiC drift layer away from the N+-type 4H-SiC substrate 1 again by the step-flow epitaxy method. Due to the presence of the periodic groove U, the atomic steps on the surface of the 4°-tilted N-type 4H-SiC JFET layer 3 epitaxially grown by the step-flow epitaxy method will be induced to merge during the growth process, thereby forming an atomic step bundle A2. The method for the groove U to induce the formation of the atomic step bundle A2 is as Figure 16 shown. The formation of the atomic step bundle A2 will generate a large area of (0001) crystal plane A1, and the width of these (0001) crystal planes A1 is related to the thickness of the epitaxial growth, the pitch of the periodic groove U, the width and depth of the groove U. Preferably, the thickness of the N-type 4H-SiC JFET layer 3 can be 100 nm to 100 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, etc.; the doping concentration of the N-type 4H-SiC JFET layer 3 can be 1×10 14 ~1×10 19 cm -3 ,for example 1×10 14 cm -3 ,1×10 15 cm -3 ,1×10 16 cm -3 ,1×10 17 cm -3 ,1×10 18 cm -3 ,1×10 19 cm -3 etc.

[0045] (4)As Figure 9 shown, the N-type 3C-SiC channel layer 4 is epitaxially grown on the side of the N-type 4H-SiC JFET layer away from the N+-type 4H-SiC substrate (i.e., on the large area of (0001) crystal plane A1 that has been formed) by the 3D nucleation epitaxy method. The difference between the growth by the 3D nucleation epitaxy method and the growth by the step-flow epitaxy method is as Figure 17 shown. Preferably, the thickness of the N-type 3C-SiC channel layer 4 can be between 50 nm and 5 μm, such as 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.; the doping concentration of the N-type 3C-SiC channel layer 4 can be 1×10 14 ~1×10 19 cm -3 ,for example 1×10 14 cm -3 ,1×1015 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 etc.

[0046] (5) As shown in Figure 10 , by chemical mechanical polishing, the macroscopic steps on the surface of the N-type 3C-SiC channel layer 4 away from the N+-type 4H-SiC substrate 1 are polished to obtain a flat surface of the N-type 3C-SiC channel layer 4. Preferably, the thickness d at the thinnest part of the polished N-type 3C-SiC channel layer 4 (i.e., the connection of the (0001) crystal plane A1 and the atomic step bundle A2) can be 10 nm to 5 μm, such as 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.

[0047] (6) As shown in Figure 11 , Figure 11 and Figure 10 have the same structure. As shown in Figure 12 , multiple photolithographic masks and ion implantations are performed in the N-type 3C-SiC channel layer 4, the N-type 4H-SiC JFET layer 3, and the N-type 4H-SiC drift layer 2 to form the P-type well region 5, the N+ source contact region 6, and the P+ source contact region 7. Preferably, the ion implantation depth of the P-type well region 5 is between 1 μm and 5 μm, such as 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc., and the doping concentration is between 1×10 14 cm -3 and 1×10 19 cm -3 , such as 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 etc. Preferably, the ion implantation depth of the N+ source contact region 6 is between 100 nm and 1 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration is between 1×10 18cm -3 to 1×10 21 cm -3 Between, for example 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 Preferably, the ion implantation depth of the P+ source contact region 7 is between 100 nm and 1 μm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration is between 1×10 18 cm -3 to 1×10 21 cm -3 Between, for example 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 wait.

[0048] (7) Figure 13 As shown, in Figure 12 Gate oxide is deposited on the implanted epitaxial layer to form a gate dielectric layer 8 , and then gate metal material is deposited and etched to form a gate electrode 9 . The orthographic projection of the gate electrode 9 on the N+ type 4H-SiC substrate 1 partially overlaps with the N+ source contact region 6 . Preferably, the thickness of the gate dielectric layer 8 is between 10nm and 1μm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, etc.; the thickness of the gate electrode 9 is between 10nm and 10μm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0049] (8) Figure 14As shown, dielectric deposition is performed on the gate electrode 9 to form the isolation dielectric layer 10. Preferably, the thickness of the isolation dielectric layer 10 is between 10 nm and 10 μm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0050] (9) As Figure 15 shown, the isolation dielectric layer 10 and the gate dielectric layer 8 are etched to form a source electrode contact window V in the regions corresponding to the N+ source contact region 6 and the P+ source contact region 7.

[0051] (10) Source electrode metal deposition and drain electrode metal deposition are performed. After ohmic contact annealing, the source electrode 11 and the drain electrode 12 are formed. As Figure 1 shown, the device fabrication is completed.

[0052] Through the above steps (1)-(10), the Figure 1 silicon carbide MOSFET device shown is formed.

[0053] It should be noted that in the above fabrication method provided by the embodiments of the present disclosure, the lithography processes involved in forming each layer structure may not only include some or all of the process steps such as deposition, photoresist coating, mask plate masking, exposure, development, etching, photoresist stripping, etc., but may also include other process steps, which are specifically subject to the patterns required in the actual fabrication process and are not limited herein. For example, a post-bake process may be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, which is not limited herein; the mask plate used in the masking process may be a half-tone mask plate (Half Tone Mask), a single-slit mask plate (Single Slit Mask), or a gray-tone mask plate (Gray Tone Mask), which is not limited herein; the etching may be dry etching or wet etching, which is not limited herein.

[0054] Based on the same inventive concept, the embodiments of the present disclosure provide an electronic device including the silicon carbide MOSFET device provided by the embodiments of the present disclosure. Since the principle of solving problems of this electronic device is similar to that of the above silicon carbide MOSFET device, therefore, the implementation of this electronic device provided by the embodiments of the present disclosure can refer to the implementation of the above silicon carbide MOSFET device provided by the embodiments of the present disclosure, and the repeated parts will not be elaborated herein.

[0055] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, home appliances, etc. Of course, in addition to including silicon carbide MOSFET devices, the electronic devices provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it further includes structures such as a transmitter, an antenna, and a receiver; when the electronic device is a mixer, it further includes structures such as an input port and an output port.

[0056] A silicon carbide MOSFET device and an electronic device provided by the embodiments of the present disclosure employ an N+-type 4H-SiC substrate with a first angle of 80 to 89° between the [11-20] crystal axis and its thickness direction, such as a 4° inclined N+-type 4H-SiC substrate. Therefore, a longitudinal N-type 4H-SiC drift layer can be used as a breakdown voltage region, improving the area utilization rate of the device. Moreover, the present disclosure uses a large-inclination N+-type 4H-SiC substrate as an epitaxial substrate, enabling the conventional epitaxial growth of an N-type 4H-SiC drift layer. By etching periodic grooves in the N-type 4H-SiC drift layer and then growing an N-type 4H-SiC JFET layer, the periodic grooves during this growth process can induce the atomic steps on the surface of the 4° inclined N-type 4H-SiC JFET layer to merge and form a large-area atomic step bundle, thereby obtaining a large-area (0001) crystal plane on the surface of the N-type 4H-SiC JFET layer. A high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the excess atomic step bundle is polished flat by chemical mechanical polishing to obtain a 3C / 4H-SiC heterogeneous MOSFET device with a high-mobility N-type 3C-SiC channel layer (mobility up to 150 cm 2 / Vs), a high-breakdown voltage N-type 4H-SiC JFET layer, and an N-type 4H-SiC drift layer, which can achieve a reduction in the on-resistance of the SiC MOSFET device.

[0057] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0058] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A silicon carbide MOSFET device, characterized in that, It includes a cell structure, and the cell structure includes: An N+-type 4H-SiC substrate, and a first included angle between the [11-20] crystal axis of the N+-type 4H-SiC substrate and its thickness direction is 80° to 89°; An N-type 4H-SiC drift layer, which is located on one side of the N+-type 4H-SiC substrate. The surface of the N-type 4H-SiC drift layer far from the N+-type 4H-SiC substrate has periodically arranged grooves. A second included angle between the [11-20] crystal axis of the N+-type 4H-SiC substrate and the interface between the N-type 4H-SiC drift layer and the N+-type 4H-SiC substrate is 1° to 10°; An N-type 4H-SiC JFET layer, which is located on the side of the N-type 4H-SiC drift layer far from the N+-type 4H-SiC substrate. The N-type 4H-SiC JFET layer fills the grooves on the side close to the N+-type 4H-SiC substrate. The surface of the N-type 4H-SiC JFET layer far from the N+-type 4H-SiC substrate includes a plurality of (0001) crystal planes; An N-type 3C-SiC channel layer, which is located on the side of the N-type 4H-SiC JFET layer far from the N+-type 4H-SiC substrate. The surface of the N-type 3C-SiC channel layer far from the N+-type 4H-SiC substrate is a flat surface.

2. The silicon carbide MOSFET device according to claim 1, wherein An included angle between the (0001) crystal plane and the interface between the N-type 4H-SiC drift layer and the N+-type 4H-SiC substrate is a third included angle, and the third included angle is the same as the second included angle.

3. The silicon carbide MOSFET device according to claim 1, characterized in that, The positive projection of the (0001) crystal plane on the N+-type 4H-SiC substrate overlaps with the positive projection of the groove on the N+-type 4H-SiC substrate.

4. The silicon carbide MOSFET device according to claim 1, wherein The thickness of the N-type 4H-SiC drift layer is 1 to 100 μm, and the doping concentration of the N-type 4H-SiC drift layer is 1×10 14 ~1×10 17 cm -3 .

5. The silicon carbide MOSFET device according to claim 1, wherein The depth of the groove is 1 nm to 1 μm, the width of the groove is 100 nm to 10 μm, and the spacing between adjacent grooves is 100 nm to 100 μm.

6. The silicon carbide MOSFET device according to claim 1, wherein The thickness of the N-type 4H-SiC JFET layer is 100 nm to 100 μm, and the doping concentration of the N-type 4H-SiC JFET layer is 1×10 14 ~1×10 19 cm -3 .

7. The silicon carbide MOSFET device according to claim 1, characterized in that, The thickness at the minimum thickness of the N-type 3C-SiC channel layer is 10 nm to 5 μm, and the doping concentration of the N-type 3C-SiC channel layer is 1×10 14 ~1×10 19 cm -3 .

8. The silicon carbide MOSFET device according to claim 1, characterized in that, It further includes an N+-type well region located at the interface between the N-type 3C-SiC channel layer and the N-type 4H-SiC JFET layer.

9. The silicon carbide MOSFET device according to any one of claims 1-8, characterized in that, It further includes: two P-type well regions that are located in and spaced apart from the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer, and the N-type 4H-SiC drift layer, and an N+-type source contact region and a P+-type source contact region that are arranged horizontally and in contact with each other in the P-type well region; wherein, the lower surface of the P-type well region close to the N+-type 4H-SiC substrate is located in the N-type 4H-SiC drift layer, the upper surface of the P-type well region far from the N+-type 4H-SiC substrate is flush with the upper surface of the N-type 3C-SiC channel layer far from the N+-type 4H-SiC substrate, and the P+-type source contact region is arranged on the side close to the N-type 3C-SiC channel layer; It further includes: a gate dielectric layer located on the side of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate, a gate electrode located on the side of the gate dielectric layer away from the N+-type 4H-SiC substrate, and an isolation dielectric layer located on the side of the gate electrode away from the N+-type 4H-SiC substrate; wherein, the gate dielectric layer contacts the N-type 3C-SiC channel layer, the P-type well region, and a part of the N+ source contact region, the gate electrode covers the gate dielectric layer, and the isolation dielectric layer wraps the gate electrode and the gate dielectric layer and contacts the N+ source contact region; It further includes a source electrode located on the side of the isolation dielectric layer, the N+ source contact region, and the P+ source contact region away from the N+-type 4H-SiC substrate, the source electrode wraps the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region; It further includes a drain electrode located on the side of the N+-type 4H-SiC substrate away from the N-type 4H-SiC drift layer.

10. An electronic device, characterized in that, It includes the silicon carbide MOSFET device according to any one of claims 1-9.

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