Silicon carbide MOSFET device and electronic equipment

Abstract

The present disclosure provides a silicon carbide MOSFET device and electronic device. A large-tilt N+-type 4H-SiC substrate is used as an epitaxial substrate to achieve conventional epitaxial growth of an N-type 4H-SiC drift layer. Periodic grooves are etched into the N-type 4H-SiC drift layer, followed by growth of an N-type 4H-SiC JFET layer. During this growth process, the grooves induce atomic steps on the surface of the 4°-tilt N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, thereby obtaining a large-area (0001) crystal plane on the surface of the N-type 4H-SiC JFET layer. A high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, excess atomic step bundles are smoothed to obtain a device having a high-mobility N-type 3C-SiC channel layer, a high-voltage N-type 4H-SiC JFET layer, and an N-type 4H-SiC drift layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device and electronic equipment. Background Art

[0002] Silicon carbide (SiC) field-effect transistors (MOSFETs) have significant advantages in power electronic systems, making them stand out from traditional silicon (Si) and wide-bandgap semiconductors and widely used as power electronic switch structures. SiC has multiple crystal forms, such as 3C and 4H, which are common and stable SiC crystal forms. However, the channel region of the commonly used 4H-SiC MOSFET has a natural acceptor-like deep energy level defect, which leads to a significant reduction in channel mobility (usually less than 20cm 2 / Vs), making the proportion of channel resistance to the overall device on-resistance much greater than that of traditional silicon-based devices. Using 3C-SiC-based MOSFETs can reduce the acceptor-like deep energy level defects in the channel, thereby obtaining MOSFETs with high channel mobility (greater than 150cm 2 / Vs). However, since the band gap of 3C-SiC is narrower than that of 4H-SiC (3C: 2.36, 4H: 3.26), its critical breakdown electric field is lower than that of 4H-SiC (3C: 1.3MV / cm, 4H: 2.8MV / cm). Under the same drift region thickness, 3C-SiC has a lower withstand voltage.

[0003] Therefore, it is particularly important to provide a silicon carbide MOSFET device with high mobility and high voltage withstand channel. Summary of the Invention

[0004] The embodiments of the present disclosure provide a silicon carbide MOSFET device and electronic device, realizing a MOSFET device having a high-mobility 3C-SiC channel combined with a high-voltage 4H-SiC JFET region, which can effectively improve the device channel mobility, reduce the channel resistance, and thus reduce the device's specific on-resistance.

[0005] The embodiments of the present disclosure provide a silicon carbide MOSFET device and an electronic device, the specific solutions of which are as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a silicon carbide MOSFET device, comprising a cellular structure, wherein the cellular structure comprises:

[0007] An N+ type 4H-SiC substrate, wherein a first angle between an [11-20] crystal axis and a thickness direction of the N+ type 4H-SiC substrate is 80-89°;

[0008] An N-type 4H-SiC drift layer is located on one side of the N+ type 4H-SiC substrate, wherein a surface of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate has periodically arranged grooves, and a second angle between an [11-20] crystal axis of the N+ type 4H-SiC substrate and an interface between the N-type 4H-SiC drift layer and the N+ type 4H-SiC substrate is 1-10°;

[0009] An N-type 4H-SiC JFET layer is located on a side of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate, a side of the N-type 4H-SiC JFET layer close to the N+ type 4H-SiC substrate fills the groove, and a surface of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate includes multiple (0001) crystal planes;

[0010] The N-type 3C-SiC channel layer is located on a side of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate, and the surface of the N-type 3C-SiC channel layer away from the N+ type 4H-SiC substrate is a flat surface.

[0011] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the angle between the (0001) crystal plane and the interface between the N-type 4H-SiC drift layer and the N+ type 4H-SiC substrate is a third angle, and the third angle is the same as the second angle.

[0012] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided by the embodiments of the present disclosure, the orthographic projection of the (0001) crystal plane on the N+ type 4H-SiC substrate and the orthographic projection of the groove on the N+ type 4H-SiC substrate overlap with each other.

[0013] In some embodiments, in the silicon carbide MOSFET device provided in the embodiments of the present disclosure, the thickness of the N-type 4H-SiC drift layer is 1-100 μm, and the doping concentration of the N-type 4H-SiC drift layer is 1×10 14 ~1×10 17 cm -3 .

[0014] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, the depth of the groove is 1 nm~1 μm, the width of the groove is 100 nm~10 μm, and the spacing between adjacent grooves is 100 nm~100 μm.

[0015] In some embodiments, in the silicon carbide MOSFET device provided in the embodiments of the present disclosure, the thickness of the N-type 4H-SiC JFET layer is 100 nm to 100 μm, and the doping concentration of the N-type 4H-SiC JFET layer is 1×10 14 ~1×10 19 cm -3 .

[0016] In some embodiments, in the silicon carbide MOSFET device provided in the embodiments of the present disclosure, the thickness of the N-type 3C-SiC channel layer at its minimum thickness is 10 nm to 5 μm, and the doping concentration of the N-type 3C-SiC channel layer is 1×10 14 ~1×10 19 cm -3 .

[0017] In some embodiments, the silicon carbide MOSFET device provided in the embodiments of the present disclosure further includes an N+ type well region located at the interface between the N-type 3C-SiC channel layer and the N-type 4H-SiC JFET layer.

[0018] In some embodiments, the silicon carbide MOSFET device provided in the embodiments of the present disclosure further includes: two P-type well regions located in and spaced apart from each other in the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer, and the N-type 4H-SiC drift layer, and an N+ source contact region and a P+ source contact region located in the P-type well region and laterally arranged and contacting each other; wherein the P-type well region is located in the N-type 4H-SiC drift layer near the lower surface of the N+ 4H-SiC substrate, the upper surface of the P-type well region away from the N+ 4H-SiC substrate is flush with the upper surface of the N-type 3C-SiC channel layer away from the N+ 4H-SiC substrate, and the P+ source contact region is located near the side of the N-type 3C-SiC channel layer;

[0019] The present invention also includes: a gate dielectric layer located on a side of the N-type 3C-SiC channel layer away from the N+ type 4H-SiC substrate, a gate electrode located on a side of the gate dielectric layer away from the N+ type 4H-SiC substrate, and an isolation dielectric layer located on a side of the gate electrode away from the N+ type 4H-SiC substrate; wherein the gate dielectric layer contacts the N-type 3C-SiC channel layer, the P-type well region, and a portion of the N+ source contact region, the gate electrode covers the gate dielectric layer, and the isolation dielectric layer wraps the gate electrode and the gate dielectric layer and contacts the N+ source contact region;

[0020] It also includes a source electrode located on a side of the isolation dielectric layer, the N+ source contact region, and the P+ source contact region away from the N+ type 4H-SiC substrate, wherein the source electrode wraps the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region;

[0021] The device further includes a drain electrode located on a side of the N+ type 4H-SiC substrate away from the N- type 4H-SiC drift layer.

[0022] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned silicon carbide MOSFET device provided by an embodiment of the present disclosure.

[0023] The beneficial effects of the present disclosure are as follows:

[0024] The embodiments of the present disclosure provide a silicon carbide MOSFET device and an electronic device, which use an N+ type 4H-SiC substrate with a first angle of 80-89° between the [11-20] crystal axis and its thickness direction, such as a 4° tilt N+ type 4H-SiC substrate. Therefore, a longitudinal N-type 4H-SiC drift layer can be used as a voltage-resistant region, thereby improving the area utilization of the device. In addition, the present disclosure uses a large tilt N+ type 4H-SiC substrate as an epitaxial substrate, which can realize conventional epitaxial growth of an N-type 4H-SiC drift layer. By etching periodic grooves in the N-type 4H-SiC drift layer and then growing an N-type 4H-SiC JFET layer, the periodic grooves can induce the atomic steps on the surface of the 4° tilt N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, thereby forming a large-area atomic step bundle on the N-type 4H-SiC. A large area of ​​(0001) crystal plane is obtained on the surface of the JFET layer, and a high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the excess atomic step beam is smoothed by chemical mechanical polishing to obtain a high-mobility N-type 3C-SiC channel layer (mobility up to 150cm 2 / Vs), a high-voltage N-type 4H-SiC JFET layer and an N-type 4H-SiC drift layer, can reduce the on-resistance of the SiC MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic structural diagram of a silicon carbide MOSFET device provided in an embodiment of the present disclosure;

[0026] Figure 2 for Figure 1 A magnified schematic diagram of the local structure;

[0027] Figure 3A schematic diagram of another structure of a silicon carbide MOSFET device provided in an embodiment of the present disclosure;

[0028] Figure 4 A flow chart of a method for preparing a silicon carbide MOSFET device provided in an embodiment of the present disclosure;

[0029] Figure 5 A flow chart of another method for preparing a silicon carbide MOSFET device provided in an embodiment of the present disclosure;

[0030] Figure 6 for Figure 1 A schematic diagram of the structure of a silicon carbide MOSFET device during the preparation process is shown;

[0031] Figure 7 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0032] Figure 8 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0033] Figure 9 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0034] Figure 10 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0035] Figure 11 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0036] Figure 12 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0037] Figure 13 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0038] Figure 14 for Figure 1 Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0039] Figure 15 for Figure 1Another structural schematic diagram of a silicon carbide MOSFET device during the preparation process is shown;

[0040] Figure 16 Schematic diagram of the formation of atomic step bundle A2 induced by groove U;

[0041] Figure 17 Schematic diagram of 3D nucleation epitaxial growth and step flow epitaxial growth. DETAILED DESCRIPTION

[0042] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated regions or are not true to scale. They are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, or there may be intermediate elements or layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, or there may be intermediate elements or layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] The present disclosure provides a silicon carbide MOSFET device, including a cell structure, such as Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 A magnified schematic diagram of the local structure of the cell structure includes:

[0046] An N+ type 4H-SiC substrate 1, wherein a first angle between the [11-20] crystal axis of the N+ type 4H-SiC substrate 1 and its thickness direction (vertical direction) is 80-89°, that is, an angle θ between the [11-20] crystal axis of the N+ type 4H-SiC substrate 1 and the horizontal direction is 1-10°; for example, the present disclosure uses an N+ type 4H-SiC substrate 1 with a 4° tilt angle;

[0047] An N-type 4H-SiC drift layer 2 is located on one side of an N+ type 4H-SiC substrate 1. A surface of the N-type 4H-SiC drift layer 2 away from the N+ type 4H-SiC substrate 1 has periodically arranged grooves U. A second angle (i.e., angle θ) between the [11-20] crystal axis of the N+ type 4H-SiC substrate and an interface between the N-type 4H-SiC drift layer 2 and the N+ type 4H-SiC substrate 1 is 1-10°. For example, the periodically arranged grooves U may be distributed in an array.

[0048] The N-type 4H-SiC JFET layer 3 is located on a side of the N-type 4H-SiC drift layer 2 away from the N+ type 4H-SiC substrate 1. The side of the N-type 4H-SiC JFET layer 3 close to the N+ type 4H-SiC substrate 1 is filled with a groove U. The surface of the N-type 4H-SiC JFET layer 3 away from the N+ type 4H-SiC substrate 1 includes multiple (0001) crystal planes A1 (i.e., silicon planes). The multiple (0001) crystal planes A1 are separated by atomic step bundles A2.

[0049] The N-type 3C-SiC channel layer 4 is located on a side of the N-type 4H-SiC JFET layer 3 away from the N+ type 4H-SiC substrate 1 . The surface of the N-type 3C-SiC channel layer 4 away from the N+ type 4H-SiC substrate 1 is a flat surface.

[0050] The above-mentioned silicon carbide MOSFET device provided by the embodiment of the present disclosure adopts an N+ type 4H-SiC substrate with a first angle of 80-89° between the [11-20] crystal axis and its thickness direction, such as a 4° tilt N+ type 4H-SiC substrate, so that a longitudinal N-type 4H-SiC drift layer can be used as a voltage-resistant region, thereby improving the area utilization of the device; and the present disclosure uses a large tilt N+ type 4H-SiC substrate as an epitaxial substrate, which can realize conventional epitaxial growth of an N-type 4H-SiC drift layer, and by etching periodic grooves in the N-type 4H-SiC drift layer, and then growing an N-type 4H-SiC JFET layer, during the growth process, the periodic grooves can induce the atomic steps on the surface of the 4° tilt N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, thereby forming a large-area atomic step bundle on the N-type 4H-SiC A large area of ​​(0001) crystal plane is obtained on the surface of the JFET layer, and a high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the excess atomic step beam is smoothed by chemical mechanical polishing to obtain a high-mobility N-type 3C-SiC channel layer (mobility up to 150cm 2 / Vs), a high-voltage N-type 4H-SiC JFET layer and an N-type 4H-SiC drift layer, can reduce the on-resistance of the SiC MOSFET device.

[0051] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 2 As shown, the angle between the (0001) crystal plane A1 of the N-type 4H-SiC JFET layer 3 and the interface between the N-type 4H-SiC drift layer 2 and the N+ type 4H-SiC substrate 1 is a third angle, and the third angle is the same as the second angle θ. For example, the present disclosure uses a 4° tilted N+ type 4H-SiC substrate 1, so the angle between the (0001) crystal plane A1 of the N-type 4H-SiC JFET layer 3 and the interface between the N-type 4H-SiC drift layer 2 and the N+ type 4H-SiC substrate 1 is 4°.

[0052] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 2As shown, the present disclosure etches periodic grooves U in the N-type 4H-SiC drift layer 2 and then grows the N-type 4H-SiC JFET layer 3. During the growth process, the periodic grooves U can induce the atomic steps on the surface of the 4°-tilt N-type 4H-SiC JFET layer 3 to merge to form a large-area atomic step bundle A2, thereby obtaining a large-area (0001) crystal plane. The orthographic projection of the (0001) crystal plane on the N+ type 4H-SiC substrate 1 overlaps with the orthographic projection of the grooves U on the N+ type 4H-SiC substrate 1.

[0053] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 and Figure 2 As shown, the thickness of the N-type 4H-SiC drift layer 2 can be 1-100 μm, for example, 1 μm, 2 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc. The doping concentration of the N-type 4H-SiC drift layer 2 can be 1×10 14 ~1×10 17 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 wait.

[0054] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 2 As shown, the depth of the groove U can be 1nm~1μm, for example, 1nm, 5nm, 10nm, 50nm, 100nm, 500nm, 1μm, etc.; the width of the groove U can be 100nm~10μm, for example, 100nm, 200nm, 500nm, 1μm, 5μm, 10μm, etc.; the spacing between adjacent grooves U can be 100nm~100μm, for example, 100nm, 200nm, 500nm, 1μm, 10μm, 50μm, 100μm, etc.

[0055] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 2 As shown, the thickness of the N-type 4H-SiC JFET layer 3 can be 100 nm to 100 μm, such as 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, etc. The doping concentration of the N-type 4H-SiC JFET layer 3 can be 1×1014 ~1×10 19 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 wait.

[0056] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 2 As shown, the thickness d of the minimum thickness of the N-type 3C-SiC channel layer 4 (i.e., the connection between the (0001) crystal plane A1 and the atomic step bundle A2) can be 10 nm to 5 μm, such as 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc. The doping concentration of the N-type 3C-SiC channel layer 4 can be 1×10 14 ~1×10 19 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 wait.

[0057] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1As shown, it also includes: two P-type well regions 5 located in and spaced apart from each other among the N-type 3C-SiC channel layer 4, the N-type 4H-SiC JFET layer 3 and the N-type 4H-SiC drift layer 2, and an N+ source contact region 6 and a P+ source contact region 7 located in the P-type well region 5 and in contact with each other. The P-type well region 5 is located in the N-type 4H-SiC drift layer 2 near the lower surface of the N+ 4H-SiC substrate 1, the upper surface of the P-type well region 5 away from the N+ 4H-SiC substrate 1 is flush with the upper surface of the N-type 3C-SiC channel layer 4 away from the N+ 4H-SiC substrate 1, and the P+ source contact region 7 is arranged near the side of the N-type 3C-SiC channel layer 4. Specifically, the P-type well region 5, the N+ source contact region 6 and the P+ source contact region 7 are all formed on the upper surface of the N-type 3C-SiC channel layer 4 by ion implantation, and the depth of the ion implantation needs to be controlled in each region.

[0058] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes: a gate dielectric layer 8 located on the side of the N-type 3C-SiC channel layer 4 away from the N+ type 4H-SiC substrate 1, a gate electrode 9 located on the side of the gate dielectric layer 8 away from the N+ type 4H-SiC substrate 1, and an isolation dielectric layer 10 located on the side of the gate electrode 9 away from the N+ type 4H-SiC substrate 1; wherein the gate dielectric layer 8 is in contact with the N-type 3C-SiC channel layer 4, the P-type well region 5 and a portion of the N+ source contact region 6, the gate electrode 9 covers the gate dielectric layer 8, and the isolation dielectric layer 10 wraps the gate electrode 9 and the gate dielectric layer 8 and is in contact with the N+ source contact region 6; specifically, the materials of the gate dielectric layer 8 and the isolation dielectric layer 10 can be dielectric materials such as silicon dioxide and silicon nitride; the material of the gate electrode 9 can be metals such as titanium, aluminum, gold, silver, copper and their alloys, or can be conductive materials such as heavily doped polysilicon, titanium nitride, and indium tin oxide.

[0059] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 As shown, it also includes a source electrode 11 located on the side of the isolation dielectric layer 10, the N+ source contact region 6 and the P+ source contact region 7 away from the N+ type 4H-SiC substrate 1. The source electrode 11 wraps the isolation dielectric layer 10 and contacts the N+ source contact region 6 and the P+ source contact region 7. Specifically, the material of the source electrode 11 can be metals such as titanium, aluminum, gold, silver, copper and their alloys, or conductive materials such as heavily doped polysilicon, titanium nitride, indium tin oxide, etc. Different cells in the active area of ​​the device are connected through the source electrode 11 interconnection and the gate electrode 9 interconnection.

[0060] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1As shown, it also includes a drain electrode 12 located on the side of the N+ type 4H-SiC substrate 1 away from the N- type 4H-SiC drift layer 2. The material of the drain electrode 12 can be nickel, aluminum, titanium, tungsten and other metals and their alloys.

[0061] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 As shown, the N-type 4H-SiC JFET layer 3 is taken as an example to wrap the side portion of the P-type well region 5. Of course, the N-type 4H-SiC JFET layer 3 can also completely wrap the P-type well region 5.

[0062] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 As shown, when the device is working, electrons first flow from the source electrode 11 through the N+ source contact region 6 contact region, then enter the N-type 4H-SiC JFET layer 3 and the N-type 4H-SiC drift layer 2 through the N-type channel induced by the gate electrode 9 in the N-type 3C-SiC channel layer 4 and the P-type well region 5, and finally reach the drain electrode 12 to form a current.

[0063] The above-mentioned silicon carbide MOSFET device provided in the embodiment of the present disclosure uses a MOSFET configuration to achieve normally-off operation, meeting the power device's demand for safe power-off shutdown; and the present disclosure uses a P-type well region 5, an N-type 4H-SiC JFET layer 3 and an N-type 4H-SiC drift layer 2 as a voltage-resistant structure, which has avalanche breakdown capability under reverse bias state, thereby improving the reliability of the device.

[0064] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, as Figure 1 As shown, due to the difference in energy band gap between 3C-SiC and 4H-SiC, there is a heterojunction barrier at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3; in order to reduce the heterojunction barrier, as shown in FIG. Figure 3 As shown, Figure 3 Another silicon carbide MOSFET device structure provided in an embodiment of the present disclosure is: Figure 3 and Figure 1 The structure is basically the same, the difference is Figure 3 The N+ well region 13 is also included at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3. The N+ well region 13 can reduce or eliminate the effect of the heterojunction barrier. Specifically, the present disclosure forms the N+ well region 13 at the interface between the N-type 3C-SiC channel layer 4 and the N-type 4H-SiC JFET layer 3 by ion implantation while forming the P-type well region 5, the N+ source contact region 6, and the P+ source contact region 7 by ion implantation.

[0065] In some embodiments, in the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure, the planar structure of the cell structure can be a strip, rectangle or hexagon, etc. After the gate electrode and the source electrode are completed, the device can be formed into a complete device by forming different cells such as strip cells, square cells, hexagonal cells, etc. Figure 1 and Figure 3 Take the plane structure of the cellular structure as a rectangle as an example.

[0066] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned silicon carbide MOSFET device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned silicon carbide MOSFET device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned silicon carbide MOSFET device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0067] In some embodiments, the method for preparing the above-mentioned silicon carbide MOSFET device provided in the embodiments of the present disclosure is as follows: Figure 4 As shown, this may include:

[0068] S401, epitaxially growing an N-type 4H-SiC drift layer on one side of an N+ type 4H-SiC substrate using a step flow epitaxial method;

[0069] S402, patterning the surface of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate to form periodically arranged grooves;

[0070] S403, cleaning the wafer surface of the N-type 4H-SiC drift layer, and then epitaxially growing an N-type 4H-SiC JFET layer on a side of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate using a step flow epitaxial method;

[0071] S404, epitaxially growing an N-type 3C-SiC channel layer on a side of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate by a 3D nucleation epitaxial method;

[0072] S405 , grinding the surface of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate by chemical mechanical polishing.

[0073] In some embodiments, in the above preparation method provided in the embodiments of the present disclosure, Figure 5 As shown, it also includes:

[0074] S501, performing ion implantation in the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer, and the N-type 4H-SiC drift layer to form a P-type well region, an N+ source contact region, and a P+ source contact region;

[0075] S502, forming a gate dielectric layer, a gate electrode, and an isolation dielectric layer in sequence on a side of the N-type 3C-SiC channel layer away from the N+-type 4H-SiC substrate;

[0076] S503, forming a source electrode on a side of the gate dielectric layer away from the N+ type 4H-SiC substrate, wherein the source electrode wraps around the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region;

[0077] S504 , forming a drain electrode on a side of the N+ type 4H—SiC substrate away from the N− type 4H—SiC drift layer.

[0078] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, when performing ion implantation in the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer and the N-type 4H-SiC drift layer in step S501, the method further includes: implanting N-type ions at the interface between the N-type 3C-SiC channel layer and the N-type 4H-SiC JFET layer to form an N+-type well region.

[0079] In order to better understand the above preparation method provided in the embodiment of the present disclosure, the present disclosure is based on Figure 1 Taking the silicon carbide MOSFET device shown in FIG. 1 as an example, the preparation process of the silicon carbide MOSFET device is described in detail.

[0080] In some embodiments, Figure 1 The manufacturing process of the silicon carbide MOSFET device shown may specifically include the following steps:

[0081] (1) If Figure 6 As shown, an N-type 4H-SiC drift layer 2 is epitaxially grown on one side of an N+ type 4H-SiC substrate 1 by a step flow epitaxy method. Preferably, the thickness of the N-type 4H-SiC drift layer 2 can be 1 to 100 μm, for example, 1 μm, 2 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc.; the doping concentration of the N-type 4H-SiC drift layer 2 can be 1×10 14 ~1×10 17 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3Preferably, the tilt angle θ between the [11-20] crystal axis of the N+ type 4H-SiC substrate 1 and the tangent line of the wafer surface is 1-10°, for example, 4°.

[0082] (2) If Figure 7 As shown, a photolithographic mask is formed on the surface of the N-type 4H-SiC drift layer 2 away from the N+ type 4H-SiC substrate 1, followed by plasma etching to form periodically arranged grooves U. Preferably, the depth of the grooves U can be 1 nm to 1 μm, for example, 1 nm, 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, etc.; the width of the grooves U can be 100 nm to 10 μm, for example, 100 nm, 200 nm, 500 nm, 1 μm, 5 μm, 10 μm, etc.; and the spacing between adjacent grooves U can be 100 nm to 100 μm, for example, 100 nm, 200 nm, 500 nm, 1 μm, 10 μm, 50 μm, 100 μm, etc.

[0083] (3) If Figure 8 As shown, after etching the groove U, the wafer surface of the N-type 4H-SiC drift layer is thoroughly cleaned, and then the N-type 4H-SiC JFET layer 3 is epitaxially grown on the side of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate 1 by the step flow epitaxy method. Due to the presence of the periodic groove U, the atomic steps on the surface of the 4° tilted N-type 4H-SiC JFET layer 3 epitaxially grown by the step flow epitaxy method will be induced to merge during the growth process, thereby forming an atomic step bundle A2. The method of inducing the formation of the atomic step bundle A2 by the groove U is as follows: Figure 16 As shown, the formation of atomic step bundles A2 will produce a large area of ​​(0001) crystal planes A1. The width of these (0001) crystal planes A1 is related to the thickness of the epitaxial growth, the spacing of the periodic grooves U, and the width and depth of the grooves U. Preferably, the thickness of the N-type 4H-SiC JFET layer 3 can be 100nm~100μm, such as 100nm, 200nm, 500nm, 1μm, 5μm, 10μm, 50μm, 100μm, etc. The doping concentration of the N-type 4H-SiC JFET layer 3 can be 1×10 14 ~1×10 19 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×1019 cm -3 wait.

[0084] (4) If Figure 9 As shown, the N-type 3C-SiC channel layer 4 is epitaxially grown on the side of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate (i.e., on the formed large area (0001) crystal plane A1) using 3D nucleation epitaxy. The difference between 3D nucleation epitaxy and step flow epitaxy is as follows: Figure 17 Preferably, the thickness of the N-type 3C-SiC channel layer 4 can be between 50 nm and 5 μm, such as 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc. The doping concentration of the N-type 3C-SiC channel layer 4 can be 1×10 14 ~1×10 19 cm -3 , for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 wait.

[0085] (5) If Figure 10 As shown, chemical mechanical polishing is used to smooth the surface macro-steps of the N-type 3C-SiC channel layer 4 away from the N+-type 4H-SiC substrate 1, thereby obtaining a smooth surface of the N-type 3C-SiC channel layer 4. Preferably, the thickness d of the smoothed N-type 3C-SiC channel layer 4 at the minimum thickness (i.e., the connection between the (0001) crystal plane A1 and the atomic step bundle A2) can be 10 nm to 5 μm, for example, 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.

[0086] (6) If Figure 11 As shown, Figure 11 and Figure 10 For the same structure, such as Figure 12As shown, multiple photolithography masks and ion implantations are performed in the N-type 3C-SiC channel layer 4, the N-type 4H-SiC JFET layer 3, and the N-type 4H-SiC drift layer 2 to form a P-type well region 5, an N+ source contact region 6, and a P+ source contact region 7. Preferably, the ion implantation depth of the P-type well region 5 is between 1 μm and 5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc., and the doping concentration is between 1×10 14 cm -3 to 1×10 19 cm -3 Between, for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 Preferably, the ion implantation depth of the N+ source contact region 6 is between 100 nm and 1 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration is between 1×10 18 cm -3 to 1×10 21 cm -3 Between, for example 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 Preferably, the ion implantation depth of the P+ source contact region 7 is between 100 nm and 1 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration is between 1×10 18 cm -3 to 1×10 21 cm -3 Between, for example 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm-3 wait.

[0087] (7) If Figure 13 As shown, in Figure 12 Gate oxide is deposited on the implanted epitaxial layer to form a gate dielectric layer 8 , and then gate metal material is deposited and etched to form a gate electrode 9 . The orthographic projection of the gate electrode 9 on the N+ type 4H-SiC substrate 1 partially overlaps with the N+ source contact region 6 . Preferably, the thickness of the gate dielectric layer 8 is between 10nm and 1μm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, etc.; the thickness of the gate electrode 9 is between 10nm and 10μm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0088] (8) If Figure 14 As shown, a dielectric deposition is performed on the gate electrode 9 to form an isolation dielectric layer 10. Preferably, the thickness of the isolation dielectric layer 10 is between 10 nm and 10 μm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0089] (9) Figure 15 As shown, the isolation dielectric layer 10 and the gate dielectric layer 8 are etched to form a source electrode contact window V in the region corresponding to the N+ source contact region 6 and the P+ source contact region 7 .

[0090] (10) Deposition of source electrode metal and drain electrode metal is performed, and after ohmic contact annealing, a source electrode 11 and a drain electrode 12 are formed, as shown in FIG. Figure 1 As shown, the device preparation is completed.

[0091] Through the above steps (1)-(10) Figure 1 The silicon carbide MOSFET device shown.

[0092] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process steps such as deposition, photoresist coating, masking, exposure, development, etching, photoresist stripping, etc., but may also include other process steps, which are subject to the formation of the desired patterned pattern in the actual production process and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition, or physical vapor deposition, which are not limited here; the mask used in the masking process may be a half-tone mask, a single slit diffraction mask, or a gray tone mask, which are not limited here; and the etching may be dry etching or wet etching, which are not limited here.

[0093] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned silicon carbide MOSFET device provided in embodiments of the present disclosure. Because the principles underlying the problem solved by this electronic device are similar to those underlying the aforementioned silicon carbide MOSFET device, the implementation of this electronic device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned silicon carbide MOSFET device provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0094] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, in addition to silicon carbide MOSFET devices, the electronic devices provided by the present disclosure may also include other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and so on.

[0095] The embodiments of the present disclosure provide a silicon carbide MOSFET device and an electronic device, which use an N+ type 4H-SiC substrate with a first angle of 80-89 degrees between the [11-20] crystal axis and its thickness direction, such as a 4° tilt N+ type 4H-SiC substrate, so that a longitudinal N-type 4H-SiC drift layer can be used as a voltage-resistant region, thereby improving the area utilization of the device; and the present disclosure uses a large tilt N+ type 4H-SiC substrate as an epitaxial substrate, which can realize conventional epitaxial growth of an N-type 4H-SiC drift layer, and then grows an N-type 4H-SiC JFET layer by etching periodic grooves in the N-type 4H-SiC drift layer. During the growth process, the periodic grooves can induce the atomic steps on the surface of the 4° tilt N-type 4H-SiC JFET layer to merge to form a large-area atomic step bundle, thereby forming a large-area atomic step bundle on the N-type 4H-SiC JFET layer. A large area of ​​(0001) crystal plane is obtained on the surface of the JFET layer, and a high-quality N-type 3C-SiC channel layer can be grown on the (0001) crystal plane. Finally, the excess atomic step beam is smoothed by chemical mechanical polishing to obtain a high-mobility N-type 3C-SiC channel layer (mobility up to 150cm 2 / Vs), a high-voltage N-type 4H-SiC JFET layer and an N-type 4H-SiC drift layer, can reduce the on-resistance of the SiC MOSFET device.

[0096] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0097] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A silicon carbide MOSFET device, characterized in that: Comprising a cellular structure, the cellular structure comprising: An N+ type 4H-SiC substrate, wherein a first angle between an [11-20] crystal axis and a thickness direction of the N+ type 4H-SiC substrate is 80-89°; An N-type 4H-SiC drift layer is located on one side of the N+ type 4H-SiC substrate, wherein a surface of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate has periodically arranged grooves, and a second angle between an [11-20] crystal axis of the N+ type 4H-SiC substrate and an interface between the N-type 4H-SiC drift layer and the N+ type 4H-SiC substrate is 1-10°; An N-type 4H-SiC JFET layer is located on a side of the N-type 4H-SiC drift layer away from the N+ type 4H-SiC substrate, a side of the N-type 4H-SiC JFET layer close to the N+ type 4H-SiC substrate fills the groove, and a surface of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate includes multiple (0001) crystal planes; The N-type 3C-SiC channel layer is located on a side of the N-type 4H-SiC JFET layer away from the N+ type 4H-SiC substrate, and the surface of the N-type 3C-SiC channel layer away from the N+ type 4H-SiC substrate is a flat surface.

2. The silicon carbide MOSFET device according to claim 1, wherein The angle between the (0001) crystal plane and the interface between the N-type 4H-SiC drift layer and the N+ type 4H-SiC substrate is a third angle, which is the same as the second angle.

3. The silicon carbide MOSFET device according to claim 1, wherein The orthographic projection of the (0001) crystal plane on the N+ type 4H-SiC substrate and the orthographic projection of the groove on the N+ type 4H-SiC substrate overlap with each other.

4. The silicon carbide MOSFET device according to claim 1, wherein The thickness of the N-type 4H-SiC drift layer is 1-100 μm, and the doping concentration of the N-type 4H-SiC drift layer is 1×10 14 ~1×10 17 cm -3 .

5. The silicon carbide MOSFET device according to claim 1, wherein The depth of the groove is 1 nm to 1 μm, the width of the groove is 100 nm to 10 μm, and the distance between adjacent grooves is 100 nm to 100 μm.

6. The silicon carbide MOSFET device according to claim 1, wherein: The thickness of the N-type 4H-SiC JFET layer is 100 nm to 100 μm, and the doping concentration of the N-type 4H-SiC JFET layer is 1×10 14 ~1×10 19 cm -3 .

7. The silicon carbide MOSFET device according to claim 1, wherein: The thickness of the N-type 3C-SiC channel layer at its minimum thickness is 10 nm to 5 μm, and the doping concentration of the N-type 3C-SiC channel layer is 1×10 14 ~1×10 19 cm -3 .

8. The silicon carbide MOSFET device according to claim 1, wherein It also includes an N+ type well region located at the interface between the N type 3C-SiC channel layer and the N type 4H-SiC JFET layer.

9. The silicon carbide MOSFET device according to any one of claims 1 to 8, wherein: The present invention also includes: two P-type well regions located in and spaced apart from each other among the N-type 3C-SiC channel layer, the N-type 4H-SiC JFET layer, and the N-type 4H-SiC drift layer, and an N+ source contact region and a P+ source contact region located in the P-type well region and laterally arranged and contacting each other; wherein the P-type well region is located in the N-type 4H-SiC drift layer near the lower surface of the N+ type 4H-SiC substrate, the upper surface of the P-type well region away from the N+ type 4H-SiC substrate is flush with the upper surface of the N-type 3C-SiC channel layer away from the N+ type 4H-SiC substrate, and the P+ source contact region is located near the side of the N-type 3C-SiC channel layer; The present invention also includes: a gate dielectric layer located on a side of the N-type 3C-SiC channel layer away from the N+ type 4H-SiC substrate, a gate electrode located on a side of the gate dielectric layer away from the N+ type 4H-SiC substrate, and an isolation dielectric layer located on a side of the gate electrode away from the N+ type 4H-SiC substrate; wherein the gate dielectric layer contacts the N-type 3C-SiC channel layer, the P-type well region, and a portion of the N+ source contact region, the gate electrode covers the gate dielectric layer, and the isolation dielectric layer wraps the gate electrode and the gate dielectric layer and contacts the N+ source contact region; It also includes a source electrode located on a side of the isolation dielectric layer, the N+ source contact region, and the P+ source contact region away from the N+ type 4H-SiC substrate, wherein the source electrode wraps the isolation dielectric layer and contacts the N+ source contact region and the P+ source contact region; The device further includes a drain electrode located on a side of the N+ type 4H-SiC substrate away from the N- type 4H-SiC drift layer.

10. An electronic device, characterized in that: The device comprises a silicon carbide MOSFET as claimed in any one of claims 1 to 9.

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