Cell structure of field effect transistor and preparation method thereof

Abstract

The invention provides a cellular structure of a field effect transistor and a preparation method thereof. The cellular structure comprises a substrate; the drift layer is provided with a first groove; the first source region structure comprises an oxide layer, source electrodes and an insulation structure, and the source electrodes are located on the two sides of the insulation structure in the first direction; the second source region structure is located in the drift layer and located on the two sides of the first source region structure in the first direction, the second source region structure comprises a first doped region and a second doped region, the first doped region is located in the second doped region, and the first doped region and the second doped region are both in contact with the first source region structure; the surfaces of the sides, away from the substrate, of the first doped region and the second doped region are located in the first surface, the doping type of the first doped region is the same as that of the drift layer, and the doping type of the first doped region is opposite to that of the second doped region; and the gate structure is positioned on one side, deviating from the substrate, of the drift layer. The problem that other devices in a circuit can be damaged by leakage current generated by a field effect transistor in a cut-off state is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a cell structure of a field effect transistor and a method for manufacturing the same. Background Art

[0002] SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) mainly acts as an electronic switch in a power electronic system. When the MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not anti-parallel connected, this leakage current may cause damage to other devices in the circuit. In addition, when the SiC MOSFET is used for rectification in an AC circuit, since the MOSFET can only conduct under a forward voltage, an anti-parallel diode is required to provide a conduction path under a reverse voltage, so as to achieve current rectification. Therefore, it is usually necessary to anti-parallel connect a diode outside the SiC MOSFET or integrate a diode inside the SiC MOSFET to improve the performance of the SiC MOSFET body diode, thereby improving the working efficiency of the SiC MOSFET. However, the external anti-parallel diode will increase the occupied space of the circuit, increase the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance, resulting in problems such as slow response speed and poor reliability of the reverse diode. The turn-on voltage of the internally integrated heterojunction SBD (Schottky Barrier Diode, hereinafter referred to as SBD) is too high, and it is difficult to play a role in freewheeling protection of the MOSFET under reverse bias. Moreover, both methods will occupy additional area, the reverse leakage of the integrated Schottky diode device is large, and even when the SBD area is too large, it will affect the reverse breakdown voltage of the MOSFET. And the self-voltage drop of the Schottky diode is too large at high currents, which will cause a very large voltage drop loss on the Schottky diode when the freewheeling current is large. Therefore, there are difficulties in dealing with the reverse leakage current of MOSFET devices at present.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main object of the present application is to provide a cell structure of a field effect transistor and a method for manufacturing the same, so as to solve the problem that the leakage current generated by the field effect transistor in the off state in the prior art will damage other devices in the circuit.

[0005] To achieve the above object, according to one aspect of the present application, a cell structure of a field effect transistor is provided, including: a substrate; a drift layer located on one side of the substrate and having a first surface on the side facing away from the substrate, the first surface having a first groove; a first source region structure located in the first groove, the first source region structure including an oxide layer, a source electrode, and an insulating structure, the oxide layer covering the bottom and side walls of the first groove, the source electrode being located on both sides of the insulating structure in a first direction, the first direction being parallel to the first surface; a second source region structure located in the drift layer and on both sides of the first source region structure in the first direction, the second source region structure including a first doped region and a second doped region, wherein the first doped region is located in the second doped region, both the first doped region and the second doped region are in contact with the first source region structure, the surfaces of the first doped region and the second doped region facing away from the substrate are both located in the first surface, the doping type of the first doped region is the same as that of the drift layer, and the doping types of the first doped region and the second doped region are opposite; a gate structure located on the side of the drift layer facing away from the substrate.

[0006] Optionally, the insulating structure includes one or more first insulating layers and a plurality of second insulating layers, and the plurality of first insulating layers and one or more second insulating layers are alternately distributed in the first direction, and the dielectric constant of the first insulating layer is lower than that of the second insulating layer.

[0007] Optionally, when both the first insulating layer and the second insulating layer are multiple, the second insulating layer is provided between the source electrode and the adjacent first insulating layer.

[0008] Optionally, the insulating structure further includes a third insulating layer, and the third insulating layer covers the upper surface of the oxide layer at the bottom of the first groove.

[0009] Optionally, the cell structure further includes a first conductive layer and a contact metal, the contact metal is located on the side of the second source region structure facing away from the substrate, and part of the first conductive layer covers the contact metal and the first source region structure.

[0010] Optionally, the insulating structure further includes a fourth insulating layer, the fourth insulating layer is located between the source electrodes and is in contact with the first insulating layer and the second insulating layer, and the surface of the fourth insulating layer facing away from the substrate is located in the first surface.

[0011] Optionally, in the first direction, the width ratio of the first insulating layer to the second insulating layer is (1:1) to (10:1).

[0012] According to another aspect of the present application, a method for preparing a cell structure of a field effect transistor is provided, and the method for preparing a cell structure of a field effect transistor is used for the cell structure of the field effect transistor, and the method comprises: providing a substrate; forming a drift layer on one side of the substrate, the drift layer having a first surface on a side away from the substrate, the first surface having a first groove; forming a first source region structure in the first groove, the first source region structure comprising an oxide layer, a source electrode and an insulating structure, the oxide layer covering the bottom and sidewalls of the first groove, the source electrode being located on both sides of the insulating structure in a first direction; forming a second source region structure in the drift layer A region structure, the second source region structure is located on both sides of the first source region structure in the first direction, the second source region structure includes a first doping region and a second doping region, wherein the first doping region is located in the second doping region, the first doping region and the second doping region are both in contact with the first source region structure, the surfaces of the first doping region and the second doping region facing away from the substrate are both located in the first surface, the first doping region and the drift layer have the same doping type, the first doping region and the second doping region have opposite doping types, and the first direction is parallel to the first surface; a gate structure is formed on the side of the drift layer facing away from the substrate.

[0013] Optionally, the step of forming the source includes: filling the first groove with source material, and etching the source material to form a second groove in the source material, and the remaining source material constitutes the source located on both sides of the second groove in the first direction.

[0014] Optionally, the step of forming the insulating structure includes: filling the second groove with a first material and etching the first material to form a plurality of third grooves arranged along the first direction, the remaining first material constituting a first insulating layer, the third groove penetrating the first insulating layer in a second direction and a third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to the second direction and the first direction respectively; filling the third groove with a second material to form a second insulating layer, the first insulating layer and the second insulating layer constituting the insulating structure; or forming a portion of the second insulating layer on the bottom and sidewalls of the second groove; forming a first insulating layer on a portion of the second insulating layer, and forming another portion of the second insulating layer on the side of the first insulating layer away from the substrate.

[0015] Applying the technical solution of the present application, a cell structure of a field-effect transistor is provided, including a substrate, a drift layer, a first source region structure, a second source region structure, and a gate structure. The first source region structure is located in a first groove of the drift layer, the second source region structure is located on both sides of the first groove in a first direction, and the source electrodes of the first source region structure are separated by an insulating structure of the first source region structure, so that source electrode - insulating structure - source electrode forms a capacitive structure. When the field-effect transistor operates in the reverse state, charges will accumulate at the source electrode acting as a capacitive plate to generate an electric field. The second doping region in the second source region structure is in contact with the first source region structure, and the second doping region can be affected by the electric field generated by the source electrode. This electric field can attract electrons in the second doping region, and a large number of electrons will accumulate in a region on the side of the second doping region close to the first source region structure. Since this region is mainly conductive by electrons, an inversion layer of the second doping region is formed. The doping type of this inversion layer is the same as that of the first doping region, and it can allow the current flowing from the first doping region to pass through, forming a continuous current channel. This continuous current channel enables the leakage current to smoothly pass through the inversion layer to the drain, thereby avoiding the leakage current from entering the circuit and damaging other devices. It solves the problem that the leakage current generated by the field-effect transistor in the cut-off state in the prior art will damage other devices in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The schematic diagrams of the accompanying drawings forming a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0017] Figure 1 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a first field-effect transistor proposed according to the present application;

[0018] Figure 2 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a second field-effect transistor proposed according to the present application;

[0019] Figure 3 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a third field-effect transistor proposed according to the present application;

[0020] Figure 4 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a fourth field-effect transistor proposed according to the present application;

[0021] Figure 5 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a fifth field-effect transistor proposed according to the present application;

[0022] Figure 6 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a sixth field-effect transistor proposed according to the present application;

[0023] Figure 7 shows Figure 2 an enlarged structural schematic diagram of the insulation structure in

[0024] Figure 8 a schematic flow chart of a preparation method for a cell structure of a field effect transistor according to the present application;

[0025] Figure 9 shows Figure 8 a schematic cross-sectional structure diagram of the substrate and the matrix after forming the drift layer in the preparation method in

[0026] Figure 10 shows Figure 9 a schematic cross-sectional structure diagram of the matrix after forming the second source region structure in the formed drift layer and forming the oxide layer in the first groove in

[0027] Figure 11 shows Figure 10 a schematic cross-sectional structure diagram of the matrix after forming the source electrode in the first groove with the oxide layer formed in

[0028] Figure 12 shows Figure 11 a schematic cross-sectional structure diagram of the matrix after forming the first insulating layer between the formed source electrodes in

[0029] Figure 13 shows Figure 12 a schematic cross-sectional structure diagram of the matrix after forming the second insulating layer in the formed third groove in

[0030] Figure 14 shows Figure 11 a schematic cross-sectional structure diagram of the matrix after forming a part of the second insulating layer in the formed second groove in

[0031] Figure 15 shows Figure 14 a schematic cross-sectional structure diagram of the matrix after forming the first insulating layer and another part of the second insulating layer in the second groove with a part of the second insulating layer formed in

[0032] Among them, the above-mentioned drawings include the following reference numerals:

[0033] 10. Substrate; 20. Drift layer; 30. First source region structure; 31. Source electrode; 32. Insulating structure; 321. First insulating layer; 322. Second insulating layer; 323. Third insulating layer; 324. Fourth insulating layer; 33. Oxide layer; 34. First groove; 40. Second source region structure; 41. First doped region; 42. Second doped region; 50. Gate structure; 51. First dielectric layer; 52. Gate; 53. Second conductive layer; 54. Second dielectric layer; 60. First conductive layer; 70. Contact metal; 80. Drain; 90. Second groove; 100. Third groove. Detailed implementation manners

[0034] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0035] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of the described features, steps, operations, devices, components, and / or combinations thereof.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0037] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the specification and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0038] As introduced in the background technology, in the prior art, SiC MOSFET mainly acts as an electronic switch in the power electronic system. When the MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not added in reverse parallel, this leakage current may cause damage to other devices in the circuit. At present, the method of integrating a diode in the SiC MOSFET body in reverse parallel or in the body will take up additional area, and the reverse leakage of the integrated Schottky diode device is large, and even when the SBD area is too large, it will affect the reverse breakdown voltage of the MOSFET. And the Schottky diode has a large voltage drop at high current, which will make the voltage drop loss on the Schottky diode very large when the freewheeling current is large. Therefore, there are difficulties in the processing of the reverse leakage current of the MOSFET device at present. In order to solve the problem that the leakage current generated by the field effect transistor in the off state in the prior art will damage other devices in the circuit, the embodiment of the present application provides a cell structure of a field effect transistor and a preparation method thereof.

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] According to one aspect of the present application, Figures 1 to 6 As shown, a cell structure of a field effect transistor is provided, comprising: a substrate 10; a drift layer 20, located on one side of the substrate 10, and having a first surface on a side away from the substrate 10, the first surface having a first groove; a first source region structure 30, located in the first groove, the first source region structure 30 comprising a source 31, an insulating structure 32 and an oxide layer 33, the oxide layer 33 covers the bottom and sidewall of the first groove, the source 31 is located on both sides of the insulating structure 32 in a first direction A, the first direction A is parallel to the first surface; a second source region structure 40, located in the drift layer 20, and located On both sides of the first source region structure 30 in the first direction A, the second source region structure 40 includes a first doping region 41 and a second doping region 42, wherein the first doping region 41 is located in the second doping region 42, the first doping region 41 and the second doping region 42 are both in contact with the first source region structure 30, and the surfaces of the first doping region and the second doping region facing away from the substrate are both located in the first surface, the first doping region 41 and the drift layer 20 have the same doping type, and the first doping region 41 and the second doping region 42 have opposite doping types; the gate structure 50 is located on the side of the drift layer 20 facing away from the substrate 10.

[0041] The present application provides a cell structure of a field-effect transistor, including a substrate, a drift layer, a first source region structure, a second source region structure, and a gate structure. The first source region structure is located in a first groove of the drift layer, the second source region structure is located on both sides of the first groove in a first direction. The source electrodes of the first source region structure are separated by an insulating structure of the first source region structure, so that source electrode - insulating structure - source electrode forms a capacitive structure. When the field-effect transistor operates in a reverse state, charges will accumulate at the source electrode acting as a capacitor plate to generate an electric field. The second doping region in the second source region structure is in contact with the first source region structure, and the second doping region can be affected by the electric field generated by the source electrode. This electric field can attract electrons in the second doping region, and a large number of electrons will accumulate in a region on the side of the second doping region close to the first source region structure. Since this region is mainly conductive by electrons, an inversion layer of the second doping region is formed. The doping type of this inversion layer is the same as that of the first doping region, which can allow the current flowing from the first doping region to pass through, forming a current continuation channel. This current continuation channel enables the leakage current to smoothly pass through the inversion layer and reach the drain, thereby avoiding the leakage current from entering the circuit and damaging other devices. This solves the problem that the leakage current generated by the field-effect transistor in the cut-off state in the prior art will damage other devices in the circuit.

[0042] In the above embodiment, the doping type of the substrate can be N-type, and the substrate can be silicon carbide or silicon nitride, etc., with a resistivity of 0.02 ± 20% Ω·cm. The doping type of the drift layer can be N-type, which is used to bear the breakdown voltage for the device. The doping concentration of the drift layer can be 1E15 - 1E16 cm -3 , and the doping concentration of the drift layer within this range can make the pressure-bearing effect of the device better. The thickness of the drift layer can be adjusted appropriately. For example, the thickness of the drift layer in a 1200V MOS device can be 9 - 11 μm, and the thickness of the drift layer in a 650V MOS device can be 5 - 7 μm.

[0043] In the above embodiment, the depth of the first groove can be 0.8 - 1.5 μm, and the width can be 0.15 - 1.3 μm to accommodate the first source region structure. The doping type of the first doping region is N-type, and the doping concentration can be 1E19 - 1E20 cm -3 , the implantation depth is 0.2 - 0.3 μm, while the doping type of the second doping region is P-type, the doping element can be Al, and the implantation dose is 1E17 ± 50% cm -3 , and the implantation depth is 0.7 - 0.8 μm. The first doping region and the second doping region with high doping concentrations can make the second source region structure have a low resistance, which is beneficial to the efficient flow of current and reduces the energy loss during switching.

[0044] In the above embodiment, the thickness of the oxide layer may be 0.03-0.08 μm. Setting the thickness within this range can provide sufficient electrical isolation to prevent the gate voltage from directly penetrating into the semiconductor region below, thereby ensuring the effectiveness of the gate control mechanism. The material may be silicon oxide.

[0045] In the above embodiment, if Figures 1 to 3 As shown, the gate structure 50 includes a first dielectric layer 51, a gate 52, a second conductive layer 53 and a second dielectric layer 54, wherein the first dielectric layer is located on the drift layer 20, the gate 52 is located on the side of the first dielectric layer 51 away from the drift layer 20, the second conductive layer 53 is located on the side of the gate 52 away from the first dielectric layer 51, and the second dielectric layer 54 covers the gate 52, the second conductive layer 53 and a portion of the first doped region 41. The gate structure 50 can control the formation and closing of the channel by applying a voltage, thereby determining the on and off states of the device.

[0046] Specifically, the material of the first dielectric layer can be oxide, nitride, such as SiO2 and Si3N4, and the thickness can be 0.03-0.08 μm. The material of the gate can be polysilicon. The material of the second conductive layer can be metals such as Mo, Ti, Ti, Ni, Pt and W. The material of the second dielectric layer can be oxide and / or nitride, such as SiO2 and Si3N4, and the thickness can be 600-1000 nm. Setting the thickness range of the first dielectric layer to the above values can better reduce the source-drain capacitance, increase the switching speed, and have both good electrical insulation and sufficient device reliability. Setting the thickness range of the second dielectric layer to the above values can provide sufficient protection without sacrificing the high-speed performance of the device.

[0047] In the above embodiment, if Figures 1 to 3 As shown, the cell structure also includes a drain 80, which, together with the source 31 and the gate 52, realizes signal amplification, switching and power management through voltage and current regulation. The material of the drain 80 can be at least one of aluminum (Al), titanium / aluminum / titanium (Ti / Al / Ti), cobalt silicide (CoSi2), tungsten (W), copper (Cu), tantalum (Ta) and tantalum nitride (TaN). This application does not make specific limitations.

[0048] In some optional embodiments, such as Figures 2 to 3 As shown, the insulating structure 32 includes one or more first insulating layers 321 and one or more second insulating layers 322, the multiple first insulating layers 321 and the multiple second insulating layers 322 are alternately distributed along the first direction A, and the dielectric constant of the first insulating layer 321 is lower than the dielectric constant of the second insulating layer 322. Figure 2 The insulating structure shown has a plurality of first insulating layers 321 and a plurality of second insulating layers 322. Figure 3Shown is an insulating structure having a first insulating layer 321 and a plurality of second insulating layers 322. (Among them, the technical solutions of the insulating structure 32 having a first insulating layer 321 and a second insulating layer 322, and the insulating structure 32 having a plurality of first insulating layers 321 and a second insulating layer 322 are not shown. The present application does not specifically limit the combination manner of the first insulating layer 321 and the second insulating layer 322). By introducing the first insulating layer 321 with a lower dielectric constant, the capacitance between the source and the drain is reduced, and the energy consumption during the switching process is reduced. At the same time, the presence of the second insulating layer 322 with a higher dielectric constant ensures the high breakdown voltage characteristics of the device, and good electrical performance can be maintained even under extreme conditions. The above alternating distribution mechanism not only optimizes the capacitance performance but also ensures the reliability of the device. And Figure 3 in the second insulating layer 322 is located between the first insulating layer 321 and the source 31, so that elements such as highly doped B or P in the polysilicon material of the source 31 can be blocked from diffusing into the first insulating layer 321 with a lower dielectric constant, resulting in a weakened conductivity of the source 31. It can also prevent elements such as B or P from diffusing into the first insulating layer 321 with a lower dielectric constant, causing the capacitance between the source and the drain to change, resulting in poor reliability of the device.

[0049] Specifically, the first insulating layer has a lower dielectric constant. The material of the first insulating layer can be materials such as fluorosilicate glass, porous organosilicate glass, fluorinated polyimide, benzocyclobutene, etc., with a thickness of 0.7 to 1 μm, while the material of the second insulating layer can be materials with a higher dielectric constant such as HfO2, Si3N4, TiO2, Al2O3, ZrO2, etc., with a line width of 0.05 to 0.01 μm. By reasonably adjusting the thickness of the first insulating layer and the line width of the second insulating layer, it is possible to reduce the source-drain capacitance, increase the switching speed, enhance the local breakdown voltage ability, and ensure the stability and long-term operation reliability of the device in a high-voltage and high-frequency environment.

[0050] In some alternative embodiments, as Figure 4 shown, when both the first insulating layer 321 and the second insulating layer 322 have a plurality of layers, there is a second insulating layer 322 between the source 31 and the adjacent first insulating layer 321. There are two reasons for such a setting. On the one hand, since the second insulating layer 322 with a higher dielectric constant has a higher density relative to the first insulating layer 321, it can block elements such as highly doped B or P in the polysilicon material of the source 31 from diffusing into the first insulating layer 321 with a lower dielectric constant, resulting in a weakened conductivity of the source 31. On the other hand, it avoids the capacitance between the source and the drain from changing due to elements such as B or P diffusing into the first insulating layer 321 with a lower dielectric constant, resulting in poor reliability of the device.

[0051] In some alternative embodiments, such as Figure 5 shown, the insulating structure 32 further includes a third insulating layer 323, the third insulating layer 323 has a relatively high dielectric constant, and the third insulating layer 323 covers the upper surface of the first groove bottom oxide layer 33. In the structure in the source trench, the electric field is likely to concentrate at the corners and the bottom, and the oxide layer 33 is easily broken down. The third insulating layer 323, as an insulating layer with a relatively high dielectric constant covering the oxide layer 33, can increase the breakdown voltage at the oxide layer 33, making the device not easily broken down, increasing the reliability of the device, and avoiding the early failure of the device caused by electric field concentration. Among them, the material of the third insulating layer can be a material with a higher dielectric constant such as HfO2, Si3N4, etc., and can be the same as or different from the material of the second insulating layer.

[0052] In some alternative embodiments, such as Figures 1 to 3 shown, the cell structure further includes a first conductive layer 60 and a contact metal 70. The contact metal 70 is located on the side of the second source region structure 40 away from the substrate 10, and part of the first conductive layer 60 covers the contact metal 70 and the first source region structure 30. The first conductive layer 60 and the contact metal 70 can optimize the current transmission efficiency. The contact metal 70 reduces the contact resistance between the first conductive layer 60 and the second source region structure 40, enabling the device to maintain good electrical performance under high-frequency and high-power conditions, while simplifying the packaging process and reducing costs.

[0053] Among them, the material of the contact metal can be materials such as Ni, Ti, etc., and the material of the first conductive layer can be aluminum (Al), titanium / aluminum / titanium (Ti / Al / Ti), cobalt silicide (CoSi2), tungsten (W), copper (Cu), tantalum (Ta), and tantalum nitride (TaN). The present application does not make specific limitations.

[0054] In some alternative embodiments, such as Figure 6 shown, the insulating structure 32 further includes a fourth insulating layer 324. The fourth insulating layer 324 is located between the source electrodes 31 and is in contact with the first insulating layer 321 and the second insulating layer 322. The surface of the fourth insulating layer 324 on the side away from the substrate 10 is located in the first surface. The fourth insulating layer 324 has a relatively high dielectric constant. Arranging the fourth insulating layer 324 at this position helps to disperse the electric field, reduce electric field concentration, and increase the breakdown voltage of the device. Moreover, it can also block water vapor to further enhance the insulation performance of the cell structure and improve the stability of the device.

[0055] Among them, the material of the fourth insulating layer can be HfO2 and Si3N4, or other materials with a higher dielectric constant, and the material can be the same as or different from the material of the second insulating layer.

[0056] In some alternative embodiments, such asFigure 7 As shown, in the first direction A, the ratio of the width d1 of the first insulating layer 321 to the width d2 of the second insulating layer 322 is (1:1) to (10:1). By designing this specific width ratio, the capacitance performance and breakdown voltage resistance of the device can be improved, achieving a balance between high performance and high reliability, and ensuring the overall efficiency and stability of the system.

[0057] According to another aspect of the present application, as Figure 8 shown, a method for preparing a cell structure of a field-effect transistor is provided. The method for preparing the cell structure of the field-effect transistor is used for the cell structure of the field-effect transistor, and the preparation method includes:

[0058] Step S1: Provide a substrate;

[0059] Specifically, the doping type of the substrate can be N-type, and the substrate can be silicon carbide or silicon nitride, etc., and its resistivity is 0.02 ± 20% Ωcm.

[0060] Step S2: Form a drift layer on one side of the substrate. The drift layer has a first surface on the side facing away from the substrate, and the first surface has a first groove;

[0061] Specifically, the doping type of the drift layer can be N-type, which is used to bear the breakdown voltage for the device. The doping concentration of the drift layer can be 1E15 to 1E16 cm -3 .

[0062] Step S3: Form a first source region structure in the first groove. The first source region structure includes an oxide layer, a source electrode, and an insulating structure. The oxide layer covers the bottom and sidewalls of the first groove, and the source electrode is located on both sides of the insulating structure in the first direction;

[0063] Specifically, the material of the source electrode can be polysilicon, the material of the oxide layer can be silicon oxide, and the material of the insulating structure can be fluorosilicate glass FSG, porous organosilicate glass P-OSG, HfO2, and Si3N4. The present application does not make specific limitations.

[0064] Step S4: Form a second source region structure in the drift layer. The second source region structure is located on both sides of the first source region structure in the first direction. The second source region structure includes a first doped region and a second doped region. Among them, the first doped region is located in the second doped region, and both the first doped region and the second doped region are in contact with the first source region structure. The surfaces of the first doped region and the second doped region facing away from the substrate are both located in the first surface. The doping type of the first doped region is the same as that of the drift layer, the doping types of the first doped region and the second doped region are opposite, and the first direction is parallel to the first surface;

[0065] Specifically, the doping type of the first doped region is N-type, and the doping concentration can be 1E19 to 1E20 cm -3, the implantation depth is 0.2 - 0.3 μm, while the doping type of the second doped region is P-type, the doping element can be Al, and the implantation dose is 1E17 ± 50% cm -3 , the implantation depth is 0.7 - 0.8 μm.

[0066] Step S5: Form a gate structure on the side of the drift layer away from the substrate.

[0067] Specifically, the gate structure includes a first dielectric layer, a gate, a second conductive layer, and a second dielectric layer. Among them, the first dielectric layer is located on the drift layer, the gate is located on the side of the first dielectric layer away from the drift layer, the second conductive layer is located on the side of the gate away from the first dielectric layer, and the second dielectric layer covers the gate, the second conductive layer, and part of the first doped region. The gate structure can control the formation and closing of the channel by applying a voltage, thereby determining the on and off states of the device.

[0068] Specifically, the material of the first dielectric layer can be oxide and / or nitride, such as SiO2 and Si3N4, and the thickness can be 0.03 - 0.08 μm. The material of the gate can be polysilicon. The material of the second conductive layer can be at least one of metals such as Mo, Ti, Ti, Ni, Pt, and W. The material of the second dielectric layer can be oxide, nitride, such as SiO2 and Si3N4, and the thickness can be 600 - 1000 nm.

[0069] The cell structure of the field effect transistor prepared by the above method for preparing the cell structure of the field effect transistor includes a substrate, a drift layer, a first source region structure, a second source region structure, and a gate structure. Among them, the first source region structure is located in the first groove of the drift layer, the second source region structure is located on both sides of the first groove in the first direction, and the source electrode of the first source region structure is separated by the insulating structure of the first source region structure, so that source-insulating structure-source forms a capacitive structure. When the field effect transistor operates in the reverse state, charges will accumulate at the source electrode acting as a capacitor plate to generate an electric field. The second doped region in the second source region structure is in contact with the first source region structure, and the second doped region can be affected by the electric field generated by the source electrode. This electric field can attract electrons in the second doped region, and a large number of electrons will accumulate in the region of the second doped region close to the first source region structure. Since this region is mainly conductive by electrons, an inversion layer of the second doped region is formed. The doping type of this inversion layer is the same as that of the first doped region, and it can allow the current flowing from the first doped region to pass through, forming a continuous current channel for the current. This continuous current channel enables the leakage current to smoothly pass through the inversion layer and be transmitted to the drain, thereby avoiding the leakage current from entering the circuit and damaging other devices. It solves the problem that the leakage current generated by the field effect transistor in the cut-off state in the prior art will damage other devices in the circuit.

[0070] In some alternative embodiments, such as Figures 9 to 11As shown, the steps of forming the source electrode 31 include: filling the source electrode material in the first groove, and etching the source electrode material to form a second groove 90 in the source electrode material, and the remaining source electrode material constitutes the source electrode 31 located on both sides of the second groove 90 in the first direction A.

[0071] Specifically, as Figure 9 shown, a substrate 10 is provided, a drift layer 20 is formed on the substrate 10, and a first groove 34 is formed in the drift layer 20. As Figure 10 shown, ion implantation is performed on both sides of the first groove to form a second doped region 42, ion implantation is performed in the second doped region 42 to form a first doped region 41, a second source region structure 40 is formed, and an oxide layer 33 is formed on the bottom and side walls of the first groove. As Figure 11 shown, the source electrode material is filled in the first groove formed with the oxide layer 33 and the source electrode material is etched to form a second groove 90 in the source electrode material, so that the entire source electrode 31 is divided into two parts of the source electrode 31 to prepare for the subsequent formation of the capacitor structure.

[0072] In some alternative embodiments, as Figures 12 to 15 shown, the steps of forming the insulating structure 32 include: filling a first material in the second groove, and etching the first material to form a plurality of third grooves 100 arranged along the first direction A, and the remaining first material constitutes a first insulating layer 321. The third grooves 100 penetrate the first insulating layer 321 in the second direction B and the third direction C. The second direction B is perpendicular to the first direction C, and the third direction C is perpendicular to both the second direction B and the first direction A respectively; filling a second material in the third grooves 100 to form a second insulating layer 322, and the first insulating layer 321 and the second insulating layer 322 constitute the insulating structure 32; or forming a part of the second insulating layer 322 on the bottom and side walls of the second groove; forming the first insulating layer 321 on a part of the second insulating layer 322, and forming another part of the second insulating layer 322 on the side of the first insulating layer 321 facing away from the substrate 10.

[0073] Specifically, there are two preparation methods for the insulating structure. The first preparation method is as follows: as Figure 12 shown, after forming two split source electrodes, a first material is filled in the second groove, and the first material is etched to form a plurality of third grooves 100 arranged along the first direction A. The remaining first material is the first insulating layer 321, where the ratio of the width of the first insulating layer 321 in the first direction A to the width of the third grooves 100 in the first direction A is (1:1) to (10:1), and the first material is a material with a lower dielectric constant. As Figure 13As shown, a second material with a relatively high dielectric constant is filled in the third groove to form a second insulating layer 322. The first insulating layer 321 and the second insulating layer 322 form an insulating structure 32. The insulating structure 32 formed by the first insulating layer 321 with a relatively low dielectric constant and the second insulating layer 322 with a relatively high dielectric constant can optimize the performance of the capacitive structure formed by source 31 - insulating structure 32 - source 31. Specifically, the introduction of the first insulating layer 321 with a relatively low dielectric constant reduces the capacitance between the source and the drain, reducing the energy consumption during the switching process. At the same time, the presence of the second insulating layer 322 with a relatively high dielectric constant ensures the high breakdown voltage characteristics of the device, enabling it to maintain good electrical performance even under extreme conditions.

[0074] The second preparation method is as follows: As Figure 14 shown, a part of the second insulating layer 322 is formed on the bottom and side walls of the second groove after forming two split sources; as Figure 15 shown, the second groove with a part of the second insulating layer 322 is filled with a first material with a relatively low dielectric constant to form a first insulating layer 321, and another part of the second insulating layer 322 is formed on the first insulating layer 321, so that the second insulating layer 322 can wrap the first insulating layer 321, thereby protecting the first insulating layer 321 in all directions.

[0075] It should be noted that the preparation order of the first source region structure and the second source region structure in this application can be exchanged, and no specific limitation is made.

[0076] In some embodiments, as Figure 1 shown, a gate structure 50, a contact metal 70, and a first conductive layer 60 are sequentially fabricated on the drift layer 20, and a drain 80 is formed on the back surface of the substrate 10. The specific fabrication method is not specifically limited in this application.

[0077] The above etching method can be a photolithography method, a wet etching method, or a dry etching method; the deposition method can be a chemical vapor deposition method, a physical vapor deposition method, a magnetron sputtering method, etc., and no specific limitation is made in this application.

[0078] By using the cell structure and the fabrication method of the field - effect transistor in the above application, the following beneficial effects can be achieved:

[0079] 1) The source-insulation structure-source cell structure of the field-effect transistor proposed in this application forms a capacitive structure. When the field-effect transistor operates in the reverse state, charges will accumulate at the source acting as a capacitor plate to generate an electric field. The second doped region in the second source region structure is in contact with the first source region structure. The second doped region can be affected by the electric field generated by the source. This electric field can attract electrons in the second doped region, and a large number of electrons will accumulate in the region of the second doped region close to the first source region structure. Since this region is mainly electron-conductive, an inversion layer of the second doped region is formed. The doping type of this inversion layer is the same as that of the first doped region, which allows the current flowing from the first doped region to pass through, forming a current continuation channel. This continuation channel enables the leakage current to smoothly pass through the inversion layer and be transmitted to the drain, thereby preventing the leakage current from entering the circuit and damaging other devices.

[0080] 2) The insulation structure in this application uses an alternating arrangement of a first insulating layer with a lower dielectric constant and a second insulating layer with a higher dielectric constant, which reduces the capacitance between the source and the drain and decreases the energy consumption during the switching process. At the same time, the presence of the second insulating layer with a higher dielectric constant ensures the high breakdown voltage characteristics of the device, enabling it to maintain good electrical performance even under extreme conditions. The above alternating distribution mechanism not only optimizes the capacitance performance but also guarantees the reliability of the device.

[0081] 3) The second insulating layer of the insulation structure in this application wraps the first insulating layer. The second insulating layer has a higher density relative to the first insulating layer, which can prevent highly doped elements such as B or P in the polysilicon material of the source from diffusing into the first insulating layer with a lower dielectric constant, resulting in a weakened conductivity of the source. It also avoids the capacitance change between the source and the drain caused by the diffusion of elements such as B or P into the first insulating layer with a lower dielectric constant, which would lead to a deterioration in the reliability of the device.

[0082] The above are only the preferred embodiments of this application and are not intended to limit this application. For those skilled in the art, various changes and modifications can be made to this application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. A cell structure of a field effect transistor, characterized in that, Comprising: A substrate; A drift layer, located on one side of the substrate and having a first surface on the side facing away from the substrate, the first surface having a first groove; A first source region structure, located in the first groove, the first source region structure including an oxide layer, a source electrode, and an insulating structure, the oxide layer covering the bottom and side walls of the first groove, the source electrode being located on both sides of the insulating structure in a first direction, the first direction being parallel to the first surface; A second source region structure, located in the drift layer and on both sides of the first source region structure in the first direction, the second source region structure including a first doped region and a second doped region, wherein the first doped region is located in the second doped region, both the first doped region and the second doped region are in contact with the first source region structure, the surfaces of the first doped region and the second doped region on the side facing away from the substrate are both located in the first surface, the doping type of the first doped region is the same as that of the drift layer, and the doping types of the first doped region and the second doped region are opposite; A gate structure, located on the side of the drift layer facing away from the substrate.

2. The cell structure according to claim 1, wherein The insulating structure includes one or more first insulating layers and one or more second insulating layers, the first insulating layers and the second insulating layers being alternately distributed along the first direction, and the dielectric constant of the first insulating layer being lower than that of the second insulating layer.

3. The cell structure according to claim 2, characterized in that, When both the first insulating layer and the second insulating layer are multiple, the second insulating layer is provided between the source electrode and the adjacent first insulating layer.

4. The cell structure according to claim 2, characterized in that, The insulating structure further includes a third insulating layer, the third insulating layer being located on the upper surface of the oxide layer at the bottom of the first groove.

5. The cell structure according to claim 2, characterized in that, The insulating structure further includes a fourth insulating layer, the fourth insulating layer being located between the source electrodes and in contact with the first insulating layer and the second insulating layer, and the surface of the fourth insulating layer on the side facing away from the substrate being located in the first surface.

6. The cell structure according to claim 1, characterized in that The cell structure further includes a first conductive layer and a contact metal, the contact metal being located on the side of the second source region structure facing away from the substrate, and part of the first conductive layer covering the contact metal and the first source region structure.

7. The cell structure according to claim 2, characterized in that, In the first direction, the ratio of the width of the first insulating layer to the width of the second insulating layer is (1:1) to (10:1).

8. A method for preparing a cell structure of a field effect transistor, characterized in that, The method for preparing the cell structure of the field effect transistor is used to prepare the cell structure of the field effect transistor according to any one of claims 1 to 7, and the preparation method includes: Providing a substrate; Forming a drift layer on one side of the substrate, the drift layer having a first surface on the side facing away from the substrate, the first surface having a first groove; Forming a first source region structure in the first groove, the first source region structure including an oxide layer, a source electrode, and an insulating structure, the oxide layer covering the bottom and side walls of the first groove, and the source electrode being located on both sides of the insulating structure in a first direction; A second source region structure is formed in the drift layer, the second source region structure is located on both sides of the first source region structure in the first direction, the second source region structure includes a first doping region and a second doping region, wherein the first doping region is located in the second doping region, the first doping region and the second doping region are both in contact with the first source region structure, surfaces of the first doping region and the second doping region facing away from the substrate are both located in the first surface, the first doping region and the drift layer have the same doping type, the first doping region and the second doping region have opposite doping types, and the first direction is parallel to the first surface; The gate structure is formed on a side of the drift layer facing away from the substrate.

9. The preparation method according to claim 8, wherein The steps of forming the source electrode include: The first groove is filled with a source material, and the source material is etched to form a second groove in the source material, and the remaining source material constitutes the source located at both sides of the second groove in the first direction.

10. The preparation method according to claim 9, characterized in that, The steps of forming the insulating structure include: Filling the second groove with a first material, and etching the first material to form a plurality of third grooves arranged along the first direction, wherein the remaining first material constitutes a first insulating layer, and the third grooves penetrate the first insulating layer in a second direction and a third direction, wherein the second direction is perpendicular to the first direction, and the third direction is perpendicular to the second direction and the first direction respectively; Filling the third groove with a second material to form a second insulating layer, wherein the first insulating layer and the second insulating layer constitute the insulating structure; or forming a portion of a second insulating layer on a bottom and sidewalls of the second groove; A first insulating layer is formed on a portion of the second insulating layer, and another portion of the second insulating layer is formed on a side of the first insulating layer facing away from the substrate.

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