Cell structure of MOSFET device

Abstract

The invention provides a cell structure of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a cell region of the cell structure comprises first JFET (Junction Field Effect Transistor) regions and second JFET regions, and the first JFET regions are at least positioned on two sides of the second JFET regions; the well region is located between the first JFET region and the second JFET region; the source region is located in the well region and surrounds the second JFET region, the portion, between the source region and the first JFET region, of the well region is a first part of well region, and the portion, between the source region and the second JFET region, of the well region is a second part of well region; the well contact region is positioned in a part of the second part of well region, so that channel regions which are respectively adjacent to the source region and the second JFET region are arranged in the residual second part of well region; and the second gate structure covers a part of the channel region, and a part of the source region and a part of the second JFET region which are respectively adjacent to the part of the channel region. According to the invention, the problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when a body diode of an existing MOSFET is used as a freewheeling path are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a cell structure of a MOSFET device. Background Art

[0002] As a wide-bandgap semiconductor material, silicon carbide (SiC) has broad application prospects in high-voltage, high-power, high-temperature, and high-frequency application fields due to its wide bandgap, high critical electric field strength, high thermal conductivity, and high saturation drift velocity.

[0003] SiC VDMOS has replaced Si-based devices in the traditional rectification field and accelerated the industrial development in fields such as rectification and inversion due to its excellent on-state blocking trade-off characteristics and high operating junction temperature. However, due to the wide bandgap of silicon carbide, the on-state voltage drop of the body diode in SiC VDMOS often exceeds 2.7V, which makes the turn-on voltage of the body diode in SiC VDMOS high and the reverse recovery loss large in the freewheeling condition, becoming a shortcoming in the freewheeling condition. In addition, the recombination process of electrons and holes when the body diode in SiC VDMOS is in the working state is likely to cause the expansion of silicon carbide material defects, resulting in device characteristic degradation and affecting the device working life.

[0004] To solve the above problems, two main solutions are currently used for improvement:

[0005] (1) Anti-parallel a Schottky diode outside the MOS;

[0006] (2) Integrate a Schottky diode in the MOS chip.

[0007] However, for the first solution, since the number and area of chips in the device increase, it will cause cost increase and packaging design complexity, resulting in an increase in parasitic effects and processes, and further causing more failure modes.

[0008] For the second solution, the current design of the Schottky diode has a weak ability to withstand the surge current during reverse freewheeling and may also cause an increase in the distance between adjacent cells.

[0009] Therefore, there is an urgent need for a MOSFET device to at least solve the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the MOSFET is used as the freewheeling path. Summary of the Invention

[0010] The main object of the present invention is to provide a cell structure of a MOSFET device to at least solve the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the MOSFET is used as the freewheeling path.

[0011] To achieve the above object, the present invention provides a cell structure of a MOSFET device. The cell structure includes a substrate, an epitaxial layer and a cell region located on one side of the substrate. The cell region is located in the epitaxial layer and includes: a first JFET region and a second JFET region, and the first JFET region is at least located on both sides of the second JFET region; a well region located between the first JFET region and the second JFET region, and the conductivity type of the well region is opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region. The well region between the source region and the first JFET region is the first partial well region, and the well region between the source region and the second JFET region is the second partial well region; a well contact region located in a part of the second partial well region, so that a channel region adjacent to the source region and the second JFET region respectively is formed in the remaining second partial well region. The doping type of the well contact region is the same as that of the well region, and the doping concentration of the well contact region is higher than that of the well region; a gate structure including an adjacent first gate structure and a second gate structure. The first gate structure covers the first partial well region, a part of the source region adjacent to the first partial well region respectively, and at least a part of the first JFET region. The second gate structure covers a part of the channel region, a part of the source region adjacent to the part of the channel region respectively, and a part of the second JFET region.

[0012] Optionally, the well contact region is adjacent to the source region, and a part of the second partial well region is adjacent to the well contact region and the second JFET region respectively; or, the well contact region is adjacent to the source region and the second JFET region respectively.

[0013] Optionally, the cell structure further includes: a Schottky metal covering a part of the second JFET region; an ohmic contact metal covering at least a part of the well contact region and being in contact with the ohmic contact metal. Wherein, when the well contact region is adjacent to the source region and a part of the second partial well region is adjacent to the well contact region and the second JFET region respectively, the ohmic contact metal covers at least a part of the well contact region, a part of the second partial well region adjacent to the well contact region respectively, and a part of the source region. When the well contact region is adjacent to the source region and the second JFET region respectively, the ohmic contact metal covers at least a part of the well contact region and a part of the source region adjacent to the well contact region.

[0014] Optionally, the epitaxial layer has a first surface on a side facing away from the substrate. In the case where the well contact region is adjacent to the source region and the partial second part of the well region is respectively adjacent to the well contact region and the second JFET region, the first surface corresponding to the second JFET region is the first region surface, and the first region surface includes an adjacent first sub-region and a second sub-region. The side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; the first surface corresponding to the second part of the well region is the second region surface, and the second region surface includes an adjacent third sub-region and a fourth sub-region. The third sub-region is the first surface corresponding to the channel region, and the fourth sub-region is the second region surface except the third sub-region; the Schottky metal covers the first sub-region and a part of the fourth sub-region.

[0015] Optionally, the first surface corresponding to the first part of the well region is the third region surface, and the first surface corresponding to the source region is the fourth region surface. At least part of the fourth region surface is located between the second region surface and the third region surface; the part of the first region surface covered by the second gate structure is the fifth sub-region, and the part of the fourth region surface covered by the second gate structure is the sixth sub-region. The third sub-region is located between the fifth sub-region and the sixth sub-region; the first surface corresponding to the first JFET region is the fifth region surface, and the part of the fifth region surface covered by the first gate structure is the seventh sub-region. The third region surface is located between at least part of the fourth region surface and the seventh sub-region.

[0016] Optionally, the epitaxial layer has a first surface on a side facing away from the substrate, and the well region has a first preset pattern in a cross-section parallel to the first surface, and the side line of the first preset pattern is a polygon.

[0017] Optionally, when the polygon is the first rectangle, the second JFET region includes a first sub-JFET region and a second sub-JFET region arranged at intervals, the second partial well region includes a part located between the first sub-JFET region and the second sub-JFET region and another part other than the part, and the well contact region is arranged in the part of the second partial well region located between the first sub-JFET region and the second sub-JFET region; in the direction perpendicular to the connection line of the first sub-JFET region and the second sub-JFET region, the first partial well region includes a first sub-well region located on the left side of the connection line and a second sub-well region located on the right side of the connection line; the Schottky metal includes a first sub-Schottky metal and a second sub-Schottky metal arranged at intervals. When the first sub-JFET region includes a part of the first sub-JFET region close to the second sub-JFET region, a part of the first sub-JFET region far from the second sub-JFET region, and another part of the first sub-JFET region located in the middle of the two parts of the first sub-JFET region, the part of the first sub-JFET region close to the second sub-JFET region in the first sub-JFET region is the first Schottky region, and the first sub-Schottky metal covers at least the first Schottky region. When the second sub-JFET region includes a part of the second sub-JFET region close to the first sub-JFET region, a part of the second sub-JFET region far from the first sub-JFET region, and another part of the second sub-JFET region located in the middle of the two parts of the first sub-JFET region, the part of the second sub-JFET region close to the first sub-JFET region in the second sub-JFET region is the second Schottky region, and the second sub-Schottky metal covers at least the second Schottky region.

[0018] Optionally, the second gate structure includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is located on the side of the first sub-Schottky metal away from the second sub-Schottky metal, and the second sub-gate structure is located on the side of the second sub-Schottky metal away from the first sub-Schottky metal; the part of the first sub-JFET region far from the second sub-JFET region in the first sub-JFET region is the first embedded semiconductor region. The first sub-gate structure covers the first embedded semiconductor region, a part of the second partial well region surrounding the first embedded semiconductor region, and a part of the source region surrounding the first embedded well region. The first embedded well region is a part of the second partial well region adjacent to the first embedded semiconductor region; the part of the second sub-JFET region far from the first sub-JFET region in the second sub-JFET region is the second embedded semiconductor region. The second sub-gate structure covers the second embedded semiconductor region, a part of the second partial well region surrounding the second embedded semiconductor region, and a part of the source region surrounding the second embedded well region. The second embedded well region is a part of the second partial well region adjacent to the second embedded semiconductor region.

[0019] Optionally, the first gate structure includes a third sub-gate structure and a fourth sub-gate structure. The third sub-gate structure is located on the left side, and the fourth sub-gate structure is located on the right side. The third sub-gate structure is in contact with the first sub-gate structure and the second sub-gate structure respectively, and both the first sub-gate structure and the second sub-gate structure are also in contact with the fourth sub-gate structure. The source region includes a partial source region of the second partial well region far from the second JFET region and close to the first sub-well region, and a partial source region of the second partial well region far from the second JFET region and close to the second sub-well region. The third sub-gate structure covers the partial source region of the second partial well region far from the second JFET region and close to the first sub-well region, and the third sub-gate structure also covers the first sub-well region and a partial first JFET region located on the side of the first sub-well region far from the first sub-JFET region and the second JFET region. The fourth sub-gate structure covers the partial source region of the second partial well region far from the second JFET region and close to the second sub-well region, and the fourth sub-gate structure also covers the second sub-well region and a partial first JFET region located on the side of the second sub-well region far from the first sub-JFET region and the second JFET region.

[0020] Optionally, the epitaxial layer has a first surface on the side facing away from the substrate. The first surface has grooves, and at least part of the well region extends from a partial surface of the grooves into the epitaxial layer.

[0021] Optionally, the contact surface between the second partial well region and the gate structure includes the {0-33-8} crystal plane.

[0022] Optionally, the first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from a partial bottom surface of the grooves into the epitaxial layer.

[0023] Optionally, the first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from the entire bottom surface of the grooves into the epitaxial layer.

[0024] Optionally, the first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from the entire bottom surface and partial side walls of the grooves into the epitaxial layer.

[0025] Optionally, the first surface corresponding to the grooves includes a bottom surface and side walls, and the cell structure further includes: a silicon oxide layer covering the side walls of the grooves where part of the second partial well region is located.

[0026] Optionally, when the polygon is the second rectangle, the well contact region includes a first partial well contact region, a second partial well contact region, and a third partial well contact region that are adjacently arranged. The first partial well contact region, the second partial well contact region, and the third partial well contact region are respectively located on three sides of the second JFET region; when the well contact region is adjacent to the source region and a part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, a part of the second partial well region is respectively adjacent to the first partial well contact region and the second JFET region, a part of the second partial well region is respectively adjacent to the second partial well contact region and the second JFET region, and a part of the second partial well region is respectively adjacent to the third partial well contact region and the second JFET region; when the well contact region is respectively adjacent to the source region and the second JFET region, the second JFET region is respectively adjacent to the first partial well contact region, the second partial well contact region, and the third partial well contact region.

[0027] Optionally, the second JFET region has a third rectangle in a cross-section parallel to the first surface, and the third rectangle is located within the second rectangle; the first JFET region surrounds the well region, the second JFET region has a first end and a second end opposite to each other in a first direction, and the first direction is parallel to the first surface; the source region surrounds the second partial well region, and the first partial well region surrounds the source region; the Schottky metal covers a part of the second JFET region at the first end, and the Schottky metal also covers a part of the second partial well region in contact with the third Schottky region. The third Schottky region is a part of the second JFET region whose first end is covered by the Schottky metal. The well contact region is located in the second partial well region and semi-surrounds the second JFET region at the first end; the second gate structure covers the third embedded semiconductor region, a part of the second partial well region surrounding the third embedded semiconductor region, and a part of the source region surrounding the third embedded well region. The third embedded semiconductor region is a part of the second JFET region at the second end, and the third embedded well region is a part of the second partial well region adjacent to the third embedded semiconductor region; the source region includes a part of the source region surrounding the second JFET region and close to the first partial well region and a part of the source region surrounding the second JFET region and close to the second partial well region. The first gate structure surrounds the second JFET region, the second gate structure is located on a side of the first gate structure close to the second JFET region, and the first gate structure covers a part of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region, and a part of the first JFET region surrounding the outer periphery of the well region.

[0028] Optionally, when the polygon is the first hexagon or the first octagon, the well contact region includes a fourth partial well contact region and a fifth partial well contact region that are spaced apart, and the fourth partial well contact region and the fifth partial well contact region are respectively located on opposite sides of the second JFET region; when the well contact region is adjacent to the source region and a part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, a part of the second partial well region is located between the fourth partial well contact region and the second JFET region, and a part of the second partial well region is located between the fifth partial well contact region and the second JFET region; when the well contact region is respectively adjacent to the source region and the second JFET region, the fourth partial well contact region is respectively adjacent to a part of the source region and the second JFET region, and the fifth partial well contact region is respectively adjacent to a part of the source region and the second JFET region.

[0029] Optionally, when the polygon is the first hexagon, the second JFET region has a first irregular figure in a cross-section parallel to the first surface, the first irregular figure is located in the first hexagon, the first irregular figure includes a second hexagon and two first preset patterns, the two first preset patterns are respectively in contact with opposite sides of the second hexagon in the second direction, and the second direction is parallel to the first surface; the first JFET region surrounds the well region, the second JFET region has a first part, a second part, and a third part that are in contact in the second direction, the second part is located between the first part and the third part, the second partial well region is respectively in contact with a side of the first part away from the second part and a side of the third part away from the second part, the first part and the third part correspond to the two first preset patterns one by one, and the second part corresponds to the second hexagon; the source region surrounds the second partial well region, and the first partial well region surrounds the source region; the Schottky metal covers at least a part of the second part; the well contact region includes a first doped region and a second doped region, the first doped region and the second doped region are located on opposite sides of the second JFET region in a direction perpendicular to the second direction, the source region, the second partial well region, and the first part are sequentially adjacent in the second direction, the source region, the second partial well region, and the third part are sequentially adjacent in the second direction, the source region, the first doped region, the second partial well region, and the second part are sequentially adjacent in a direction perpendicular to the second direction, and the source region, the second doped region, the second partial well region, and the second part are sequentially adjacent in a direction perpendicular to the second direction.

[0030] Optionally, the second gate structure includes a fifth sub-gate structure and a sixth sub-gate structure located on opposite sides of the Schottky metal in the second direction; the first part includes a partial first part close to the second part well region and far from the second part and a partial first part close to the second part and far from the second part well region. The fifth sub-gate structure covers the fourth embedded semiconductor region, a part of the second part well region in contact with the fourth embedded semiconductor region, and a part of the source region in contact with the fourth embedded well region. The fourth embedded semiconductor region is the partial first part close to the second part well region and far from the second part, and the fourth embedded well region is the part of the second part well region located on the side of the first part far from the second part; the third part includes a partial third part close to the second part well region and far from the second part and a partial third part close to the second part and far from the second part well region. The sixth sub-gate structure covers the fifth embedded semiconductor region, a part of the second part well region in contact with the fifth embedded semiconductor region, and a part of the source region in contact with the fifth embedded well region. The fifth embedded semiconductor region is the partial third part close to the second part well region and far from the second part, and the fifth embedded well region is the part of the second part well region located on the side of the third part far from the second part; the source region includes a part of the source region surrounding the second JFET region and close to the first part well region and a part of the source region surrounding the second JFET region and close to the second part well region. The first gate structure surrounds the second JFET region. The fifth sub-gate structure is located on one side of the first gate structure close to the second JFET region, and the fifth sub-gate structure covers the part of the source region, the second part well region, and the partial first part that are sequentially adjacent in the second direction. The sixth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the sixth sub-gate structure covers the part of the source region, the second part well region, and the partial third part that are sequentially adjacent in the second direction. The first gate structure covers the part of the source region surrounding the second JFET region and close to the first part well region, the first part well region, and a part of the first JFET region surrounding the outer periphery of the well region.

[0031] Optionally, when the polygon is the first octagon, the second JFET region has a second irregular figure in a cross-section parallel to the first surface. The second irregular figure is located within the first octagon and includes a second octagon and two second preset patterns. The two second preset patterns are in contact with opposite sides of the second octagon in a third direction parallel to the first surface. The first JFET region surrounds the well region. The second JFET region has a fourth part, a fifth part, and a sixth part in contact and arranged in the third direction. The fifth part is located between the fourth part and the sixth part. The sides of the fourth part away from the fifth part and the sixth part away from the fifth part are respectively in contact with the second part of the well region. The fourth part and the sixth part correspond one-to-one with the two second preset patterns, and the fifth part corresponds to the second octagon. The source region surrounds the second part of the well region, and the first part of the well region surrounds the source region. The Schottky metal covers the fifth part. The well contact region includes a third doped region and a fourth doped region. The third doped region and the fourth doped region are located on opposite sides of the second JFET region in a direction perpendicular to the third direction. The source region, the second part of the well region, and the fourth part are adjacent in sequence in the third direction. The source region, the second part of the well region, and the sixth part are adjacent in sequence in the third direction. The source region, the third doped region, the second part of the well region, and the fourth part are adjacent in sequence in a direction perpendicular to the third direction. The source region, the fourth doped region, the second part of the well region, and the sixth part are adjacent in sequence in a direction perpendicular to the third direction.

[0032] Optionally, the second gate structure includes a seventh sub-gate structure and an eighth sub-gate structure located on opposite sides of the Schottky metal in the third direction; the fourth part includes a partial fourth part close to the second part well region and far from the fifth part and a partial fourth part close to the fifth part and far from the second part well region. The seventh sub-gate structure covers the sixth embedded semiconductor region, a part of the second part well region in contact with the sixth embedded semiconductor region, and a part of the source region in contact with the sixth embedded well region. The sixth embedded semiconductor region is the partial fourth part close to the second part well region and far from the fifth part, and the sixth embedded well region is the part of the second part well region on the side of the fourth part far from the fifth part; the sixth part includes a partial sixth part close to the second part well region and far from the fifth part and a partial sixth part close to the fifth part and far from the second part well region. The eighth sub-gate structure covers the seventh embedded semiconductor region, a part of the second part well region in contact with the seventh embedded semiconductor region, and a part of the source region in contact with the seventh embedded well region. The seventh embedded semiconductor region is the partial sixth part close to the second part well region and far from the fifth part, and the seventh embedded well region is the part of the second part well region on the side of the sixth part far from the fifth part; the source region includes a part of the source region surrounding the second JFET region and close to the first part well region and a part of the source region surrounding the second JFET region and close to the second part well region. The first gate structure surrounds the second JFET region. The seventh sub-gate structure is located on one side of the first gate structure close to the second JFET region, and the seventh sub-gate structure covers the source region, the second part well region, and a partial fourth part that are sequentially adjacent in the third direction. The eighth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the eighth sub-gate structure covers the source region, the second part well region, and a partial sixth part that are sequentially adjacent in the third direction. The first gate structure covers a part of the source region surrounding the second JFET region and close to the first part well region, the first part well region, and a part of the first JFET region surrounding the well region.

[0033] Applying the technical solution of the present invention, a cell structure of a MOSFET device, the cell structure includes a substrate, an epitaxial layer on one side of the substrate, and a cell region located in the epitaxial layer. The cell region includes: a first JFET region and a second JFET region arranged at intervals, and the first JFET region is at least on both sides of the second JFET region; a well region located between the first JFET region and the second JFET region, and the conductivity type of the well region is opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, the well region between the source region and the first JFET region is the first partial well region, and the well region between the source region and the second JFET region is the second partial well region; a well contact region located in a part of the second partial well region, so that a channel region adjacent to the source region and the second JFET region respectively is formed in the remaining second partial well region. The doping type of the well contact region is the same as that of the well region, and the doping concentration of the well contact region is higher than that of the well region; a gate structure includes an adjacent first gate structure and a second gate structure. The first gate structure covers the first partial well region, a part of the source region adjacent to the first partial well region respectively, and at least part of the first JFET region. The second gate structure covers a part of the channel region, a part of the source region adjacent to the part of the channel region respectively, and a part of the second JFET region.

[0034] It can be seen that the present application can integrate a Schottky diode in a MOSFET device. Since the turn-on voltage of the Schottky diode is lower than that of the traditional body diode, the turn-on is greatly reduced, thereby improving the problem of the relatively high turn-on voltage of the traditional MOSFET through the present application, which is beneficial to the conduction of the reverse current in the MOSFET. Moreover, since the conduction of the Schottky diode has unipolar conductivity, it can avoid the bipolar degradation effect when the MOSFET is under a small current density and the PN junction has not started to inject, and at the same time, it can reduce the reverse recovery current and reverse recovery loss. In addition, when the first gate structure covers the first part of the well region and the part of the source region and at least part of the first JFET region adjacent to the first part of the well region respectively, a first conductive channel can be formed in the first part of the well region. When the second gate structure covers the channel region in the second part of the well region and the part of the source region and part of the second JFET region adjacent to the part of the channel region respectively, a second conductive channel can be formed in the second part of the well region. That is, by integrating a hybrid PIN Schottky diode (MPS) in the well region of the MOSFET device in the present application, while not increasing the cell width in the MOSFET device and retaining the original first conductive channel in the MOSFET device, the channel width in the MOSFET device is increased through the above-mentioned second conductive channel. Furthermore, during the forward conduction of the MOSFET device, the current density below the well region and the second JFET region of the MOSFET device can be increased, so that the MOSFET device has good forward conduction characteristics. Based on this, the present application solves the technical problems of the large reverse current turn-on voltage and high reverse recovery loss of the body diode of the existing MOSFET when used as a freewheeling path. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The specification drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0036] Figure 1 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to a first embodiment of the present invention in the A-A' direction;

[0037] Figure 2 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to a first embodiment of the present invention in the B-B' direction;

[0038] Figure 3 FIG. shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to a second embodiment of the present invention in the B-B' direction;

[0039] Figure 4Shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to the third embodiment of the present invention in the B-B' direction;

[0040] Figure 5 Shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to the fourth embodiment of the present invention in the B-B' direction;

[0041] Figure 6 Shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided according to the fifth embodiment of the present invention in the B-B' direction;

[0042] Figure 7 Shows a perspective view of a cell structure of a MOSFET device provided according to the first embodiment of the present invention in the direction of the first surface of the vertical epitaxial layer;

[0043] Figure 8 Shows in Figure 7 On the basis of the shown structure, a perspective view after covering the gate structure and the ohmic contact metal;

[0044] Figure 9 Shows a perspective view of a cell structure of a MOSFET device provided according to the sixth embodiment of the present invention in the direction of the first surface of the vertical epitaxial layer;

[0045] Figure 10 Shows in Figure 9 On the basis of the shown structure, a perspective view after covering the gate structure and the ohmic contact metal;

[0046] Figure 11 Shows a perspective view of a cell structure of a MOSFET device provided according to the seventh embodiment of the present invention in the direction of the first surface of the vertical epitaxial layer;

[0047] Figure 12 Shows in Figure 10 On the basis of the shown structure, a perspective view after covering the gate structure and the ohmic contact metal;

[0048] Figure 13 Shows a perspective view of a cell structure of a MOSFET device provided according to the eighth embodiment of the present invention in the direction of the first surface of the vertical epitaxial layer;

[0049] Figure 14 Shows in Figure 13 On the basis of the shown structure, a perspective view after covering the gate structure and the ohmic contact metal;

[0050] Figure 15Shows a perspective view of the cell structure of a MOSFET device provided according to the eighth embodiment of the present invention in the direction of the first surface of the vertical epitaxial layer;

[0051] Figure 16 Shows, after Figure 15 forming ohmic contact metal on the basis of the structure, a perspective view.

[0052] Among them, the above-mentioned drawings include the following reference numerals:

[0053] 100, substrate; 101, silicon carbide material layer; 102, silicon oxide layer; 200, epitaxial layer; 201, first sub-epitaxial layer; 202, second sub-epitaxial layer; 203, JFET doping region; 300, well region; 301, second part of the well region; 3011, channel region; 302, first part of the well region; 400, source region; 500, well contact region; 601, ohmic contact metal; 602, Schottky metal; 6021, first sub-Schottky metal; 6022, second sub-Schottky metal; 700, gate structure; 701, polysilicon; 702, gate oxide layer; 703, dielectric layer; 800, back metal layer; 900, front metal layer; 10, second JFET region; 11, first sub-JFET region; 12, second sub-JFET region; 20, first JFET region; 30, second gate structure; 40, first gate structure. Detailed implementation manners

[0054] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0055] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0057] As described in the background art, when the body diode of the MOSFET in the prior art is used as a freewheeling path, the reverse freewheeling turn-on voltage is large and the reverse recovery loss is high. In order to at least solve the above technical problems, the present application provides a MOSFET device.

[0058] According to one aspect of the present invention, a cell structure of a MOSFET device is provided, as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 shown, the cell structure includes a substrate 100, an epitaxial layer 200 and a cell region. The epitaxial layer 200 is located on one side of the substrate 100. The epitaxial layer 200 has a first surface 1a facing away from the substrate 100, and the cell region extends from the first surface 1a into the epitaxial layer 200. Among them, in combination with Figure 1 , Figure 2 and Figure 3 shown, the cell region includes a first JFET region 20, a second JFET region 10, a well region 300, a source region 400, a well contact region 500 and a gate structure 700. Further, the first JFET region 20 is at least located on both sides of the second JFET region 10. Further, each cell region may include one or more second JFET regions 10. In the case where the second JFET region 10 includes two, as Figure 7 shown, the second JFET region 10 may include a first sub-JFET region 11 and a second sub-JFET region 12 arranged at intervals.

[0059] Specifically, as Figures 1 to 6 shown, the side of the substrate 100 facing away from the epitaxial layer 200 has a second surface 1b. The above MOSFET device further includes a back metal layer 800 located on the second surface 1b and an ohmic contact metal 601 and a Schottky metal 602 located on the first surface 1a.

[0060] Specifically, both the stacked substrate 100 and the epitaxial layer 200 can be silicon carbide material layers 101.

[0061] Specifically, the substrate 100 can be 4H-SiC, and the doping concentration can be 5E18 - 5E21 cm -3 , and the thickness can be 50 - 500 μm.

[0062] Specifically, as Figures 1 to 6 shown, the epitaxial layer 200 can include a first sub-epitaxial layer 201, a second sub-epitaxial layer 202, and a JFET doping region 203 that are stacked in the direction perpendicular to the first surface 1a. Here, it should be noted that the JFET doping region 203 can be regarded as the second JFET region 10 as Figure 7 shown.

[0063] Optionally, the above-mentioned first sub-epitaxial layer 201, second sub-epitaxial layer 202, and JFET doping region 203 can all be formed by an epitaxial process.

[0064] Optionally, the above-mentioned first sub-epitaxial layer 201 and second sub-epitaxial layer 202 can be formed by an epitaxial process, and the above-mentioned JFET doping region 203 can be obtained by ion implantation.

[0065] Among them, the first sub-epitaxial layer 201 can be a field stop layer. The second sub-epitaxial layer 202 can be a drift layer. The JFET doping region 203 can be a junction field-effect transistor (JFET).

[0066] Specifically, the doping concentration of the JFET doping region 203 can be greater than the doping concentration of the second sub-epitaxial layer 202.

[0067] Specifically, the doping concentration of the first sub-epitaxial layer 201 can be 5E15 - 1E19 cm -3 , and the thickness can be 5 - 50 μm.

[0068] Specifically, the doping concentration of the second sub-epitaxial layer 202 can be 1E15 - 5E17 cm -3 , and the thickness can be 5 - 100 μm.

[0069] Specifically, the doping concentration of the JFET doping region 203 can be 5E15 - 1E18 cm -3 , and the thickness can be 0.5 - 5 μm.

[0070] Combined with Figure 1 , Figure 2 and Figure 7As shown, the well region 300 is located between the first JFET region 20 and the second JFET region 10, and the conductivity type of the well region 300 is opposite to that of the epitaxial layer 200; the source region 400 is located in the well region 300 and the source region 400 surrounds the second JFET region 10. Further, the well region 300 between the source region 400 and the first JFET region 20 is the first partial well region 302, and the well region 300 between the source region 400 and the second JFET region 10 is the second partial well region 301; the well contact region 500 is located in a part of the second partial well region 301, so that a channel region 3011 (it can be understood that the channel region 3011 is a part of the second partial well region 301) adjacent to the source region 400 and the second JFET region 10 respectively is formed in the remaining second partial well region 301. The conductivity type of the well contact region 500 is the same as that of the well region 300, and the doping concentration of the well contact region 500 is higher than that of the well region 300.

[0071] Specifically, the first partial well region 302 and the second partial well region 301 in the above MOSFET device can be connected in the epitaxial layer 200.

[0072] Specifically, the doping concentration of the well region 300 can be 1e16 - 5e19 cm -3 , and the implantation depth can be 0.5 - 5 μm; the doping concentration of the well contact region 500 can be 5e17 - 5e21 cm -3 , and the implantation depth can be 0.3 - 5 μm.

[0073] Specifically, the doping concentration of the source region 400 can be 1e18 - 5E21 cm -3 , and the implantation depth is 0.1 - 3 μm.

[0074] Combined with Figure 2 and Figure 8 shown, in order to form a Schottky barrier in the region corresponding to the second JFET region 10, the Schottky metal 602 can cover a part of the second JFET region 10.

[0075] Optionally, the material of the Schottky metal 602 includes but is not limited to any one or more of Ti, Al, W, Mo, TiC, TiW, NiCr, Au, and Ni. Exemplarily, the thickness of the Schottky metal 602 is 0.01 - 1 μm.

[0076] In some embodiments, in order to reduce the ohmic contact resistance, the ohmic contact metal 601 is located on the first surface, and the ohmic contact metal 601 can cover at least a part of the well contact region 500. Specifically, as Figure 8 shown, the ohmic contact metal 601 can completely cover the well contact region 500; or, as Figure 10 , Figure 12 and Figure 14As shown, the ohmic contact metal 601 can cover a part of the well contact region 500. Further, as Figure 8 、 Figure 10 、 Figure 12 and Figure 14 shown, the ohmic contact metal 601 and the Schottky metal 602 can be arranged in contact with each other.

[0077] Optionally, the material of the above-mentioned ohmic contact metal 601 is selected from any one or a combination of more than one of Ni, Ti, Al, Ag, Au, AlSi, Pt, Pd, Ta, and Co.

[0078] Optionally, the thickness of the above-mentioned ohmic contact metal 601 on the first surface is 0.01 - 1 μm.

[0079] Combined with Figure 1 、 Figure 7 and Figure 8 shown, the gate structure 700 can be located on the first surface 1a and be arranged at intervals from the ohmic contact metal 601. The gate structure 700 includes an adjacent first gate structure 40 and a second gate structure 30. Among them, the first gate structure 40 covers the first part of the well region 302 and the part of the source region 400 and at least part of the first JFET region 20 that are respectively adjacent to the first part of the well region 302. The second gate structure 30 covers the part of the channel region 3011 and the part of the source region 400 and the part of the second JFET region 10 that are respectively adjacent to the part of the channel region 3011.

[0080] Specifically, as Figure 1 、 Figure 2 and Figure 3 shown, the gate structure 700 can include polysilicon 701, a gate oxide layer 702, and a dielectric layer 703.

[0081] Among them, the gate oxide layer 702 can be formed by thermal oxidation, depositing SiO2, or oxidizing after depositing Si. Exemplarily, the thickness of the gate oxide layer 702 can be 10 - 200 nm. The polysilicon 701 is formed by depositing on the gate oxide layer 702 and then performing phosphorus implantation and diffusion. Exemplarily, the doping concentration of the polysilicon 701 can be 1e19 - 1e20 cm -3 , and the thickness of the polysilicon 701 can be 0.1 - 1 μm. Exemplarily, the thickness of the dielectric layer 703 can be 0.5 - 5 μm.

[0082] It can be understood that the above-mentioned Schottky metal 602, epitaxial layer 200, substrate 100, and back metal layer 800 can form a Schottky diode.

[0083] Specifically, as Figures 3 to 6As shown, the above MOSFET device may further include a front metal layer 900, which is located on the side of the Schottky metal 602 away from the epitaxial layer 200.

[0084] Exemplarily, the material of the front metal layer 900 includes, but is not limited to, any one or more of Al, Au, Cu, and Si. The thickness of the front metal layer 900 can be 0.1 - 1 μm.

[0085] In summary, the present application can integrate a Schottky diode in a MOSFET device. Since the turn - on voltage of the Schottky diode is lower than that of the traditional bulk diode, the turn - on is greatly reduced, thereby improving the problem of the relatively high turn - on voltage of the traditional MOSFET through the present application, which is beneficial to the conduction of the reverse current in the MOSFET. And, since the conduction of the Schottky diode has unipolar conductivity, it can avoid the bipolar degradation effect when the MOSFET is at a low current density and the PN junction has not started to inject, and at the same time, it can reduce the reverse recovery current and reverse recovery loss. Additionally, when the first gate structure 40 covers the first part of the well region 302 and the part of the source region 400 and at least part of the first JFET region 20 adjacent to the first part of the well region 302 respectively, a first conductive channel can be formed in the first part of the well region 302. When the second gate structure 30 covers the channel region 3011 in the second part of the well region 301 and the part of the source region 400 and part of the second JFET region 10 adjacent to the part of the channel region 3011 respectively, a second conductive channel (the above - mentioned channel region 3011) can be formed in the second part of the well region 301. That is, the present application integrates a hybrid PIN Schottky diode (MPS) in the well region 300 of the MOSFET device, so that while not increasing the cell width in the MOSFET device and retaining the original first conductive channel in the MOSFET device, the channel width in the MOSFET device is increased. Furthermore, during the forward conduction of the MOSFET device, the current density below the well region 300 and the Schott contact region (the second JFET region 10) of the MOSFET device can be increased, enabling the MOSFET device to have good forward conduction characteristics. Based on this, the present application solves the technical problems of the large reverse - flow turn - on voltage and high reverse recovery loss of the body diode of the existing MOSFET when used as a free - wheeling path.

[0086] Under small - injection conditions, that is, when the device operates at a low current density, to further reduce the reverse recovery loss of the body diode in the device and further improve the overall characteristics of the device. In some embodiments, such as Figures 9 to 12As shown, the well contact region 500 is adjacent to the source region 400, and the partial second part well region 301 is respectively adjacent to the well contact region 500 and the second JFET region 10; on this basis, the above-mentioned ohmic contact metal 601 can also cover the partial second part well region 301 and the partial source region 400 that are respectively adjacent to the well contact region 500.

[0087] Under high injection conditions, that is, when the device operates at a high current density, to further reduce the on-voltage drop of the body diode in the device. In some other embodiments, such as Figure 13 and Figure 14 As shown, the well contact region 500 can be adjacent to the source region 400 and the second JFET region 10 respectively. On this basis, the above-mentioned ohmic contact metal 601 can also cover the partial source region 400 that is respectively adjacent to the well contact region 500. However, for any of the above embodiments, the partial second part well region 301 is also respectively adjacent to the source region 400 and the second JFET region 10 to form the above-mentioned channel region 3011.

[0088] In some alternative embodiments, such as Figures 7 to 14 As shown, in order to optimize the electrical performance of the MOSFET, improve the breakdown voltage capability, reduce the electric field concentration, and achieve good ohmic contact and conductance modulation effects, the second JFET region 10 extends from the first surface into the epitaxial layer, so that the first surface corresponding to the second JFET region 10 is the first region surface, and the first region surface includes an adjacent first sub-region and a second sub-region. The side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; the second part well region 301 extends from the first surface into the epitaxial layer, so that the first surface corresponding to the second part well region 301 is the second region surface, and the second region surface includes an adjacent third sub-region and a fourth sub-region. The third sub-region is the first surface corresponding to the channel region 3011, and the fourth sub-region is the second region surface other than the third sub-region; when the well contact region is adjacent to the source region and the second JFET region respectively, the Schottky metal 602 covers the first sub-region, or when the well contact region is adjacent to the source region and the partial second part well region is respectively adjacent to the well contact region and the second JFET region, the Schottky metal 602 covers the first sub-region and the partial fourth sub-region.

[0089] In some alternative embodiments, in combination with Figures 7 to 14As shown, the first part of the well region 302 extends from the first surface into the epitaxial layer, such that the first surface corresponding to the first part of the well region 302 is the surface of the third region; the source region 400 extends from the first surface into the well region 300, such that the first surface corresponding to the source region 400 is the surface of the fourth region, and at least a part of the fourth region surface is located between the second region surface and the third region surface; the part of the first region surface covered by the second gate structure 30 is the fifth sub-region, the part of the fourth region surface covered by the second gate structure 30 is the sixth sub-region, and the third sub-region is located between the fifth sub-region and the sixth sub-region; the first JFET region 20 extends from the first surface into the epitaxial layer, such that the first surface corresponding to the first JFET region 20 is the surface of the fifth region, and the part of the fifth region surface covered by the first gate structure 40 is the seventh sub-region, and the third region surface is located between at least a part of the fourth region surface and the seventh sub-region. Thus, it can be seen that there is a first conductive channel in the first part of the well region 302 covered by the first gate structure 40 and located between the first JFET region 20 and the source region 400, and there is a second conductive channel in the second part of the well region 301 covered by the second gate structure 30 and located between the second JFET region 10 and the source region 400.

[0090] Optionally, as Figures 7 to 14 shown, the well region 300 (the first part of the well region 302 and / or the second part of the well region 301) has a first preset pattern in a cross-section parallel to the first surface, and the side lines of the first preset pattern are polygons (the figure enclosed by the side lines presents as a polygon in the first surface).

[0091] Exemplarily, as Figure 7 and Figure 8 shown, the first preset pattern is a first rectangle, the second JFET region 10 includes a first sub-JFET region 11 and a second sub-JFET region 12, the second part of the well region 301 includes a part located between the first sub-JFET region 11 and the second sub-JFET region 12, and another part other than the part located between the first sub-JFET region 11 and the second sub-JFET region 12, and the well contact region 500 is arranged in the part of the second part of the well region 301 located between the first sub-JFET region 11 and the second sub-JFET region 12. It can be seen that the other part of the second part of the well region 301 other than the part located between the first sub-JFET region 11 and the second sub-JFET region 12 is located around the first sub-JFET region 11 and the second sub-JFET region 12.

[0092] As Figure 7 and Figure 8As shown, in the direction perpendicular to the connection line of the first sub-JFET region 11 and the second sub-JFET region 12 (i.e., the direction of A-A'), the first part of the well region 302 includes a first sub-well region (not labeled in the figure) and a second sub-well region (not labeled in the figure). The first sub-well region is respectively located on the left side of the first sub-JFET region 11 and the second sub-JFET region 12, and the second sub-well region is respectively located on the right side of the first sub-JFET region 11 and the second sub-JFET region 12. It can be understood that the above-mentioned left and right sides are the relative two sides of the connection line of the first sub-JFET region 11 and the second sub-JFET region 12.

[0093] As Figure 7 and Figure 8 shown, the Schottky metal 602 includes a first sub-Schottky metal 6021 and a second sub-Schottky metal 6022 which are arranged at intervals. Specifically, when the first sub-JFET region 11 includes a part of the first sub-JFET region 11 close to the second sub-JFET region 12 (in the B-B' direction), a part of the first sub-JFET region 11 far from the second sub-JFET region 12, and another part of the first sub-JFET region 11 located in the middle of the above two parts of the first sub-JFET region 11, the part of the first sub-JFET region 11 close to the second sub-JFET region 12 in the first sub-JFET region 11 can be regarded as the first Schottky region, and the first sub-Schottky metal 6021 covers the first Schottky region or the first sub-Schottky metal 6021 covers the first Schottky region and a part of the second part of the well region 301 in contact with the first Schottky region. It can be understood that when the first sub-JFET region 11 includes a part of the first sub-JFET region 11 close to the second sub-JFET region 12 (in the B-B' direction), a part of the first sub-JFET region 11 far from the second sub-JFET region 12, and another part of the first sub-JFET region 11 located in the middle of the above two parts of the first sub-JFET region 11, the other part of the first sub-JFET region 11 located in the middle of the above two parts of the first sub-JFET region 11 may not be covered by the first sub-Schottky metal 6021.

[0094] As Figure 7 and Figure 8As shown, when the second sub-JFET region 12 includes (in the B-B' direction) a part of the second sub-JFET region 12 on the side close to the first sub-JFET region 11, a part of the second sub-JFET region 12 on the side far from the first sub-JFET region 11, and another part of the second sub-JFET region 12 located between the above two parts of the first sub-JFET region 11, the part of the second sub-JFET region 12 close to the first sub-JFET region 11 in the second sub-JFET region 12 can be regarded as the second Schottky region, and the second sub-Schottky metal 6022 covers the second Schottky region or the second sub-Schottky metal 6022 covers the second Schottky region and a part of the second part well region 301 in contact with the second Schottky region. It can be understood that when the second sub-JFET region 12 includes (in the B-B' direction) a part of the second sub-JFET region 12 on the side close to the first sub-JFET region 11, a part of the second sub-JFET region 12 on the side far from the first sub-JFET region 11, and another part of the second sub-JFET region 12 located between the above two parts of the first sub-JFET region 11, another part of the second sub-JFET region 12 located between the above two parts of the second sub-JFET region may not be covered by the second sub-Schottky metal 6022.

[0095] In some embodiments, in combination with Figure 7 and Figure 8 As shown, the ohmic contact metal 601 can be one, and the ohmic contact metal 601 is located on one side of the Schottky metal 602 (the first sub-Schottky metal 6021 or the second sub-Schottky metal 6022), and the ohmic contact metal 601 can cover the well contact region 500 and a part of the source region 400.

[0096] Alternatively, in some other embodiments, the ohmic contact metal 601 can be one. The well contact region 500 has partial second part well regions 301 on both sides in the A-A' direction, that is, in the A-A' direction, the partial second part well regions 301 are located between the well contact region 500 and the source region 400. At this time, the ohmic contact metal 601 can cover the well contact region 500, a part of the second part well region 301, and a part of the source region 400.

[0097] In some other embodiments, the ohmic contact metal 601 can be one. The well contact region 500 has two contact regions arranged at intervals in the B-B' direction, and each contact region has partial second part well regions 301 on both sides in the B-B' direction. At this time, the ohmic contact metal 601 can cover the above two contact regions, a part of the second part well region 301, and a part of the source region 400.

[0098] As Figure 8As shown, the second gate structure 30 may include a first sub-gate structure (not labeled in the figure) and a second sub-gate structure (not labeled in the figure). The first sub-gate structure is located on the side of the first sub-Schottky metal 6021 away from the second sub-Schottky metal 6022, and the second sub-gate structure is located on the side of the second sub-Schottky metal 6022 away from the first sub-Schottky metal 6021.

[0099] As Figure 7 and Figure 8 shown, a part of the first sub-JFET region 11 in the first sub-JFET region 11 away from the second sub-JFET region 12 is a first embedded semiconductor region. The first sub-gate structure covers the first embedded semiconductor region, a part of the second part well region 301 surrounding the first embedded semiconductor region, and a part of the source region 400 surrounding the first embedded well region. The first embedded well region is a part of the second part well region 301 adjacent to the first embedded semiconductor region; (in other words, the first sub-gate structure covers the first embedded semiconductor region, a part of the second part well region 301 adjacent to the first embedded semiconductor region, and a part of the source region 400 located on the side of the part of the second part well region 301 adjacent to the first embedded semiconductor region away from the first embedded semiconductor region); a part of the second sub-JFET region 12 in the second sub-JFET region 12 away from the first sub-JFET region 11 is a second embedded semiconductor region. The second sub-gate structure covers the second embedded semiconductor region, a part of the second part well region 301 surrounding the second embedded semiconductor region, and a part of the source region 400 surrounding the second embedded well region. The second embedded well region is a part of the second part well region 301 adjacent to the second embedded semiconductor region (in other words, the second sub-gate structure covers the second embedded semiconductor region, a part of the second part well region 301 adjacent to the second embedded semiconductor region, and a part of the source region 400 located on the side of the part of the second part well region 301 adjacent to the second embedded semiconductor region away from the second embedded semiconductor region). It can be understood that for the part of the first sub-JFET region 11 not covered by the first sub-Schottky metal 6021, there is still a part of this part of the first sub-JFET region 11 not covered by the above-mentioned first sub-gate structure.

[0100] As Figure 8 shown, the first gate structure 40 may include a third sub-gate structure (not labeled in the figure) and a fourth sub-gate structure (not labeled in the figure). The third sub-gate structure is located on the left side of the line connecting the first sub-JFET region 11 and the second sub-JFET region 12, and the fourth sub-gate structure is located on the right side of the line connecting the first sub-JFET region 11 and the second sub-JFET region 12. The third sub-gate structure is in contact with the first sub-gate structure and the second sub-gate structure respectively, and the fourth sub-gate structure is also in contact with the first sub-gate structure and the second sub-gate structure respectively.

[0101] Combined Figure 7 and Figure 8As shown, the source region 400 includes a partial source region 400 of the second part well region 301 that is away from the second JFET region 10 and close to the first sub-well region side, and a partial source region 400 of the second part well region 301 that is away from the second JFET region 10 and close to the second sub-well region side. The third sub-gate structure covers the partial source region 400 of the second part well region 301 that is away from the second JFET region 10 and close to the first sub-well region side, and the third sub-gate structure also covers the first sub-well region and a partial first JFET region 20 that is on the same side of the first sub-well region away from the first sub-JFET region 11 and the second sub-JFET region 12.

[0102] As Figure 7 and Figure 8 shown, the fourth sub-gate structure covers the partial source region 400 of the second part well region 301 that is away from the second JFET region 10 and close to the second sub-well region side, and the fourth sub-gate structure also covers the second sub-well region and a partial first JFET region 20 that is on the same side of the second sub-well region away from the first sub-JFET region 11 and the second sub-JFET region 12.

[0103] In some other alternative embodiments, as Figure 15 shown, the source region surrounding the second JFET region 10 may include portions on opposite sides of the second JFET region 10 in the A-A' direction and portions on both sides of the second JFET region 10 in the B-B' direction. To further improve the ohmic contact, there are partial well contact regions 500 in the portions of the source region on both sides of the second JFET region 10 in the B-B' direction, and as Figure 16 shown, a partial ohmic contact metal 601 covers the partial well contact region 500 and a partial source region 400 adjacent to the partial well contact region 500.

[0104] Specifically, in combination with Figure 2 and Figure 7 and Figure 8 shown, the above-mentioned well contact region 500, the second JFET region 10 (JFET doping region 203), and the Schottky metal 602 can form a hybrid PIN Schottky diode (MPS), so that a hybrid PIN Schottky diode (MPS) can be integrated in the MOSFET device. In addition, the doping concentration of the well contact region 500 can be higher than the doping concentration of the well region 300. Thus, after the well contact region 500 is formed by injection in the well region 300, a PN junction is added to the MOSFET device on the basis of the Schottky barrier diode. This PN junction will turn on under large current and inject minority carriers into the epitaxial layer 200 of the MOSFET device. The resulting conductance modulation effect can greatly reduce the resistance of the device. This MOSFET device integrated with a hybrid PIN Schottky diode (MPS) has a lower voltage drop during forward conduction and a higher breakdown voltage during reverse bias.

[0105] In some alternative embodiments, to further improve the blocking ability of the device, such as Figure 3 shown, the first surface 1a has trenches, and at least a part of the well region 300 extends from a partial surface of the trenches into the epitaxial layer 200. It can be understood that the well region 300 can be moved away from the Schottky metal 602 through the trenches, so that the blocking of the device can be better.

[0106] Specifically, the second JFET region 10 has a partial region located in the first surface, and this partial region can be located outside the trenches.

[0107] In some alternative embodiments, such as Figure 6 shown, the contact surface between the second partial well region (well region 300) and the gate structure 700 includes the {0-33-8} crystal plane. In the above embodiments, such a setting can further improve the channel mobility in the device.

[0108] To simplify the process, in some alternative embodiments, when the first surface corresponding to the trenches includes a bottom surface and sidewalls, a part of the well region extends from a partial bottom surface of the trenches into the epitaxial layer.

[0109] Alternatively, in some other alternative embodiments, to further improve the electric field concentration at the trench corners, a part of the well region extends from the entire bottom surface of the trenches into the epitaxial layer; or, a part of the well region extends from the entire bottom surface and a partial sidewall of the trenches into the epitaxial layer.

[0110] In some embodiments, to reduce leakage, such as Figure 3 and Figure 6 shown, the cell structure may further include a silicon oxide layer 102, and the silicon oxide layer 102 can be located on the sidewalls of the trenches, and this silicon oxide layer 102 can be located between a part of the ohmic contact metal 601 and the epitaxial layer 200.

[0111] In some embodiments, the number of the second JFET regions 10 in each cell region can be one, and when the side line of the first preset pattern is a second rectangle, such as Figures 9 to 10 shown, the well contact region 500 may include a first partial well contact region (not marked in the figure), a second partial well contact region (not marked in the figure), and a third partial well contact region (not marked in the figure) that are adjacently arranged. The first partial well contact region, the second partial well contact region, and the third partial well contact region can be respectively located on three sides of the second JFET region 10 (it can be understood that the second JFET region 10 has four sides, and the first partial well contact region, the second partial well contact region, and the third partial well contact region are respectively located on three of the four sides of the second JFET region 10).

[0112] When the well contact region 500 is adjacent to the source region 400 and the partial second part well region 301 is respectively adjacent to the well contact region 500 and the second JFET region 10, the partial second part well region 301 is respectively adjacent to the first part well contact region and the second JFET region 10, the partial second part well region 301 is respectively adjacent to the second part well contact region and the second JFET region 10, and the partial second part well region 301 is respectively adjacent to the third part well contact region and the second JFET region 10; or, when the well contact region 500 is respectively adjacent to the source region 400 and the second JFET region 10, the first part well contact region, the second part well contact region, and the third part well contact region can all be arranged adjacent to the second JFET region 10.

[0113] It should be noted that at least one side of the second JFET region 10 does not have the well contact region 500, so that the side of the second JFET region 10 without the well contact region 500 can be adjacent to the second part well region 301, and the side of the second part well region 301 far from the second JFET region 10 is adjacent to the source region 400, that is, the partial second part well region 301 can be respectively adjacent to the second JFET region 10 and the source region 400 to form the above-mentioned channel region 3011. As Figure 9 shown, the second JFET region 10, the second part well region 301, and the source region 400 are sequentially adjacent in the first direction C.

[0114] It is mentioned here that, as Figure 7 shown, the second JFET region 10, the second part well region 301, and the source region 400 are sequentially adjacent in the B - B' direction; as Figure 11 shown, the second JFET region 10, the second part well region 301, and the source region 400 are sequentially adjacent in the second direction D; as Figure 13 shown, the second JFET region 10, the second part well region 301, and the source region 400 are sequentially adjacent in the third direction E. In summary, as Figures 7 to 14 shown, the partial second part well region 301 in the figure can all be respectively adjacent to the second JFET region 10 and the source region 400 to form the above-mentioned channel region 3011.

[0115] Furthermore, as Figure 9 and Figure 10As shown, the second JFET region 10 has a third rectangle in a cross-section parallel to the first surface, and the third rectangle is located within the second rectangle; the first JFET region 20 surrounds the well region 300, the second JFET region 10 has opposite first and second ends in a first direction C, and another part of the second JFET region 10 located between the first and second ends, the first direction C being parallel to the first surface; the source region 400 surrounds the second part of the well region 301, and the first part of the well region 302 surrounds the source region 400; the Schottky metal 602 covers a part of the second JFET region 10 at the first end. At this time, the part of the second JFET region 10 at the first end covered by the Schottky metal 602 can be regarded as the third Schottky region, and the Schottky metal 602 also covers a part of the second part of the well region 301 in contact with the third Schottky region, and the well contact region 500 is located in the second part of the well region 301 and semi-surrounds the second JFET region 10 at the first end. It can be understood that the above-mentioned another part of the second JFET region 10 located between the first and second ends is not covered by the Schottky metal. Moreover, the part between the second JFET region 10 at the second end in the second JFET region 10 and the second part of the well region 301 does not have the well contact region 500, or the part between the second JFET region 10 at the second end in the second JFET region 10 and the source region 400 does not have the well contact region 500.

[0116] Exemplarily, as Figure 10 shown, there can be one ohmic contact metal 601, and the ohmic contact metal 601 is disposed around the outer periphery of a part of the Schottky metal 602 (i.e., the ohmic contact metal 601 semi-surrounds the outer periphery of the Schottky metal 602), and the ohmic contact metal 601 covers a part of the well contact region 500, a part of the second part of the well region 301, and a part of the source region 400.

[0117] As Figure 10 shown, the part of the second JFET region 10 at the second end can be regarded as the third embedded semiconductor region, and the second gate structure 30 in the gate structure 700 covers the third embedded semiconductor region. The second gate structure 30 also covers a part of the second part of the well region 301 surrounding the third embedded semiconductor region and a part of the source region 400 surrounding the third embedded well region, and the third embedded well region is a part of the second part of the well region 301 adjacent to the third embedded semiconductor region.

[0118] As Figure 9 and Figure 10As shown, the source region 400 includes a partial source region 400 that surrounds the second JFET region 10 and is close to the first partial well region 302, and a partial source region 400 that surrounds the second JFET region 10 and is close to the second partial well region 301. The first gate structure 40 in the gate structure 700 surrounds the second JFET region 10. The second gate structure 30 is located on one side of the first gate structure 40 close to the second JFET region 10, and the first gate structure 40 covers the partial source region 400 that surrounds the second JFET region 10 and is close to the first partial well region 302, the first partial well region 302, and a partial first JFET region 20 that surrounds the outer periphery of the well region 300.

[0119] In some embodiments, when the polygon is the first hexagon or the first octagon, the number of second JFET regions 10 in each cell region can be one, as Figures 11 to 14 As shown, the well contact region 500 may include a fourth partial well contact region (not labeled in the figure) and a fifth partial well contact region (not labeled in the figure) that are spaced apart. The fourth partial well contact region and the fifth partial well contact region may be respectively located on opposite sides of the second JFET region 10. When the well contact region 500 is adjacent to the source region 400 and a part of the second partial well region 301 is respectively adjacent to the well contact region 500 and the second JFET region 10, a part of the second partial well region 301 may be located between the fourth partial well contact region (well contact region 500) and the second JFET region 10, and a part of the second partial well region 301 may be located between the fifth partial well contact region and the second JFET region 10; or, when the well contact region 500 is respectively adjacent to the source region 400 and the second JFET region 10, the fourth partial well contact region may be adjacent to the second JFET region 10 and the source region 400 respectively, and the fifth partial well contact region may be adjacent to the second JFET region 10 and the source region 400 respectively. It can be understood that the fourth partial well contact region may be adjacent to the first side of the second JFET region 10, and the fifth partial well contact region may be adjacent to the second side of the second JFET region 10, and the first side and the second side are opposite sides of the second JFET region 10.

[0120] In some alternative embodiments, as Figure 11 and Figure 12 shown, when the polygon is the first hexagon, the second JFET region 10 has a first irregular figure in a cross-section parallel to the first surface. The first irregular figure is located in the first hexagon. The first irregular figure includes a second hexagon and two first preset patterns, and the two first preset patterns are respectively in contact with opposite sides of the second hexagon in the second direction D, and the second direction D is parallel to the first surface.

[0121] As Figure 11 and Figure 12As shown, the first JFET region 20 surrounds the well region 300. The second JFET region 10 has a first part, a second part, and a third part with a contact arrangement in the second direction D. The second part is located between the first part and the third part. The second part well region 301 is in contact with the side of the first part away from the second part and the side of the third part away from the second part respectively. The first part and the third part correspond to two first preset patterns one by one, and the second part corresponds to the second hexagon.

[0122] As Figure 11 and Figure 12 shown, the source region 400 surrounds the second part well region 301, and the first part well region 302 surrounds the source region 400.

[0123] As Figure 11 and Figure 12 shown, the Schottky metal 602 covers at least part of the second part. As Figure 11 and Figure 12 shown, the well contact region 500 includes a first part doped region (not shown in the figure) and a second part doped region (not shown in the figure). Among them, the first part doped region and the second part doped region are located on opposite sides of the second JFET region 10 in a direction perpendicular to the second direction D. Based on this, the source region 400, the second part well region 301, and the first part of the second JFET region 10 are sequentially adjacent in the second direction D; the source region 400, the second part well region 301, and the third part of the second JFET region 10 are sequentially adjacent in the second direction D; the source region 400, the first part doped region, the second part well region 301, and the second part of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the second direction D; the source region 400, the second part doped region, the second part well region 301, and the second part of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the second direction D.

[0124] In some embodiments, the Schottky metal 602 may also cover a part of the second part well region 301 that is in contact with the second part.

[0125] As Figure 12 shown, the second gate structure 30 in the gate structure 700 may include a fifth sub-gate structure (not labeled in the figure) and a sixth sub-gate structure (not labeled in the figure) that are located on opposite sides of the Schottky metal 602 in the second direction D.

[0126] As Figure 11 and Figure 12As shown, the first part in the second JFET region 10 includes a partial first part that is close to the second part well region 301 and far from the second part in the second JFET region 10, and a partial first part that is close to the second part in the second JFET region 10 and far from the second part well region 301. The partial first part that is close to the second part well region 301 and far from the second part in the second JFET region 10 can be regarded as the fourth embedded semiconductor region, and a fifth sub-gate structure (not labeled in the figure) covers the fourth embedded semiconductor region. The fifth sub-gate structure also covers a part of the second part well region 301 that contacts the fourth embedded semiconductor region and a part of the source region 400 that contacts the fourth embedded well region. The fourth embedded well region is the part of the second part well region 301 that is located on the side away from the second part of the first part in the second JFET region 10.

[0127] As Figure 11 and Figure 12 As shown, the third part in the second JFET region 10 includes a partial third part that is close to the second part well region 301 and far from the second part in the second JFET region 10, and a partial third part that is close to the second part in the second JFET region 10 and far from the second part well region 301. The partial third part that is close to the second part well region 301 and far from the second part in the second JFET region 10 can be regarded as the fifth embedded semiconductor region, and a sixth sub-gate structure (not labeled in the figure) covers the fifth embedded semiconductor region. The sixth sub-gate structure also covers a part of the second part well region 301 that contacts the fifth embedded semiconductor region and a part of the source region that contacts the fifth embedded well region. The fifth embedded well region is the part of the second part well region 301 that is located on the side away from the second part of the third part.

[0128] As Figure 11 and Figure 12 As shown, the source region 400 includes a partial source region that surrounds the second JFET region 10 and is close to the first part well region 302, and a partial source region that surrounds the second JFET region 10 and is close to the second part well region 301. The first gate structure 40 surrounds the second JFET region 10. The fifth sub-gate structure is located on the side of the first gate structure 40 close to the second JFET region 10, and the fifth sub-gate structure covers a part of the source region 400, the second part well region 301, and a part of the first part of the second JFET region 10 that are sequentially adjacent in the second direction D.

[0129] As Figure 11 and Figure 12 As shown, the sixth sub-gate structure is located on the other side of the first gate structure 40 close to the second JFET region 10, and the sixth sub-gate structure covers a part of the source region 400, the second part well region 301, and a part of the third part of the second JFET region 10 that are sequentially adjacent in the second direction D.

[0130] As Figure 11 andFigure 12 As shown, the first gate structure 40 covers the partial source region 400 that surrounds the second JFET region 10 and is close to the first partial well region 302, the first partial well region 302, and the partial first JFET region 20 that surrounds the outer periphery of the well region 300.

[0131] In some alternative embodiments, as Figure 13 and Figure 14 shown, when the polygon is the first octagon, the second JFET region 10 has a second irregular figure in a cross-section parallel to the first surface, the second irregular figure is located in the first octagon, the second irregular figure includes a second octagon and two second preset patterns, and the two second preset patterns are in contact with and disposed on opposite sides of the second octagon in the third direction E, and the third direction E is parallel to the first surface.

[0132] As Figure 13 and Figure 14 shown, the first JFET region 20 surrounds the well region 300, and the second JFET region 10 has a fourth part, a fifth part, and a sixth part that are in contact and disposed in the third direction E, the fifth part is located between the fourth part and the sixth part, the sides of the fourth part away from the fifth part and the sixth part away from the fifth part are respectively in contact with the second partial well region 301, the fourth part and the sixth part respectively correspond to the two second preset patterns one by one, and the fifth part corresponds to the second octagon.

[0133] As Figure 13 and Figure 14 shown, the source region 400 surrounds the second partial well region 301, and the first partial well region 302 surrounds the source region 400. The Schottky metal 602 covers the fifth part.

[0134] As Figure 13 and Figure 14 shown, the well contact region 500 includes a third doped region (not shown in the figure) and a fourth doped region (not shown in the figure). Specifically, the third doped region and the fourth doped region are located on opposite sides of the second JFET region 10 in a direction perpendicular to the third direction E. Based on this, the source region 400, the second partial well region 301, and the fourth part of the second JFET region 10 are sequentially adjacent in the third direction E; the source region 400, the second partial well region 301, and the sixth part of the second JFET region 10 are sequentially adjacent in the third direction E; the source region 400, the third doped region, the second partial well region 301, and the fourth part of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the third direction E; the source region 400, the fourth doped region, the second partial well region 301, and the sixth part of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the third direction E.

[0135] In some embodiments, the Schottky metal may also cover a portion of the second part well region that contacts the fifth part.

[0136] As Figure 14 shown, the second gate structure 30 in the gate structure 700 includes a seventh sub-gate structure (not labeled in the figure) and an eighth sub-gate structure (not labeled in the figure) located on opposite sides of the Schottky metal 602 in the third direction E.

[0137] As Figure 13 and Figure 14 shown, the fourth part of the second JFET region 10 includes a partial fourth part that is close to the second part well region 301 and far from the fifth part of the second JFET region 10, and a partial fourth part that is close to the fifth part of the second JFET region 10 and far from the second part well region 301. The partial fourth part that is close to the fifth part of the second JFET region 10 and far from the second part well region 301 can be regarded as a sixth embedded semiconductor region, and the seventh sub-gate structure (not labeled in the figure) covers the sixth embedded semiconductor region. The seventh sub-gate structure also covers a portion of the second part well region 301 that contacts the sixth embedded semiconductor region and a portion of the source region 400 that contacts the sixth embedded well region. The sixth embedded well region is a portion of the second part well region 301 that is located on the side of the fourth part of the second JFET region 10 away from the fifth part.

[0138] As Figure 13 and Figure 14 shown, the sixth part of the second JFET region 10 includes a partial sixth part that is close to the second part well region 301 and far from the fifth part of the second JFET region 10, and a partial sixth part that is close to the fifth part of the second JFET region 10 and far from the second part well region 301. The partial sixth part that is close to the fifth part of the second JFET region 10 and far from the second part well region 301 can be regarded as a seventh embedded semiconductor region. The eighth sub-gate structure (not labeled in the figure) covers the seventh embedded semiconductor region.

[0139] As Figure 13 and Figure 14 shown, the eighth sub-gate structure also covers a portion of the second part well region 301 that contacts the seventh embedded semiconductor region and a portion of the source region 400 that contacts the seventh embedded well region. The seventh embedded well region is a portion of the second part well region 301 that is located on the side of the sixth part of the second JFET region 10 away from the fifth part.

[0140] As Figure 13 and Figure 14As shown, the source region 400 includes a partial source region 400 that surrounds the second JFET region 10 and is close to the first partial well region 302, and a partial source region 400 that surrounds the second JFET region 10 and is close to the second partial well region 301. The first gate structure 40 surrounds the second JFET region 10. The seventh sub-gate structure is located on the side of the first gate structure 40 close to the second JFET region 10, and the seventh sub-gate structure covers a partial fourth part of the source region 400, the second partial well region 301, and the second JFET region 10 that are sequentially adjacent in the third direction E. Exemplarily, the seventh sub-gate structure covers a partial source region 400, a partial second partial well region 301, and a partial fourth part of the second JFET region 10.

[0141] As Figure 13 and Figure 14 shown, the eighth sub-gate structure is located on the other side of the first gate structure 40 close to the second JFET region 10, and the eighth sub-gate structure covers a partial sixth part of the source region 400, the second partial well region 301, and the second JFET region 10 that are sequentially adjacent in the third direction E. Exemplarily, the eighth sub-gate structure covers a partial source region 400, a partial second partial well region 301, and a partial sixth part of the second JFET region 10.

[0142] As Figure 13 and Figure 14 shown, the first gate structure 40 covers a partial source region 400 that surrounds the second JFET region 10 and is close to the first partial well region 302, the first partial well region 302, and a partial first JFET region 20 that surrounds the well region 300.

[0143] Exemplarily, as Figure 12 and Figure 14 shown, in order to increase the channel density and ensure current uniformity, there are two ohmic contact metals 601, and the two ohmic contact metals 601 are located on opposite sides of the Schottky metal 602 in a one-to-one correspondence. And, as Figure 12 shown, each ohmic contact metal 601 covers a partial well contact region 500, a partial second partial well region 301, and a partial source region 400; as Figure 14 shown, each ohmic contact metal 601 covers a partial well contact region 500 and a partial source region 400.

[0144] In addition, according to another aspect of the present application, a method for manufacturing a MOSFET device is further provided, including:

[0145] Providing a substrate;

[0146] Forming an epitaxial layer on one side surface of the substrate in sequence;

[0147] Forming a JFET doping region in the epitaxial layer, and the surface of the epitaxial layer away from the substrate is the first surface of the epitaxial layer;

[0148] Optionally, the step of forming the epitaxial layer includes: sequentially forming a first sub-epitaxial layer and a second sub-epitaxial layer on one surface of the substrate by an epitaxial process;

[0149] Optionally, the step of forming the JFET doping region includes: epitaxially growing a third sub-epitaxial layer on the side of the second sub-epitaxial layer away from the first sub-epitaxial layer to form the JFET doping region.

[0150] Optionally, the step of forming the JFET doping region includes: performing ion implantation on the surface of the second sub-epitaxial layer away from the first sub-epitaxial layer to form a well contact region;

[0151] A well region is formed in the epitaxial layer by an ion implantation process, so that the well region extends from the first surface into the epitaxial layer. The epitaxial layer includes a first JFET region and a second JFET region. The well region surrounds the second JFET region. The first JFET region is located on at least one side of the well region away from the second JFET region, and the conductivity type of the epitaxial layer is opposite to that of the well region;

[0152] A source region is formed in the well region by an ion implantation process, so that the source region extends from the first surface into the well region. The source region surrounds the second JFET region, and there is a first partial well region between the source region and the first JFET region, and a second partial well region between the source region and the second JFET region. The well region includes the first partial well region and the second partial well region;

[0153] A well contact region is formed in the well region by an ion implantation process, so that the well contact region extends from the first surface into the well region, and the well contact region semi-surrounds the second JFET region. The conductivity type of the well contact region is the same as that of the well region;

[0154] Optionally, before the step of forming the well region by an ion implantation process, the trench region is etched by an etching process so that the well region, the source region, and the well contact region are formed by implantation in the trench;

[0155] It should be noted that after the ion implantation process, a high-temperature annealing at a temperature higher than 1650 °C can be used to activate the impurity ions implanted by the ion implantation.

[0156] A gate structure is formed on the first surface. The gate structure includes a gate oxide layer in contact with the first surface, polysilicon on the side of the gate oxide layer away from the first surface, and a dielectric layer covering the polysilicon;

[0157] An ohmic contact metal is formed on the first surface. The ohmic contact metal covers a part of the surface of the well contact region on the first surface, a part of the surface of the second partial well region on the first surface, and a part of the surface of the source region on the first surface;

[0158] A Schottky metal is formed on the first surface to cover a partial surface of the second JFET region in the first surface;

[0159] A front metal layer is formed on a side of the Schottky metal away from the epitaxial layer;

[0160] The substrate is thinned, and a back metal layer is formed on a surface (the second surface) of the substrate on a side away from the epitaxial layer.

[0161] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0162] Applying the technical solution of the present invention, a cell structure of a MOSFET device, the cell structure includes a substrate, an epitaxial layer on one side of the substrate, and a cell region located in the epitaxial layer. The cell region includes: a first JFET region and a second JFET region arranged at intervals, both the first JFET region and the second JFET region are located in the epitaxial layer; a well region located in the epitaxial layer and surrounding the second JFET region, the first JFET region is located on at least one side of the well region away from the second JFET region, and the conductivity type of the well region is opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, there is a first partial well region between the source region and the first JFET region, and there is a second partial well region between the source region and the second JFET region, and the well region includes the first partial well region and the second partial well region; a well contact region located in a part of the second partial well region, so that there are channel regions adjacent to the source region and the second JFET region respectively in the second partial well region, the conductivity type of the well contact region is the same as that of the well region, and the doping concentration of the well contact region is higher than that of the well region; an ohmic contact metal covering at least a part of the well contact region; a gate structure including an adjacent first gate structure and a second gate structure, the first gate structure covers the first partial well region, a part of the source region adjacent to the first partial well region respectively, and at least a part of the first JFET region, the second gate structure covers a part of the channel region, a part of the source region adjacent to the part of the channel region respectively, and a part of the second JFET region, and the gate structure is spaced from the ohmic contact metal. It can be seen that a Schottky diode is integrated in the MOSFET device in this application. Since the turn-on voltage of the Schottky diode is lower than that of the traditional bulk diode, the turn-on is greatly reduced, thereby improving the problem of the relatively high turn-on voltage of the traditional MOSFET through this application, which is beneficial to the conduction of the reverse current in the MOSFET; and, since the conduction of the Schottky diode has unipolar conductivity, this can avoid the bipolar degradation effect when the MOSFET is under low current density and the PN junction has not started to inject, and at the same time can reduce the reverse recovery current and reverse recovery loss. In addition, for the first partial well region located between the first JFET region and the source region covered by the first gate structure, there is a first conductive channel in the first partial well region. On this basis, a second conductive channel is formed in the second partial well region covered by the second gate structure between the second JFET region and the source region in this application, and then a hybrid PIN Schottky diode (MPS) is integrated in the well region of the MOSFET device, so that while not increasing the cell width in the MOSFET device and retaining the original first conductive channel in the MOSFET device, the channel width in the MOSFET device is increased, and then during the forward conduction of the MOSFET device, the current density below the well region and the Schott contact region of the MOSFET device can be increased, so that the MOSFET device has good forward conduction characteristics.Based on this, the present application solves the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the existing MOSFET is used as the freewheeling path.

[0163] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A cell structure of a MOSFET device, characterized in that, The cellular structure includes a substrate, an epitaxial layer and a cellular region located on one side of the substrate, the cellular region is located in the epitaxial layer, and the cellular region includes: a first JFET region and a second JFET region, wherein the first JFET region is located at least on two sides of the second JFET region; a well region, located between the first JFET region and the second JFET region, the well region having a conductivity type opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, the well region between the source region and the first JFET region being a first partial well region, and the well region between the source region and the second JFET region being a second partial well region; a well contact region located in part of the second partial well region, so that the remaining second partial well region has a channel region adjacent to the source region and the second JFET region respectively, the well contact region and the well region have the same doping type, and the doping concentration of the well contact region is higher than the doping concentration of the well region; A gate structure comprises a first gate structure and a second gate structure adjacent to each other, wherein the first gate structure covers the first partial well region and the portion of the source region and at least the portion of the first JFET region respectively adjacent to the first partial well region, and the second gate structure covers the portion of the channel region and the portion of the source region and the portion of the second JFET region respectively adjacent to the portion of the channel region.

2. The cellular structure according to claim 1, characterized in that: The well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively; or, The well contact region is adjacent to the source region and the second JFET region, respectively.

3. The cell structure according to claim 2, wherein The cellular structure also includes: Schottky metal covering a portion of the second JFET region; The ohmic contact metal at least covers a portion of the well contact area and is disposed in contact with the ohmic contact metal; wherein, In the case where the well contact region is adjacent to the source region and part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the second partial well region and part of the source region respectively adjacent to the well contact region; in the case where the well contact region is respectively adjacent to the source region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the source region adjacent to the well contact region.

4. The cell structure according to claim 3, characterized in that, The epitaxial layer has a first surface on a side facing away from the substrate, in which the well contact region is adjacent to the source region and a portion of the second partial well region is adjacent to the well contact region and the second JFET region, respectively. The first surface corresponding to the second JFET region is a first region surface, the first region surface includes a first sub-region and a second sub-region adjacent to each other, and a side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; The first surface corresponding to the second part of the well region is the second region surface, and the second region surface includes an adjacent third sub-region and a fourth sub-region. The third sub-region is the first surface corresponding to the channel region, and the fourth sub-region is the second region surface except the third sub-region; The Schottky metal covers the first sub-region and part of the fourth sub-region.

5. The cell structure according to claim 4, wherein The first surface corresponding to the first part of the well region is the third region surface, the first surface corresponding to the source region is the fourth region surface, and at least part of the fourth region surface is located between the second region surface and the third region surface; The part of the first region surface covered by the second gate structure is the fifth sub-region, the part of the fourth region surface covered by the second gate structure is the sixth sub-region, and the third sub-region is located between the fifth sub-region and the sixth sub-region; The first surface corresponding to the first JFET region is the fifth region surface, and the part of the fifth region surface covered by the first gate structure is the seventh sub-region. The third region surface is located between at least part of the fourth region surface and the seventh sub-region.

6. The cell structure according to claim 3, characterized in that, The epitaxial layer has a first surface on a side facing away from the substrate, and the well region has a first preset pattern in a cross-section parallel to the first surface, and the side line of the first preset pattern is a polygon.

7. The cell structure according to claim 6, wherein In the case where the polygon is a first rectangle, The second JFET region includes a first sub-JFET region and a second sub-JFET region. The second part of the well region includes a part located between the first sub-JFET region and the second sub-JFET region and another part except the part. The well contact region is disposed in a part of the second part of the well region located between the first sub-JFET region and the second sub-JFET region; In a direction perpendicular to the connection line between the first sub-JFET region and the second sub-JFET region, the first part of the well region includes a first sub-well region located on the left side of the connection line and a second sub-well region located on the right side of the connection line; The Schottky metal includes a first sub-Schottky metal and a second sub-Schottky metal that are spaced apart. When the first sub-JFET region includes a part of the first sub-JFET region close to the second sub-JFET region, a part of the first sub-JFET region far from the second sub-JFET region, and another part of the first sub-JFET region located between the two parts of the first sub-JFET region, the part of the first sub-JFET region close to the second sub-JFET region in the first sub-JFET region is the first Schottky region, and the first sub-Schottky metal covers at least the first Schottky region. When the second sub-JFET region includes a part of the second sub-JFET region close to the first sub-JFET region, a part of the second sub-JFET region far from the first sub-JFET region, and another part of the second sub-JFET region located between the two parts of the first sub-JFET region, the part of the second sub-JFET region close to the first sub-JFET region in the second sub-JFET region is the second Schottky region, and the second sub-Schottky metal covers at least the second Schottky region.

8. The cell structure according to claim 7, wherein The second gate structure includes a first sub-gate structure and a second sub-gate structure. The first sub-gate structure is located on a side of the first sub-Schottky metal away from the second sub-Schottky metal, and the second sub-gate structure is located on a side of the second sub-Schottky metal away from the first sub-Schottky metal; The part of the first sub-JFET region far from the second sub-JFET region in the first sub-JFET region is the first embedded semiconductor region. The first sub-gate structure covers the first embedded semiconductor region, a part of the second part well region surrounding the first embedded semiconductor region, and a part of the source region surrounding the first embedded well region. The first embedded well region is a part of the second part well region adjacent to the first embedded semiconductor region; The part of the second sub-JFET region far from the first sub-JFET region in the second sub-JFET region is the second embedded semiconductor region. The second sub-gate structure covers the second embedded semiconductor region, a part of the second part well region surrounding the second embedded semiconductor region, and a part of the source region surrounding the second embedded well region. The second embedded well region is a part of the second part well region adjacent to the second embedded semiconductor region.

9. The cell structure according to claim 8, wherein The first gate structure includes a third sub-gate structure and a fourth sub-gate structure. The third sub-gate structure is located on the left side, and the fourth sub-gate structure is located on the right side. The third sub-gate structure is in contact with the first sub-gate structure and the second sub-gate structure respectively, and the first sub-gate structure and the second sub-gate structure are also both in contact with the fourth sub-gate structure; The source region includes a part of the source region of the second partial well region away from the second JFET region and close to the first sub-well region and a part of the source region of the second partial well region away from the second JFET region and close to the second sub-well region. The third sub-gate structure covers the part of the source region of the second partial well region away from the second JFET region and close to the first sub-well region. The third sub-gate structure also covers the first sub-well region and a part of the first JFET region located on a side of the first sub-well region away from the first sub-JFET region and the second sub-JFET region; The fourth sub-gate structure covers the part of the source region of the second partial well region away from the second JFET region and close to the second sub-well region. The fourth sub-gate structure also covers the second sub-well region and a part of the first JFET region located on a side of the second sub-well region away from the first sub-JFET region and the second sub-JFET region.

10. The cell structure according to claim 7, characterized in that, The epitaxial layer has a first surface on a side facing away from the substrate. The first surface has grooves, and at least part of the well region extends from a partial surface of the grooves into the epitaxial layer.

11. The cell structure according to claim 10, characterized in that, The contact surface between the second partial well region and the gate structure includes a {0-33-8} crystal plane.

12. The cell structure according to claim 10, characterized in that, The first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from a partial bottom surface of the grooves into the epitaxial layer.

13. The cell structure according to claim 10, characterized in that, The first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from the entire bottom surface of the grooves into the epitaxial layer.

14. The cell structure according to claim 10, wherein, The first surface corresponding to the grooves includes a bottom surface and side walls, and part of the well region extends from the entire bottom surface and a partial side wall of the grooves into the epitaxial layer.

15. The cell structure according to claim 10, characterized in that, The first surface corresponding to the grooves includes a bottom surface and side walls, and the cell structure further includes: A silicon oxide layer covering the side walls of the grooves where part of the second partial well region is located.

16. The cell structure according to claim 6, wherein In the case where the polygon is a second rectangle, the well contact region includes a first partial well contact region, a second partial well contact region, and a third partial well contact region that are adjacently arranged. The first partial well contact region, the second partial well contact region, and the third partial well contact region are respectively located on three sides of the second JFET region; In the case where the well contact region is adjacent to the source region and part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, part of the second partial well region is respectively adjacent to the first partial well contact region and the second JFET region, part of the second partial well region is respectively adjacent to the second partial well contact region and the second JFET region, and part of the second partial well region is respectively adjacent to the third partial well contact region and the second JFET region; In the case where the well contact region is respectively adjacent to the source region and the second JFET region, the second JFET region is respectively adjacent to the first partial well contact region, the second partial well contact region, and the third partial well contact region.

17. The cell structure according to claim 16, wherein The second JFET region has a third rectangle in a cross-section parallel to the first surface, and the third rectangle is located within the second rectangle; The first JFET region surrounds the well region. The second JFET region has opposite first and second ends in a first direction, and the first direction is parallel to the first surface; The source region surrounds the second part of the well region, and the first part of the well region surrounds the source region; The Schottky metal covers a part of the second JFET region at the first end, and the Schottky metal also covers a part of the second part of the well region in contact with a third Schottky region. The third Schottky region is the part of the second JFET region at the first end covered by the Schottky metal. The well contact region is located in the second part of the well region and semi-surrounds the second JFET region at the first end; The second gate structure covers a third embedded semiconductor region, a part of the second part of the well region surrounding the third embedded semiconductor region, and a part of the source region surrounding a third embedded well region. The third embedded semiconductor region is the part of the second JFET region at the second end, and the third embedded well region is the part of the second part of the well region adjacent to the third embedded semiconductor region; The source region includes a part of the source region surrounding the second JFET region and close to the first part of the well region and a part of the source region surrounding the second JFET region and close to the second part of the well region. The first gate structure surrounds the second JFET region. The second gate structure is located on a side of the first gate structure close to the second JFET region, and the first gate structure covers a part of the source region surrounding the second JFET region and close to the first part of the well region, the first part of the well region, and a part of the first JFET region surrounding the outer periphery of the well region; 18. The cell structure according to claim 6, wherein In the case where the polygon is a first hexagon or a first octagon, The well contact region includes a fourth part of the well contact region and a fifth part of the well contact region arranged at intervals, and the fourth part of the well contact region and the fifth part of the well contact region are respectively located on opposite sides of the second JFET region; In the case where the well contact region is adjacent to the source region and a part of the second part of the well region is respectively adjacent to the well contact region and the second JFET region, a part of the second part of the well region is located between the fourth part of the well contact region and the second JFET region, and a part of the second part of the well region is located between the fifth part of the well contact region and the second JFET region; In the case where the well contact region is respectively adjacent to the source region and the second JFET region, the fourth part of the well contact region is respectively adjacent to a part of the source region and the second JFET region, and the fifth part of the well contact region is respectively adjacent to a part of the source region and the second JFET region; 19. The cell structure according to claim 18, wherein, When the polygon is the first hexagon, the second JFET region has a first irregular figure in a cross-section parallel to the first surface, the first irregular figure is located in the first hexagon, the first irregular figure includes a second hexagon and two first preset patterns, and the two first preset patterns are respectively in contact with opposite sides of the second hexagon in a second direction, and the second direction is parallel to the first surface; The first JFET region surrounds the well region, the second JFET region has a first part, a second part, and a third part in contact arrangement in the second direction, the second part is located between the first part and the third part, the second part well region is respectively in contact with a side of the first part away from the second part and a side of the third part away from the second part, the first part and the third part correspond to the two first preset patterns one by one, and the second part corresponds to the second hexagon; The source region surrounds the second part well region, and the first part well region surrounds the source region; The Schottky metal covers at least part of the second part; The well contact region includes a first part doped region and a second part doped region, the first part doped region and the second part doped region are located on opposite sides of the second JFET region in a direction perpendicular to the second direction, the source region, the second part well region, and the first part are adjacent in sequence in the second direction, the source region, the second part well region, and the third part are adjacent in sequence in the second direction, the source region, the first part doped region, the second part well region, and the second part are adjacent in sequence in a direction perpendicular to the second direction, and the source region, the second part doped region, the second part well region, and the second part are adjacent in sequence in a direction perpendicular to the second direction.

20. The cell structure according to claim 19, wherein The second gate structure includes a fifth sub-gate structure and a sixth sub-gate structure located on opposite sides of the Schottky metal in the second direction; The first part includes a part of the first part close to the second part well region and away from the second part and a part of the first part close to the second part and away from the second part well region, the fifth sub-gate structure covers a fourth embedded semiconductor region, a part of the second part well region in contact with the fourth embedded semiconductor region, and a part of the source region in contact with the fourth embedded well region, the fourth embedded semiconductor region is a part of the first part close to the second part well region and away from the second part, and the fourth embedded well region is a part of the second part well region located on a side of the first part away from the second part; The third part includes a part of the third part close to the well region of the second part and far from the second part, and a part of the third part close to the second part and far from the well region of the second part. The sixth sub-gate structure covers the fifth embedded semiconductor region, a part of the well region of the second part in contact with the fifth embedded semiconductor region, and a part of the source region in contact with the fifth embedded well region. The fifth embedded semiconductor region is a part of the third part close to the well region of the second part and far from the second part. The fifth embedded well region is a part of the well region of the second part on the side of the third part far from the second part; The source region includes a part of the source region surrounding the second JFET region and close to the well region of the first part, and a part of the source region surrounding the second JFET region and close to the well region of the second part. The first gate structure surrounds the second JFET region. The fifth sub-gate structure is located on the side of the first gate structure close to the second JFET region, and the fifth sub-gate structure covers a part of the source region, a part of the well region of the second part, and a part of the first part that are sequentially adjacent in the second direction. The sixth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the sixth sub-gate structure covers a part of the source region, a part of the well region of the second part, and a part of the third part that are sequentially adjacent in the second direction. The first gate structure covers a part of the source region surrounding the second JFET region and close to the well region of the first part, the well region of the first part, and a part of the first JFET region surrounding the outer periphery of the well region; 21. The cell structure according to claim 18, wherein, When the polygon is a first octagon, the second JFET region has a second irregular figure in a cross-section parallel to the first surface. The second irregular figure is located in the first octagon. The second irregular figure includes a second octagon and two second preset patterns. The two second preset patterns are in contact with and arranged on the opposite sides of the second octagon in the third direction. The third direction is parallel to the first surface; The first JFET region surrounds the well region. The second JFET region has a fourth part, a fifth part, and a sixth part that are in contact and arranged in the third direction. The fifth part is located between the fourth part and the sixth part. One side of the fourth part far from the fifth part and one side of the sixth part far from the fifth part are respectively in contact with the well region of the second part. The fourth part and the sixth part correspond to the two second preset patterns one by one. The fifth part corresponds to the second octagon; The source region surrounds the well region of the second part, and the well region of the first part surrounds the source region; The Schottky metal covers the fifth part; The well contact region includes a third partial doping region and a fourth partial doping region. The third partial doping region and the fourth partial doping region are located on opposite sides of the second JFET region in a direction perpendicular to the third direction. The source region, the second partial well region, and the fourth part are sequentially adjacent in the third direction. The source region, the second partial well region, and the sixth part are sequentially adjacent in the third direction. The source region, the third partial doping region, the second partial well region, and the fourth part are sequentially adjacent in a direction perpendicular to the third direction. The source region, the fourth partial doping region, the second partial well region, and the sixth part are sequentially adjacent in a direction perpendicular to the third direction.

22. The cell structure according to claim 21, wherein the second gate structure includes a seventh sub-gate structure and an eighth sub-gate structure located on opposite sides of the Schottky metal in the third direction; the fourth part includes a part of the fourth part close to the second partial well region and far from the fifth part and a part of the fourth part close to the fifth part and far from the second partial well region. The seventh sub-gate structure covers a sixth embedded semiconductor region, a part of the second partial well region in contact with the sixth embedded semiconductor region, and a part of the source region in contact with the sixth embedded well region. The sixth embedded semiconductor region is a part of the fourth part close to the second partial well region and far from the fifth part. The sixth embedded well region is a part of the second partial well region located on the side of the fourth part far from the fifth part; the sixth part includes a part of the sixth part close to the second partial well region and far from the fifth part and a part of the sixth part close to the fifth part and far from the second partial well region. The eighth sub-gate structure covers a seventh embedded semiconductor region, a part of the second partial well region in contact with the seventh embedded semiconductor region, and a part of the source region in contact with the seventh embedded well region. The seventh embedded semiconductor region is a part of the sixth part close to the second partial well region and far from the fifth part. The seventh embedded well region is a part of the second partial well region located on the side of the sixth part far from the fifth part; The source region includes a portion of the source region that surrounds the second JFET region and is adjacent to the first partial well region, and a portion of the source region that surrounds the second JFET region and is adjacent to the second partial well region. The first gate structure surrounds the second JFET region. The seventh sub-gate structure is located on a side of the first gate structure close to the second JFET region, and the seventh sub-gate structure covers the source region, the second partial well region, and a portion of the fourth portion that are sequentially adjacent in the third direction. The eighth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the eighth sub-gate structure covers the source region, the second partial well region, and a portion of the sixth portion that are sequentially adjacent in the third direction. The first gate structure covers a portion of the source region that surrounds the second JFET region and is adjacent to the first partial well region, the first partial well region, and a portion of the first JFET region that surrounds the well region.

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