Cell structure of MOSFET device

Abstract

The present invention provides a cellular structure of a MOSFET device, wherein the cellular region of the cellular structure includes: a first JFET region and a second JFET region, wherein the first JFET region is located at least on both sides of the second JFET region; a well region located between the first JFET region and the second JFET region; a source region located in the well region and surrounding the second JFET region, wherein the well region between the source region and the first JFET region is a first partial well region, and the well region between the source region and the second JFET region is a second partial well region; a well contact region located in part of the second partial well region, so that the remaining second partial well region has a channel region adjacent to the source region and the second JFET region respectively; a second gate structure covering part of the channel region and part of the source region and part of the second JFET region adjacent to part of the channel region respectively. The present application solves the problem of large reverse freewheeling turn-on voltage and high reverse recovery loss of the existing MOSFET when the body diode is used as a freewheeling path.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a cell structure of a MOSFET device. Background Art

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, has broad application prospects in high voltage, high power, high temperature and high frequency applications due to its advantages such as wide bandgap, high critical electric field strength, high thermal conductivity and high saturation drift velocity.

[0003] SiC VDMOS, with its excellent on-off and blocking trade-off characteristics and high operating junction temperature, has replaced Si-based devices in traditional rectification and accelerated industrial development in fields such as rectification and inversion. However, due to the wide bandgap of silicon carbide, the forward voltage drop of the body diode in SiC VDMOS often exceeds 2.7V. This results in a high body diode turn-on voltage and large reverse recovery losses in the freewheeling state of SiCVDMOS, which becomes a shortcoming in freewheeling operation. In addition, the electron-hole recombination process in the body diode of SiCVDMOS in the working state easily causes the expansion of defects in the silicon carbide material, causing degradation of device characteristics and shortening the device's operating life.

[0004] To solve the above problems, there are currently two main solutions:

[0005] (1) Anti-parallel Schottky diode outside MOS;

[0006] (2) Integrate Schottky diodes into MOS chips.

[0007] However, for the first solution, the increase in the number and area of ​​chips in the device will lead to increased costs and complicated packaging design, which will lead to an increase in parasitic effects and processes, and thus cause more failure modes.

[0008] For the second solution, the current design of the Schottky diode has a weak ability to withstand surge current during reverse freewheeling and may also cause the distance between adjacent cells to increase.

[0009] Therefore, there is an urgent need for a MOSFET device that can at least solve the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the MOSFET is used as a freewheeling path. Summary of the Invention

[0010] The main purpose of the present invention is to provide a cell structure of a MOSFET device to at least solve the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the MOSFET is used as a freewheeling path.

[0011] In order to achieve the above-mentioned object, the present invention provides a cellular structure of a MOSFET device, the cellular structure comprising a substrate and an epitaxial layer and a cellular region located on one side of the substrate, the cellular region being located in the epitaxial layer, the cellular region comprising: a first JFET region and a second JFET region, the first JFET region being located at least on both sides of the second JFET region; a well region being located between the first JFET region and the second JFET region, the well region being of opposite conductivity to the epitaxial layer; a source region being located in the well region and surrounding the second JFET region, the well region between the source region and the first JFET region being a first partial well region, and the well region between the source region and the second JFET region being a first partial well region. The well region is the second partial well region; the well contact region is located in part of the second partial well region, so that the remaining second partial well region has a channel region adjacent to the source region and the second JFET region respectively, the well contact region and the well region have the same doping type, and the doping concentration of the well contact region is higher than the doping concentration of the well region; the gate structure includes adjacent first gate structures and second gate structures, the first gate structure covers the first partial well region and part of the source region and at least part of the first JFET region respectively adjacent to the first partial well region, and the second gate structure covers part of the channel region and part of the source region and part of the second JFET region respectively adjacent to the part of the channel region.

[0012] Optionally, the well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively; or the well contact region is adjacent to the source region and the second JFET region respectively.

[0013] Optionally, the cellular structure also includes: a Schottky metal covering part of the second JFET region; an ohmic contact metal covering at least part of the well contact region and being arranged in contact with the ohmic contact metal; wherein, when the well contact region is adjacent to the source region and part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the second partial well region and part of the source region respectively adjacent to the well contact region; and when the well contact region is respectively adjacent to the source region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the source region adjacent to the well contact region.

[0014] Optionally, the epitaxial layer has a first surface on the side facing away from the substrate, and when the well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively, the first surface corresponding to the second JFET region is the first region surface, the first region surface includes the adjacent first sub-region and second sub-region, and the side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; the first surface corresponding to the second partial well region is the second region surface, the second region surface includes the adjacent third sub-region and fourth sub-region, the third sub-region is the first surface corresponding to the channel region, and the fourth sub-region is the second region surface excluding the third sub-region; the Schottky metal covers the first sub-region and part of the fourth sub-region.

[0015] Optionally, the first surface corresponding to the first portion of the well region is the surface of the third region, the first surface corresponding to the source region is the surface of the fourth region, and at least a portion of the surface of the fourth region is located between the surface of the second region and the surface of the third region; the portion of the surface of the first region covered by the second gate structure is the fifth sub-region, the portion of the surface of the fourth region covered by the second gate structure is the sixth sub-region, and the third sub-region is located between the fifth sub-region and the sixth sub-region; the first surface corresponding to the first JFET region is the surface of the fifth region, the portion of the surface of the fifth region covered by the first gate structure is the seventh sub-region, and the surface of the third region is located between at least a portion of the surface of the fourth region and the seventh sub-region.

[0016] Optionally, the epitaxial layer has a first surface on a side facing away from the substrate, the well region has a first preset pattern in a cross section parallel to the first surface, and the side lines of the first preset pattern are polygonal.

[0017] Optionally, in the case where the polygon is a first rectangle, the second JFET region includes a first sub-JFET region and a second sub-JFET region that are spaced apart, the second partial well region includes a portion located between the first sub-JFET region and the second sub-JFET region and another portion other than the portion, and the well contact region is arranged in a portion of the second partial well region located between the first sub-JFET region and the second sub-JFET region; in a direction perpendicular to a line connecting the first sub-JFET region and the second sub-JFET region, the first partial well region includes a first sub-well region located on the left side of the line and a second sub-well region located on the right side of the line; the Schottky metal includes a first sub-Schottky metal and a second sub-Schottky metal that are spaced apart, and in the first sub-JFET region includes a portion of the first sub-JFET region close to one side of the second sub-JFET region, a portion of the first sub-JFET region away from the second sub-JFET region In the case of a portion of the first sub-JFET region on one side of the two sub-JFET regions and another portion of the first sub-JFET region located between the two portions of the first sub-JFET region, the portion of the first sub-JFET region in the first sub-JFET region close to the second sub-JFET region is a first Schottky region, and the first sub-Schottky metal at least covers the first Schottky region. In the case of the second sub-JFET region including a portion of the second sub-JFET region close to the first sub-JFET region, a portion of the second sub-JFET region away from the first sub-JFET region and another portion of the second sub-JFET region located between the two portions of the first sub-JFET region, the portion of the second sub-JFET region in the second sub-JFET region close to the first sub-JFET region is a second Schottky region, and the second sub-Schottky metal at least covers the second Schottky region.

[0018] Optionally, the second gate structure includes a first sub-gate structure and a second sub-gate structure, the first sub-gate structure is located on a side of the first sub-Schottky metal away from the second sub-Schottky metal, and the second sub-gate structure is located on a side of the second sub-Schottky metal away from the first sub-Schottky metal; the portion of the first sub-JFET region in the first sub-JFET region away from the second sub-JFET region is a first embedded semiconductor region, the first sub-gate structure covers the first embedded semiconductor region, the portion of the second partial well region surrounding the first embedded semiconductor region, and the portion of the source region surrounding the first embedded well region, and the first embedded well region is the portion of the second partial well region adjacent to the first embedded semiconductor region; the portion of the second sub-JFET region in the second sub-JFET region away from the first sub-JFET region is a second embedded semiconductor region, the second sub-gate structure covers the second embedded semiconductor region, the portion of the second partial well region surrounding the second embedded semiconductor region, and the portion of the source region surrounding the second embedded well region, and the second embedded well region is the portion of the second partial well region adjacent to the second embedded semiconductor region.

[0019] Optionally, the first gate structure includes a third sub-gate structure and a fourth sub-gate structure, the third sub-gate structure is located on the left, and the fourth sub-gate structure is located on the right, the third sub-gate structure is respectively arranged in contact with the first sub-gate structure and the second sub-gate structure, and the first sub-gate structure and the second sub-gate structure are also arranged in contact with the fourth sub-gate structure; the source region includes a portion of the source region of the second partial well region away from the second JFET region and close to the first sub-well region, and a portion of the source region of the second partial well region away from the second JFET region and close to the second sub-well region, the third sub-gate structure covers a portion of the source region of the second partial well region away from the second JFET region and close to the first sub-well region, the third sub-gate structure also covers the first sub-well region and a portion of the first JFET region located on the side of the first sub-well region away from the first sub-JFET region and the second sub-JFET region; the fourth sub-gate structure covers a portion of the source region of the second partial well region away from the second JFET region and close to the second sub-well region, the fourth sub-gate structure also covers the second sub-well region and a portion of the first JFET region located on the side of the second sub-well region away from the first sub-JFET region and the second sub-JFET region.

[0020] Optionally, the epitaxial layer has a first surface on a side facing away from the substrate, the first surface has a trench, and at least a portion of the well region extends from a portion of the surface of the trench into the epitaxial layer.

[0021] Optionally, a contact surface between the second partial well region and the gate structure includes a {0-33-8} crystal plane.

[0022] Optionally, the first surface corresponding to the trench includes a bottom surface and sidewalls, and a portion of the well region extends from a portion of the bottom surface of the trench into the epitaxial layer.

[0023] Optionally, the first surface corresponding to the trench includes a bottom surface and sidewalls, and a portion of the well region extends from the entire bottom surface of the trench into the epitaxial layer.

[0024] Optionally, the first surface corresponding to the trench includes a bottom surface and sidewalls, and a portion of the well region extends from the entire bottom surface and a portion of the sidewalls of the trench into the epitaxial layer.

[0025] Optionally, the first surface corresponding to the trench includes a bottom surface and sidewalls, and the cellular structure further includes: a silicon oxide layer covering a portion of the sidewalls of the trench where the second partial well region is located.

[0026] Optionally, when the polygon is a second rectangle, the well contact region includes a first partial well contact region, a second partial well contact region and a third partial well contact region that are adjacent to each other, and the first partial well contact region, the second partial well contact region and the third partial well contact region are located one by one on three sides of the second JFET region; when the well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively, part of the second partial well region is adjacent to the first partial well contact region and the second JFET region respectively, part of the second partial well region is adjacent to the second partial well contact region and the second JFET region respectively, and part of the second partial well region is adjacent to the third partial well contact region and the second JFET region respectively; when the well contact region is adjacent to the source region and the second JFET region respectively, the second JFET region is adjacent to the first partial well contact region, the second partial well contact region and the third partial well contact region respectively.

[0027] Optionally, the second JFET region has a third rectangle in a cross section parallel to the first surface, and the third rectangle is located in the second rectangle; the first JFET region surrounds the well region, and the second JFET region has a first end and a second end opposite to each other in a first direction, and the first direction is parallel to the first surface; the source region surrounds the second partial well region, and the first partial well region surrounds the source region; the Schottky metal covers part of the second JFET region at the first end, and the Schottky metal also covers part of the second partial well region that contacts the third Schottky region, the third Schottky region is the part of the second JFET region covered by the Schottky metal at the first end, and the well contact region is located in the second partial well region and semi-surrounds the second JFET region at the first end; the second gate structure covers the third embedded semiconductor region, surrounding A portion of the second partial well region surrounding the third embedded semiconductor region and a portion of the source region surrounding the third embedded well region, the third embedded semiconductor region is a portion of the second JFET region at the second end, and the third embedded well region is a portion of the second partial well region adjacent to the third embedded semiconductor region; the source region includes a portion of the source region surrounding the second JFET region and close to the first partial well region and a portion of the source region surrounding the second JFET region and close to the second partial well region, the first gate structure surrounds the second JFET region, the second gate structure is located on a side of the first gate structure close to the second JFET region, and the first gate structure covers a portion of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region, and a portion of the first JFET region surrounding the outer periphery of the well region.

[0028] Optionally, when the polygon is a first hexagon or a first octagon, the well contact region includes a fourth partial well contact region and a fifth partial well contact region that are spaced apart, and the fourth partial well contact region and the fifth partial well contact region are respectively located on opposite sides of the second JFET region; when the well contact region is adjacent to the source region and part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, part of the second partial well region is located between the fourth partial well contact region and the second JFET region, and part of the second partial well region is located between the fifth partial well contact region and the second JFET region; when the well contact region is respectively adjacent to the source region and the second JFET region, the fourth partial well contact region is respectively adjacent to part of the source region and the second JFET region, and the fifth partial well contact region is respectively adjacent to part of the source region and the second JFET region.

[0029] Optionally, in the case where the polygon is a first hexagon, the second JFET region has a first irregular figure in a cross section parallel to the first surface, the first irregular figure is located in the first hexagon, the first irregular figure includes a second hexagon and two first preset patterns, the two first preset patterns are respectively contacted and arranged on two opposite sides of the second hexagon in the second direction, and the second direction is parallel to the first surface; the first JFET region surrounds the well region, and the second JFET region has a first part, a second part and a third part that are contacted and arranged in the second direction, the second part is located between the first part and the third part, the well region of the second part is respectively contacted with a side of the first part away from the second part and a side of the third part away from the second part, and the first part and the third part are contacted with the two The first preset pattern corresponds one to one, and the second part corresponds to the second hexagon; the source region surrounds the second part of the well region, and the first part of the well region surrounds the source region; the Schottky metal covers at least part of the second part; the well contact region includes a first part doped region and a second part doped region, the first part doped region and the second part doped region are located on opposite sides of the second JFET region in a direction perpendicular to the second direction, the source region, the second part of the well region and the first part are sequentially adjacent in the second direction, the source region, the second part of the well region and the third part are sequentially adjacent in the second direction, the source region, the first part of the doped region, the second part of the well region and the second part are sequentially adjacent in a direction perpendicular to the second direction, and the source region, the second part of the doped region, the second part of the well region and the second part are sequentially adjacent in a direction perpendicular to the second direction.

[0030] Optionally, the second gate structure includes a fifth sub-gate structure and a sixth sub-gate structure located on opposite sides of the Schottky metal in the second direction; the first part includes a portion of the first part close to the second partial well region and away from the second part and a portion of the first part close to the second part and away from the second partial well region, the fifth sub-gate structure covers the fourth embedded semiconductor region, the portion of the second partial well region in contact with the fourth embedded semiconductor region, and the portion of the source region in contact with the fourth embedded well region, the fourth embedded semiconductor region is the portion of the first part close to the second partial well region and away from the second part, and the fourth embedded well region is the portion of the second partial well region located on the side of the first part away from the second part; the third part includes a portion of the third part close to the second partial well region and away from the second part and a portion of the third part close to the second part and away from the second partial well region, the sixth sub-gate structure covers the fifth embedded semiconductor region, the portion of the second partial well region in contact with the fifth embedded semiconductor region, and the portion of the source region in contact with the fifth embedded well region, the The fifth embedded semiconductor region is a portion of the third portion close to the second partial well region and away from the second portion, and the fifth embedded well region is a portion of the second partial well region located on the side of the third portion away from the second portion; the source region includes a portion of the source region surrounding the second JFET region and close to the first partial well region and a portion of the source region surrounding the second JFET region and close to the second partial well region, the first gate structure surrounds the second JFET region, the fifth sub-gate structure is located on the side of the first gate structure close to the second JFET region, and the fifth sub-gate structure covers the portion of the source region, the second partial well region and the portion of the first portion that are sequentially adjacent in the second direction, the sixth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the sixth sub-gate structure covers the portion of the source region, the second partial well region and the portion of the third portion that are sequentially adjacent in the second direction, the first gate structure covers the portion of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region and the portion of the first JFET region surrounding the well region.

[0031] Optionally, in the case where the polygon is a first octagon, the second JFET region has a second irregular figure in a cross section parallel to the first surface, the second irregular figure is located in the first octagon, the second irregular figure includes a second octagon and two second preset patterns, the two second preset patterns are contacted and arranged on two opposite sides of the second octagon in a third direction, and the third direction is parallel to the first surface; the first JFET region surrounds the well region, and the second JFET region has a fourth portion, a fifth portion and a sixth portion that are contacted and arranged in the third direction, the fifth portion is located between the fourth portion and the sixth portion, the side of the fourth portion away from the fifth portion and the side of the sixth portion away from the fifth portion are respectively contacted with the second portion of the well region, and the fourth portion and the sixth portion are contacted with the two The second preset patterns correspond one to one, and the fifth part corresponds to the second octagon; the source region surrounds the second part of the well region, and the first part of the well region surrounds the source region; the Schottky metal covers the fifth part; the well contact region includes the third part of the doped region and the fourth part of the doped region, and the third part of the doped region and the fourth part of the doped region are located on opposite sides of the second JFET region in the direction perpendicular to the third direction, the source region, the second part of the well region and the fourth part are sequentially adjacent in the third direction, the source region, the third part of the doped region, the second part of the well region and the sixth part are sequentially adjacent in the third direction, the source region, the third part of the doped region, the second part of the well region and the fourth part are sequentially adjacent in the direction perpendicular to the third direction, and the source region, the fourth part of the doped region, the second part of the well region and the sixth part are sequentially adjacent in the direction perpendicular to the third direction.

[0032] Optionally, the second gate structure includes a seventh sub-gate structure and an eighth sub-gate structure located on opposite sides of the Schottky metal in the third direction; the fourth part includes a partial fourth part close to the second partial well region and away from the fifth part and a partial fourth part close to the fifth part and away from the second partial well region, the seventh sub-gate structure covers the sixth embedded semiconductor region, the partial second partial well region in contact with the sixth embedded semiconductor region, and the partial source region in contact with the sixth embedded well region, the sixth embedded semiconductor region is the partial fourth part close to the second partial well region and away from the fifth part, and the sixth embedded well region is the part of the second partial well region located on the side of the fourth part away from the fifth part; the sixth part includes a partial sixth part close to the second partial well region and away from the fifth part and a partial sixth part close to the fifth part and away from the second partial well region, the eighth sub-gate structure covers the seventh embedded semiconductor region, the partial second partial well region in contact with the seventh embedded semiconductor region, and the partial source region in contact with the seventh embedded well region region, the seventh embedded semiconductor region is the partial sixth portion close to the second partial well region and away from the fifth portion, and the seventh embedded well region is the portion of the second partial well region located on the side of the sixth portion away from the fifth portion; the source region includes a partial source region surrounding the second JFET region and close to the first partial well region and a partial source region surrounding the second JFET region and close to the second partial well region, the first gate structure surrounds the second JFET region, the seventh sub-gate structure is located on the side of the first gate structure close to the second JFET region, and the seventh sub-gate structure covers the source region, the second partial well region and part of the fourth portion sequentially adjacent in the third direction, the eighth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the eighth sub-gate structure covers the source region, the second partial well region and part of the sixth portion sequentially adjacent in the third direction, the first gate structure covers the partial source region surrounding the second JFET region and close to the first partial well region, the first partial well region and part of the first JFET region surrounding the well region.

[0033] The technical solution of the present invention is applied to a cell structure of a MOSFET device, the cell structure comprising a substrate, an epitaxial layer located on one side of the substrate, and a cell region, the cell region being located in the epitaxial layer, the cell region comprising: a first JFET region and a second JFET region spaced apart, the first JFET region being located at least on both sides of the second JFET region; a well region located between the first JFET region and the second JFET region, the well region having a conductivity type opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, the well region between the source region and the first JFET region being a first partial well region, and the well region between the source region and the second JFET region being a first partial well region. The well region is the second partial well region; the well contact region is located in part of the second partial well region, so that the remaining second partial well region has a channel region adjacent to the source region and the second JFET region respectively, the well contact region and the well region have the same doping type, and the doping concentration of the well contact region is higher than the doping concentration of the well region; the gate structure includes adjacent first gate structures and second gate structures, the first gate structure covers the first partial well region and part of the source region and at least part of the first JFET region respectively adjacent to the first partial well region, and the second gate structure covers part of the channel region and part of the source region and part of the second JFET region respectively adjacent to the part of the channel region.

[0034] As can be seen, the present application can integrate a Schottky diode into a MOSFET device. Since the turn-on voltage of the Schottky diode is lower than that of a traditional body diode, the turn-on time is greatly reduced. Thus, the present application improves the problem of the high turn-on voltage of traditional MOSFETs, which is beneficial to the conduction of reverse current in the MOSFET. Moreover, since the conduction of the Schottky diode has unipolar conductivity, this can prevent the bipolar degradation effect of the MOSFET at low current density and before the PN junction begins to inject, while reducing reverse recovery current and reverse recovery loss. In addition, when the first gate structure covers the first partial well region and the portion of the source region and at least a portion of the first JFET region respectively adjacent to the first partial well region, the first partial well region can have a first conductive channel. When the second gate structure covers the channel region in the second partial well region and the partial source region and the partial second JFET region adjacent to the partial channel region, the second partial well region can have a second conductive channel. That is, the present application integrates a hybrid PIN Schottky diode (MPS) in the well region of the MOSFET device, so that the channel width of the MOSFET device is increased through the above-mentioned second conductive channel without increasing the cell width in the MOSFET device and retaining the original first conductive channel in the MOSFET device. Therefore, during the forward conduction period of the MOSFET device, the current density under the well region and the second JFET region of the MOSFET device can be increased, so that the MOSFET device has good forward conduction characteristics. Based on this, the present application solves the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the existing MOSFET is used as a freewheeling path. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0036] Figure 1 A schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in the first embodiment of the present invention along the AA' direction is shown;

[0037] Figure 2 A schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in the BB' direction according to the first embodiment of the present invention is shown;

[0038] Figure 3 A schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in a second embodiment of the present invention along the BB' direction is shown;

[0039] Figure 4FIG2 shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in a third embodiment of the present invention along the BB' direction;

[0040] Figure 5 FIG2 shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in a fourth embodiment of the present invention along the BB' direction;

[0041] Figure 6 FIG2 shows a schematic cross-sectional structure diagram of a cell structure of a MOSFET device provided in a fifth embodiment of the present invention along the BB' direction;

[0042] Figure 7 A perspective view of a cell structure of a MOSFET device provided in a first embodiment of the present invention in a direction perpendicular to the first surface of the epitaxial layer is shown;

[0043] Figure 8 Shown in Figure 7 A perspective view of the structure shown, with gate structure and ohmic contact metal covered;

[0044] Figure 9 FIG2 shows a perspective view of a cell structure of a MOSFET device provided in a sixth embodiment of the present invention in a direction perpendicular to the first surface of the epitaxial layer;

[0045] Figure 10 Shown in Figure 9 A perspective view of the structure shown, with gate structure and ohmic contact metal covered;

[0046] Figure 11 FIG2 shows a perspective view of a cell structure of a MOSFET device provided in a seventh embodiment of the present invention in a direction perpendicular to the first surface of the epitaxial layer;

[0047] Figure 12 Shown in Figure 10 A perspective view of the structure shown, with gate structure and ohmic contact metal covered;

[0048] Figure 13 FIG2 shows a perspective view of a cell structure of a MOSFET device provided in an eighth embodiment of the present invention in a direction perpendicular to the first surface of the epitaxial layer;

[0049] Figure 14 Shown in Figure 13 A perspective view of the structure shown, with gate structure and ohmic contact metal covered;

[0050] Figure 15FIG2 shows a perspective view of a cell structure of a MOSFET device provided in an eighth embodiment of the present invention in a direction perpendicular to the first surface of the epitaxial layer;

[0051] Figure 16 Shown in Figure 15 Based on the above structure, a perspective view is shown after the ohmic contact metal is formed.

[0052] The above drawings include the following reference numerals:

[0053] 100, substrate; 101, silicon carbide material layer; 102, silicon oxide layer; 200, epitaxial layer; 201, first sub-epitaxial layer; 202, second sub-epitaxial layer; 203, JFET doping region; 300, well region; 301, second partial well region; 3011, channel region; 302, first partial well region; 400, source region; 500, well contact region; 601, ohmic contact metal; 602, Schottky metal; 60 21. First sub-Schottky metal; 6022. Second sub-Schottky metal; 700. Gate structure; 701. Polysilicon; 702. Gate oxide layer; 703. Dielectric layer; 800. Back metal layer; 900. Front metal layer; 10. Second JFET region; 11. First sub-JFET region; 12. Second sub-JFET region; 20. First JFET region; 30. Second gate structure; 40. First gate structure. DETAILED DESCRIPTION

[0054] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0055] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0057] As described in the background art, when the body diode of a MOSFET in the prior art is used as a freewheeling path, the reverse freewheeling turn-on voltage is large and the reverse recovery loss is high. In order to at least solve the above technical problems, the present application provides a MOSFET device.

[0058] According to one aspect of the present invention, a cell structure of a MOSFET device is provided, such as Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 and Figure 6 As shown, the cell structure includes a substrate 100, an epitaxial layer 200 and a cell region. The epitaxial layer 200 is located on one side of the substrate 100. The epitaxial layer 200 has a first surface 1a facing away from the substrate 100. The cell region extends from the first surface 1a to the epitaxial layer 200. Figure 1 、 Figure 2 and Figure 3 As shown, the cell region includes a first JFET region 20 and a second JFET region 10, a well region 300, a source region 400, a well contact region 500 and a gate structure 700. Further, the first JFET region 20 is located at least on both sides of the second JFET region 10. Further, each cell region may include one or more second JFET regions 10, and in the case where the second JFET region 10 includes two, as shown in FIG. Figure 7 As shown, the second JFET region 10 may include a first sub-JFET region 11 and a second sub-JFET region 12 that are spaced apart.

[0059] Specifically, if Figures 1 to 6 As shown, the substrate 100 has a second surface 1 b on a side facing away from the epitaxial layer 200 . The MOSFET device further includes a back metal layer 800 on the second surface 1 b and an ohmic contact metal 601 and a Schottky metal 602 on the first surface 1 a .

[0060] Specifically, the stacked substrate 100 and epitaxial layer 200 may both be silicon carbide material layers 101 .

[0061] Specifically, the substrate 100 may be 4H-SiC, and the doping concentration may be 5E18~5E21cm -3 , the thickness can be 50~500μm.

[0062] Specifically, if Figures 1 to 6 As shown, the epitaxial layer 200 may include a first sub-epitaxial layer 201, a second sub-epitaxial layer 202 and a JFET doping region 203 in a direction perpendicular to the first surface 1a. It should be noted that the JFET doping region 203 may be considered as follows: Figure 7 A second JFET region 10 is shown.

[0063] Optionally, the first sub-epitaxial layer 201 , the second sub-epitaxial layer 202 and the JFET doping region 203 may all be grown by an epitaxial process.

[0064] Optionally, the first sub-epitaxial layer 201 and the second sub-epitaxial layer 202 may be formed by an epitaxial process, and the JFET doping region 203 may be formed by ion implantation.

[0065] The first epitaxial sub-layer 201 may be a field stop layer, the second epitaxial sub-layer 202 may be a drift layer, and the JFET doped region 203 may be a junction field-effect transistor (JFET).

[0066] Specifically, the doping concentration of the JFET doping region 203 may be greater than the doping concentration of the second sub-epitaxial layer 202 .

[0067] Specifically, the doping concentration of the first epitaxial sub-layer 201 can be 5E15~1E19cm -3 , the thickness can be 5~50μm.

[0068] Specifically, the doping concentration of the second epitaxial sub-layer 202 can be 1E15~5E17cm -3 , the thickness can be 5~100μm.

[0069] Specifically, the doping concentration of the JFET doping region 203 may be 5E15-1E18 cm -3 , the thickness can be 0.5~5μm.

[0070] Combine Figure 1 、 Figure 2 and Figure 7As shown, a well region 300 is located between the first JFET region 20 and the second JFET region 10, and the conductivity type of the well region 300 is opposite to that of the epitaxial layer 200. A source region 400 is located in the well region 300 and surrounds the second JFET region 10. Furthermore, the well region 300 between the source region 400 and the first JFET region 20 is a first partial well region 302, and the well region 300 between the source region 400 and the second JFET region 10 is a second partial well region 301. A well contact region 500 is located in a portion of the second partial well region 301, so that the remaining second partial well region 301 has a channel region 3011 adjacent to the source region 400 and the second JFET region 10, respectively (it will be understood that the channel region 3011 is a portion of the second partial well region 301). The well contact region 500 and the well region 300 have the same conductivity type, and the doping concentration of the well contact region 500 is higher than that of the well region 300.

[0071] Specifically, the first partial well region 302 and the second partial well region 301 in the above MOSFET device may be connected in the epitaxial layer 200 .

[0072] Specifically, the doping concentration of the well region 300 may be 1e16~5e19cm -3 The implantation depth can be 0.5~5μm; the doping concentration of the well contact region 500 can be 5e17~5e21cm -3 , the injection depth can be 0.3~5μm.

[0073] Specifically, the doping concentration of the source region 400 can be 1e18~5E21cm -3 , the injection depth is 0.1~3μm.

[0074] Combine Figure 2 and Figure 8 As shown, in order to form a Schottky barrier in the area corresponding to the second JFET region 10 , the Schottky metal 602 may cover a portion of the second JFET region 10 .

[0075] Optionally, the material of the Schottky metal 602 includes, but is not limited to, any one or more of Ti, Al, W, Mo, TiC, TiW, NiCr, Au, and Ni. Exemplarily, the thickness of the Schottky metal 602 is 0.01-1 μm.

[0076] In some embodiments, in order to reduce the ohmic contact resistance, the ohmic contact metal 601 is located on the first surface, and the ohmic contact metal 601 can cover at least a portion of the well contact region 500. Specifically, as Figure 8 As shown, the ohmic contact metal 601 may completely cover the well contact region 500; or Figure 10 、 Figure 12 and Figure 14As shown, the ohmic contact metal 601 may cover a portion of the well contact region 500. Figure 8 、 Figure 10 、 Figure 12 and Figure 14 As shown, the ohmic contact metal 601 and the Schottky metal 602 may be provided in contact with each other.

[0077] Optionally, the material of the ohmic contact metal 601 is selected from any one or more combinations of Ni, Ti, Al, Ag, Au, AlSi, Pt, Pd, Ta and Co.

[0078] Optionally, the thickness of the ohmic contact metal 601 on the first surface is 0.01-1 μm.

[0079] Combine Figure 1 、 Figure 7 and Figure 8 As shown, the gate structure 700 may be located on the first surface 1a and spaced apart from the ohmic contact metal 601. The gate structure 700 includes a first gate structure 40 and a second gate structure 30 that are adjacent to each other. The first gate structure 40 covers the first partial well region 302, the portion of the source region 400 that is respectively adjacent to the first partial well region 302, and at least a portion of the first JFET region 20. The second gate structure 30 covers a portion of the channel region 3011, the portion of the source region 400 that is respectively adjacent to the portion of the channel region 3011, and a portion of the second JFET region 10 that is respectively adjacent to the portion of the channel region 3011.

[0080] Specifically, if Figure 1 、 Figure 2 and Figure 3 As shown, the gate structure 700 may include polysilicon 701 , a gate oxide layer 702 and a dielectric layer 703 .

[0081] The gate oxide layer 702 can be formed by thermal oxidation, deposition of SiO2, or oxidation after deposition of Si. For example, the thickness of the gate oxide layer 702 can be 10 to 200 nm. The polysilicon 701 is formed by phosphorus implantation and diffusion after deposition on the gate oxide layer 702. For example, the doping concentration of the polysilicon 701 can be 1e19 to 1e20 cm -3 The thickness of the polysilicon layer 701 may be 0.1-1 μm. For example, the thickness of the dielectric layer 703 may be 0.5-5 μm.

[0082] It can be understood that the Schottky metal 602 , the epitaxial layer 200 , the substrate 100 and the back metal layer 800 can constitute a Schottky diode.

[0083] Specifically, if Figures 3 to 6As shown, the MOSFET device may further include a front metal layer 900 . The front metal layer 900 is located on a side of the Schottky metal 602 away from the epitaxial layer 200 .

[0084] For example, the material of the front metal layer 900 includes, but is not limited to, any one or more of Al, Au, Cu, and Si. The thickness of the front metal layer 900 may be 0.1-1 μm.

[0085] In summary, the present application can integrate a Schottky diode into a MOSFET device. Since the turn-on voltage of the Schottky diode is lower than that of a traditional body diode, the turn-on time is greatly reduced. Thus, the present application improves the high turn-on voltage problem of traditional MOSFETs, which is beneficial for the conduction of reverse current in the MOSFET. Furthermore, since the conduction of the Schottky diode has unipolar conductivity, this allows the MOSFET to avoid bipolar degradation effects at low current densities and before the PN junction begins to inject, while also reducing reverse recovery current and reverse recovery losses. Furthermore, when the first gate structure 40 covers the first partial well region 302 and the portion of the source region 400 and at least a portion of the first JFET region 20 adjacent to the first partial well region 302, the first partial well region 302 can have a first conductive channel. When the second gate structure 30 covers the channel region 3011 in the second partial well region 301 and the portion of the source region 400 and the portion of the second JFET region 10 adjacent to the portion of the channel region 3011, the second partial well region 301 may have a second conductive channel (the aforementioned channel region 3011). That is, by integrating a hybrid PIN Schottky diode (MPS) in the well region 300 of the MOSFET device, the channel width of the MOSFET device is increased without increasing the cell width of the MOSFET device and retaining the original first conductive channel of the MOSFET device. Furthermore, during the forward conduction period of the MOSFET device, the current density below the well region 300 and the Schottky contact region (second JFET region 10) of the MOSFET device can be increased, resulting in the MOSFET device having good forward conduction characteristics. Based on this, the present application solves the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the existing MOSFET is used as a freewheeling path.

[0086] Under low injection conditions, that is, when the device operates at a lower current density, the reverse recovery loss of the body diode in the device is further reduced, and the overall characteristics of the device are further improved. In some embodiments, Figures 9 to 12As shown, the well contact region 500 is adjacent to the source region 400 and part of the second partial well region 301 is adjacent to the well contact region 500 and the second JFET region 10 respectively; on this basis, the above-mentioned ohmic contact metal 601 can also cover part of the second partial well region 301 and part of the source region 400 respectively adjacent to the well contact region 500.

[0087] Under large injection conditions, that is, when the device operates at a high current density, the conduction voltage drop of the body diode in the device is further reduced. In other embodiments, Figure 13 and Figure 14 As shown, the well contact region 500 can be disposed adjacent to the source region 400 and the second JFET region 10. On this basis, the ohmic contact metal 601 can also cover portions of the source region 400 adjacent to the well contact region 500. However, for any of the above embodiments, portions of the second partial well region 301 can also be adjacent to the source region 400 and the second JFET region 10 to form the channel region 3011.

[0088] In some optional embodiments, such as Figures 7 to 14 As shown, in order to optimize the electrical performance of the MOSFET, improve the withstand voltage capability, reduce the electric field concentration, and achieve a good ohmic contact and conductivity modulation effect, the second JFET region 10 extends from the first surface into the epitaxial layer so that the first surface corresponding to the second JFET region 10 is a first region surface, the first region surface includes a first sub-region and a second sub-region adjacent to each other, and the side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; the second partial well region 301 extends from the first surface into the epitaxial layer so that the first surface corresponding to the second partial well region 301 is a second region surface, the second region surface includes a third sub-region and a fourth sub-region adjacent to each other, the third sub-region is the first surface corresponding to the channel region 3011, and the fourth sub-region is the second region surface excluding the third sub-region; when the well contact region is adjacent to the source region and the second JFET region respectively, the Schottky metal 602 covers the first sub-region, or when the well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively, the Schottky metal 602 covers the first sub-region and part of the fourth sub-region.

[0089] In some optional embodiments, combined with Figures 7 to 14As shown, the first partial well region 302 extends from the first surface into the epitaxial layer, so that the first surface corresponding to the first partial well region 302 is the third region surface; the source region 400 extends from the first surface into the well region 300, so that the first surface corresponding to the source region 400 is the fourth region surface, and at least part of the fourth region surface is located between the second region surface and the third region surface; the portion of the first region surface covered by the second gate structure 30 is the fifth sub-region, the portion of the fourth region surface covered by the second gate structure 30 is the sixth sub-region, and the third sub-region is located between the fifth sub-region and the sixth sub-region; the first JFET region 20 extends from the first surface into the epitaxial layer, so that the first surface corresponding to the first JFET region 20 is the fifth region surface, the portion of the fifth region surface covered by the first gate structure 40 is the seventh sub-region, and the third region surface is located between at least part of the fourth region surface and the seventh sub-region. It can be seen that the first partial well region 302 located between the first JFET region 20 and the source region 400 and covered by the first gate structure 40 has a first conductive channel, and the second partial well region 301 located between the second JFET region 10 and the source region 400 and covered by the second gate structure 30 has a second conductive channel.

[0090] Alternatively, as Figures 7 to 14 As shown, the well region 300 (the first partial well region 302 and / or the second partial well region 301) has a first preset pattern in a cross section parallel to the first surface, and the side lines of the first preset pattern are polygonal (the pattern enclosed by the side lines appears as a polygon on the first surface).

[0091] For example, Figure 7 and Figure 8 As shown, the first preset pattern is a first rectangle, the second JFET region 10 includes a first sub-JFET region 11 and a second sub-JFET region 12, the second partial well region 301 includes a portion located between the first sub-JFET region 11 and the second sub-JFET region 12, and another portion excluding the portion located between the first sub-JFET region 11 and the second sub-JFET region 12, and the well contact region 500 is provided in the portion of the second partial well region 301 located between the first sub-JFET region 11 and the second sub-JFET region 12. It can be seen that the portion of the second partial well region 301 excluding the portion located between the first sub-JFET region 11 and the second sub-JFET region 12 is located around the first sub-JFET region 11 and the second sub-JFET region 12.

[0092] like Figure 7 and Figure 8As shown, in a direction perpendicular to the line connecting the first sub-JFET region 11 and the second sub-JFET region 12 (i.e., the direction A-A'), the first partial well region 302 includes a first sub-well region (not labeled in the figure) and a second sub-well region (not labeled in the figure). The first sub-well region is located to the left of the first sub-JFET region 11 and the second sub-JFET region 12, respectively, and the second sub-well region is located to the right of the first sub-JFET region 11 and the second sub-JFET region 12, respectively. It will be understood that the left and right sides mentioned above are opposite sides of the line connecting the first sub-JFET region 11 and the second sub-JFET region 12.

[0093] like Figure 7 and Figure 8 As shown, the Schottky metal 602 includes a first sub-Schottky metal 6021 and a second sub-Schottky metal 6022 that are spaced apart. Specifically, when the first sub-JFET region 11 includes a portion of the first sub-JFET region 11 close to the second sub-JFET region 12 (in the BB' direction), a portion of the first sub-JFET region 11 away from the second sub-JFET region 12, and another portion of the first sub-JFET region 11 located between the two portions of the first sub-JFET region 11, the portion of the first sub-JFET region 11 close to the second sub-JFET region 12 in the first sub-JFET region 11 can be considered as the first Schottky region, and the first sub-Schottky metal 6021 covers the first Schottky region, or the first sub-Schottky metal 6021 covers the first Schottky region and the portion of the second partial well region 301 that is in contact with the first Schottky region. It can be understood that when the first sub-JFET region 11 includes a portion of the first sub-JFET region 11 close to the second sub-JFET region 12 (in the B-B' direction) and a portion of the first sub-JFET region 11 away from the second sub-JFET region 12, as well as another portion of the first sub-JFET region 11 located between the above two portions of the first sub-JFET region 11, the other portion of the first sub-JFET region 11 located between the above two portions of the first sub-JFET region 11 may not be covered by the first sub-Schottky metal 6021.

[0094] like Figure 7 and Figure 8As shown, when the second sub-JFET region 12 includes a portion of the second sub-JFET region 12 close to the first sub-JFET region 11 (in the B-B' direction), a portion of the second sub-JFET region 12 away from the first sub-JFET region 11, and another portion of the second sub-JFET region 12 located between the above two portions of the first sub-JFET region 11, the portion of the second sub-JFET region 12 close to the first sub-JFET region 11 in the second sub-JFET region 12 can be considered as a second Schottky region, and the second sub-Schottky metal 6022 covers the second Schottky region or the second sub-Schottky metal 6022 covers the second Schottky region and the portion of the second partial well region 301 that is in contact with the second Schottky region. It can be understood that when the second sub-JFET region 12 includes a portion of the second sub-JFET region 12 close to the first sub-JFET region 11 (in the B-B' direction), a portion of the second sub-JFET region 12 away from the first sub-JFET region 11, and another portion of the second sub-JFET region 12 located between the above two portions of the first sub-JFET region 11, the other portion of the second sub-JFET region 12 located between the above two portions of the second sub-JFET region may not be covered by the second sub-Schottky metal 6022.

[0095] In some embodiments, combined Figure 7 and Figure 8 As shown, there can be one ohmic contact metal 601 , which is located on one side of the Schottky metal 602 (the first sub-Schottky metal 6021 or the second sub-Schottky metal 6022 ). The ohmic contact metal 601 can cover the well contact region 500 and a portion of the source region 400 .

[0096] Alternatively, in other embodiments, the ohmic contact metal 601 can be one, and the ohmic contact metal 601 can be one, and the well contact region 500 has a portion of the second partial well region 301 on both sides of the A-A' direction, that is, in the A-A' direction, the portion of the second partial well region 301 is located between the well contact region 500 and the source region 400. At this time, the ohmic contact metal 601 can cover the well contact region 500, the portion of the second partial well region 301 and the portion of the source region 400.

[0097] In other embodiments, the ohmic contact metal 601 can be one, and the well contact region 500 has two contact regions spaced apart in the BB' direction, and each contact region has a portion of the second partial well region 301 on both sides in the BB' direction. In this case, the ohmic contact metal 601 can cover the above-mentioned two contact regions, a portion of the second partial well region 301 and a portion of the source region 400.

[0098] like Figure 8As shown, the second gate structure 30 may include a first sub-gate structure (not marked in the figure) and a second sub-gate structure (not marked in the figure), the first sub-gate structure is located on the side of the first sub-Schottky metal 6021 away from the second sub-Schottky metal 6022, and the second sub-gate structure is located on the side of the second sub-Schottky metal 6022 away from the first sub-Schottky metal 6021.

[0099] like Figure 7 and Figure 8 As shown, the portion of the first sub-JFET region 11 away from the second sub-JFET region 12 in the first sub-JFET region 11 is the first embedded semiconductor region, the first sub-gate structure covers the first embedded semiconductor region, the portion of the second partial well region 301 surrounding the first embedded semiconductor region, and the portion of the source region 400 surrounding the first embedded well region, and the first embedded well region is the portion of the second partial well region 301 adjacent to the first embedded semiconductor region; (In other words, the first sub-gate structure covers the first embedded semiconductor region, the portion of the second partial well region 301 adjacent to the first embedded semiconductor region, and the portion of the source region 400 located on the side of the portion of the second partial well region 301 adjacent to the first embedded semiconductor region away from the first embedded semiconductor region. The portion of the second sub-JFET region 12 away from the first sub-JFET region 11 in the second sub-JFET region 12 is a second embedded semiconductor region. The second sub-gate structure covers the second embedded semiconductor region, the portion of the second partial well region 301 surrounding the second embedded semiconductor region, and the portion of the source region 400 surrounding the second embedded well region. The second embedded well region is the portion of the second partial well region 301 adjacent to the second embedded semiconductor region (in other words, the second sub-gate structure covers the second embedded semiconductor region, the portion of the second partial well region 301 adjacent to the second embedded semiconductor region, and the portion of the source region 400 located on the side of the portion of the second partial well region 301 adjacent to the second embedded semiconductor region away from the second embedded semiconductor region). It can be understood that for the portion of the first sub-JFET region 11 not covered by the first sub-Schottky metal 6021, there is still a portion of this portion of the first sub-JFET region 11 not covered by the first sub-gate structure.

[0100] like Figure 8 As shown, the first gate structure 40 may include a third sub-gate structure (not marked in the figure) and a fourth sub-gate structure (not marked in the figure), the third sub-gate structure is located on the left side of the line connecting the above-mentioned first sub-JFET region 11 and the second sub-JFET region 12, and the fourth sub-gate structure is located on the right side of the line connecting the above-mentioned first sub-JFET region 11 and the second sub-JFET region 12, and the third sub-gate structure is respectively arranged in contact with the first sub-gate structure and the second sub-gate structure, and the fourth sub-gate structure is also respectively arranged in contact with the first sub-gate structure and the second sub-gate structure.

[0101] Combine Figure 7 and Figure 8As shown, the source region 400 includes a portion of the second partial well region 301 on a side away from the second JFET region 10 and close to the first sub-well region, and a portion of the second partial well region 301 on a side away from the second JFET region 10 and close to the second sub-well region. The third sub-gate structure covers the portion of the source region 400 on a side of the second partial well region 301 away from the second JFET region 10 and close to the first sub-well region. The third sub-gate structure also covers the first sub-well region and a portion of the first JFET region 20 located on the same side of the first sub-well region away from the first sub-JFET region 11 and the second sub-JFET region 12.

[0102] like Figure 7 and Figure 8 As shown, the fourth sub-gate structure covers the second partial well region 301, a portion of the source region 400 away from the second JFET region 10 and close to the second sub-well region. The fourth sub-gate structure also covers the second sub-well region and a portion of the first JFET region 20 located on the same side of the second sub-well region away from the first sub-JFET region 11 and the second sub-JFET region 12.

[0103] In other optional embodiments, such as Figure 15 As shown, the source region surrounding the second JFET region 10 may include portions located on opposite sides of the second JFET region 10 in the AA' direction and portions located on both sides of the second JFET region 10 in the BB' direction. To further improve the ohmic contact, portions of the source region located on both sides of the second JFET region 10 in the BB' direction have partial well contact regions 500, and as shown in FIG. Figure 16 As shown, a portion of the ohmic contact metal 601 covers the portion of the well contact region 500 and the portion of the source region 400 adjacent to the portion of the well contact region 500 .

[0104] Specifically, combined Figure 2 and Figure 7 and Figure 8 As shown, the well contact region 500, the second JFET region 10 (JFET doped region 203), and the Schottky metal 602 can form a hybrid PIN Schottky diode (MPS), thereby enabling the integration of a hybrid PIN Schottky diode (MPS) into a MOSFET device. Furthermore, the doping concentration of the well contact region 500 can be higher than that of the well region 300. Thus, after the well contact region 500 is implanted into the well region 300 to form the well contact region 500, the MOSFET device adds a PN junction to the Schottky barrier diode. This PN junction turns on under high current and injects minority carriers into the epitaxial layer 200 of the MOSFET device. The resulting conductivity modulation effect can significantly reduce the device's resistance. This MOSFET device with an integrated hybrid PIN Schottky diode (MPS) exhibits a low voltage drop during forward conduction and a high withstand voltage capability during reverse bias.

[0105] In order to further improve the blocking capability of the device, in some optional embodiments, such as Figure 3 As shown, the first surface 1a has a trench, and at least part of the well region 300 extends from part of the surface of the trench into the epitaxial layer 200. It is understood that the trench can keep the well region 300 away from the Schottky metal 602, which can improve the blocking performance of the device.

[0106] Specifically, second JFET region 10 has a partial region located in the first surface, and the partial region may be located outside the trench.

[0107] In some optional embodiments, such as Figure 6 As shown, the contact surface between the second portion of the well region (well region 300) and the gate structure 700 includes a {0-33-8} crystal plane. In the above embodiment, such a configuration can further improve the channel mobility in the device.

[0108] To simplify the process, in some optional embodiments, when the first surface corresponding to the trench includes a bottom surface and sidewalls, a portion of the well region extends from a portion of the bottom surface of the trench into the epitaxial layer.

[0109] Alternatively, in other optional embodiments, in order to further improve the electric field concentration at the corners of the trench, part of the well region extends from the entire bottom surface of the trench into the epitaxial layer; or, part of the well region extends from the entire bottom surface and part of the side wall of the trench into the epitaxial layer.

[0110] In some embodiments, to reduce leakage, such as Figure 3 and Figure 6 As shown, the cell structure may further include a silicon oxide layer 102 . The silicon oxide layer 102 may be located on the sidewalls of the trench, and the silicon oxide layer 102 may be located between a portion of the ohmic contact metal 601 and the epitaxial layer 200 .

[0111] In some embodiments, the number of the second JFET region 10 in each cell region may be one, and when the edge line of the first preset pattern is a second rectangle, as shown in FIG. Figures 9 and 10 As shown, the well contact region 500 may include a first partial well contact region (not marked in the figure), a second partial well contact region (not marked in the figure) and a third partial well contact region (not marked in the figure) arranged adjacent to each other. The first partial well contact region, the second partial well contact region and the third partial well contact region may be respectively located on three sides of the second JFET region 10 (it can be understood that the second JFET region 10 has four sides, and the first partial well contact region, the second partial well contact region and the third partial well contact region are located on three sides of the second JFET region 10 in a one-to-one correspondence).

[0112] In the case where the well contact region 500 is adjacent to the source region 400 and part of the second partial well region 301 is adjacent to the well contact region 500 and the second JFET region 10 respectively, part of the second partial well region 301 is adjacent to the first partial well contact region and the second JFET region 10 respectively, part of the second partial well region 301 is adjacent to the second partial well contact region and the second JFET region 10 respectively, and part of the second partial well region 301 is adjacent to the third partial well contact region and the second JFET region 10 respectively; or, in the case where the well contact region 500 is adjacent to the source region 400 and the second JFET region 10 respectively, the first partial well contact region, the second partial well contact region and the third partial well contact region can all be arranged adjacent to the second JFET region 10.

[0113] It should be noted that at least one side of the second JFET region 10 does not have the well contact region 500, so that the side of the second JFET region 10 that does not have the well contact region 500 can be adjacent to the second partial well region 301, and the side of the second partial well region 301 away from the second JFET region 10 is adjacent to the source region 400, that is, part of the second partial well region 301 can be adjacent to the second JFET region 10 and the source region 400 respectively to form the above-mentioned channel region 3011. Figure 9 As shown, the second JFET region 10 , the second partial well region 301 and the source region 400 are sequentially adjacent in the first direction C.

[0114] It is mentioned here that Figure 7 As shown, the second JFET region 10, the second partial well region 301 and the source region 400 are sequentially adjacent in the BB' direction; Figure 11 As shown, the second JFET region 10, the second partial well region 301 and the source region 400 are sequentially adjacent in the second direction D; Figure 13 As shown, the second JFET region 10, the second partial well region 301 and the source region 400 are sequentially adjacent in the third direction E. In summary, as Figures 7 to 14 Parts of the second partial well region 301 shown may be adjacent to the second JFET region 10 and the source region 400 , respectively, to form the aforementioned channel region 3011 .

[0115] Furthermore, if Figure 9 and Figure 10As shown, the second JFET region 10 has a third rectangular shape in a cross-section parallel to the first surface, and the third rectangle is located within the second rectangle. The first JFET region 20 surrounds the well region 300. The second JFET region 10 has a first end, a second end, and another portion of the second JFET region 10 located between the first and second ends in a first direction C parallel to the first surface. The source region 400 surrounds the second partial well region 301, and the first partial well region 302 surrounds the source region 400. The Schottky metal 602 covers the portion of the second JFET region 10 at the first end. In this case, the portion of the second JFET region 10 at the first end covered by the Schottky metal 602 can be considered the third Schottky region. The Schottky metal 602 also covers the portion of the second partial well region 301 that contacts the third Schottky region. The well contact region 500 is located in the second partial well region 301 and semi-surrounds the second JFET region 10 at the first end. It is understood that the portion of the second JFET region 10 located between the first and second ends is not covered by the Schottky metal. Furthermore, the portion of the second JFET region 10 located between the second JFET region 10 at the second end and the second partial well region 301 does not have the well contact region 500 , or the portion of the second JFET region 10 located between the second JFET region 10 at the second end and the source region 400 does not have the well contact region 500 .

[0116] For example, Figure 10 As shown, the ohmic contact metal 601 can be one, and the ohmic contact metal 601 is arranged around the periphery of part of the Schottky metal 602 (that is, the ohmic contact metal 601 is half-surrounded by the periphery of the Schottky metal 602), and the ohmic contact metal 601 covers part of the well contact region 500, part of the second partial well region 301 and part of the source region 400.

[0117] like Figure 10 As shown, a portion of the second JFET region 10 at the second end can be considered as a third embedded semiconductor region, and the second gate structure 30 in the gate structure 700 covers the third embedded semiconductor region. The second gate structure 30 also covers a portion of the second partial well region 301 surrounding the third embedded semiconductor region and a portion of the source region 400 surrounding the third embedded well region. The third embedded well region is the portion of the second partial well region 301 adjacent to the third embedded semiconductor region.

[0118] like Figure 9 and Figure 10As shown, the source region 400 includes a portion of the source region 400 surrounding the second JFET region 10 and close to the first partial well region 302, and a portion of the source region 400 surrounding the second JFET region 10 and close to the second partial well region 301. The first gate structure 40 in the gate structure 700 surrounds the second JFET region 10, and the second gate structure 30 is located on a side of the first gate structure 40 close to the second JFET region 10. The first gate structure 40 covers the portion of the source region 400 surrounding the second JFET region 10 and close to the first partial well region 302, the first partial well region 302, and the portion of the first JFET region 20 surrounding the outer periphery of the well region 300.

[0119] In some embodiments, when the polygon is a first hexagon or a first octagon, the number of the second JFET region 10 in each cell region may be one, such as Figures 11 to 14 As shown, the well contact region 500 may include a fourth partial well contact region (not labeled in the figure) and a fifth partial well contact region (not labeled in the figure) spaced apart from each other. The fourth partial well contact region and the fifth partial well contact region may be located on opposite sides of the second JFET region 10. When the well contact region 500 is adjacent to the source region 400 and portions of the second partial well region 301 are adjacent to the well contact region 500 and the second JFET region 10, portions of the second partial well region 301 may be located between the fourth partial well contact region (well contact region 500) and the second JFET region 10, and portions of the second partial well region 301 may be located between the fifth partial well contact region and the second JFET region 10. Alternatively, when the well contact region 500 is adjacent to the source region 400 and the second JFET region 10, the fourth partial well contact region may be located adjacent to the second JFET region 10 and the source region 400, respectively, and the fifth partial well contact region may be located adjacent to the second JFET region 10 and the source region 400, respectively. It can be understood that the fourth partial well contact region can be set adjacent to the first side of the second JFET region 10, and the fifth partial well contact region can be set adjacent to the second side of the second JFET region 10, and the first side and the second side are opposite sides of the second JFET region 10.

[0120] In some optional embodiments, such as Figure 11 and Figure 12 As shown, in the case where the polygon is a first hexagon, the second JFET region 10 has a first irregular pattern in a cross section parallel to the first surface, the first irregular pattern is located in the first hexagon, the first irregular pattern includes a second hexagon and two first preset patterns, the two first preset patterns are respectively in contact with two opposite sides of the second hexagon in the second direction D, and the second direction D is parallel to the first surface.

[0121] like Figure 11 and Figure 12As shown, the first JFET region 20 surrounds the well region 300, and the second JFET region 10 has a first portion, a second portion, and a third portion that are contact-arranged in the second direction D. The second portion is located between the first portion and the third portion. The second portion well region 301 is respectively contact-arranged with a side of the first portion away from the second portion and a side of the third portion away from the second portion. The first portion and the third portion correspond one-to-one to the two first preset patterns, and the second portion corresponds to the second hexagon.

[0122] like Figure 11 and Figure 12 As shown, the source region 400 surrounds the second partial well region 301 , and the first partial well region 302 surrounds the source region 400 .

[0123] like Figure 11 and Figure 12 As shown, the Schottky metal 602 covers at least a portion of the second portion. Figure 11 and Figure 12 As shown, the well contact region 500 includes a first partial doped region (not shown in the figure) and a second partial doped region (not shown in the figure). The first partial doped region and the second partial doped region are located on opposite sides of the second JFET region 10 in a direction perpendicular to the second direction D. Based on this, the source region 400, the second partial well region 301, and the first portion of the second JFET region 10 are sequentially adjacent in the second direction D; the source region 400, the second partial well region 301, and the third portion of the second JFET region 10 are sequentially adjacent in the second direction D; the source region 400, the first partial doped region, the second partial well region 301, and the second portion of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the second direction D; and the source region 400, the second partial doped region, the second partial well region 301, and the second portion of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the second direction D.

[0124] In some embodiments, the Schottky metal 602 may further cover a portion of the second partial well region 301 that is in contact with the second portion.

[0125] like Figure 12 As shown, the second gate structure 30 in the gate structure 700 may include a fifth sub-gate structure (not labeled in the figure) and a sixth sub-gate structure (not labeled in the figure) located on opposite sides of the Schottky metal 602 in the second direction D.

[0126] like Figure 11 and Figure 12As shown, the first portion of the second JFET region 10 includes a portion of the first portion proximate to the second partial well region 301 and distal to the second portion of the second JFET region 10, and a portion of the first portion proximate to the second portion of the second JFET region 10 and distal to the second partial well region 301. The portion of the first portion proximate to the second partial well region 301 and distal to the second portion of the second JFET region 10 can be considered a fourth embedded semiconductor region. The fifth sub-gate structure (not labeled in the figure) covers the fourth embedded semiconductor region. The fifth sub-gate structure also covers a portion of the second partial well region 301 that contacts the fourth embedded semiconductor region, as well as a portion of the source region 400 that contacts the fourth embedded well region. The fourth embedded well region is the portion of the second partial well region 301 located on the side of the first portion of the second JFET region 10 that is distal to the second portion.

[0127] like Figure 11 and Figure 12 As shown, the third portion of the second JFET region 10 includes a portion of the third portion proximate to the second partial well region 301 and distal to the second portion of the second JFET region 10, and a portion of the third portion proximate to the second portion of the second JFET region 10 and distal to the second partial well region 301. The portion of the third portion proximate to the second partial well region 301 and distal to the second portion of the second JFET region 10 can be considered a fifth embedded semiconductor region. The sixth sub-gate structure (not labeled in the figure) covers the fifth embedded semiconductor region. The sixth sub-gate structure also covers the portion of the second partial well region 301 that contacts the fifth embedded semiconductor region, as well as the portion of the source region that contacts the fifth embedded well region. The fifth embedded well region is the portion of the second partial well region 301 located on the side of the third portion distal to the second portion.

[0128] like Figure 11 and Figure 12 As shown, the source region 400 includes a partial source region surrounding the second JFET region 10 and close to the first partial well region 302 and a partial source region surrounding the second JFET region 10 and close to the second partial well region 301, the first gate structure 40 surrounds the second JFET region 10, the fifth sub-gate structure is located on the side of the first gate structure 40 close to the second JFET region 10, and the fifth sub-gate structure covers the partial source region 400, the second partial well region 301 and the partial first portion of the second JFET region 10 that are sequentially adjacent in the second direction D.

[0129] like Figure 11 and Figure 12 As shown, the sixth sub-gate structure is located on the other side of the first gate structure 40 close to the second JFET region 10, and the sixth sub-gate structure covers the partial source region 400, the second partial well region 301 and the partial third portion of the second JFET region 10 sequentially adjacent in the second direction D.

[0130] like Figure 11 and Figure 12 As shown, the first gate structure 40 covers a portion of the source region 400 surrounding the second JFET region 10 and close to the first partial well region 302 , the first partial well region 302 , and a portion of the first JFET region 20 surrounding the outer periphery of the well region 300 .

[0131] In some optional embodiments, such as Figure 13 and Figure 14 As shown, in the case where the polygon is a first octagon, the second JFET region 10 has a second irregular pattern in a cross section parallel to the first surface, the second irregular pattern is located in the first octagon, and the second irregular pattern includes a second octagon and two second preset patterns, the two second preset patterns are contacted and arranged on two opposite sides of the second octagon in a third direction E, and the third direction E is parallel to the first surface.

[0132] like Figure 13 and Figure 14 As shown, the first JFET region 20 surrounds the well region 300, and the second JFET region 10 has a fourth part, a fifth part and a sixth part that are contact-arranged in the third direction E. The fifth part is located between the fourth part and the sixth part, and the side of the fourth part away from the fifth part and the side of the sixth part away from the fifth part are respectively contacted with the second part of the well region 301. The fourth part and the sixth part respectively correspond one-to-one to the two second preset patterns, and the fifth part corresponds to the second octagon.

[0133] like Figure 13 and Figure 14 As shown, the source region 400 surrounds the second partial well region 301, and the first partial well region 302 surrounds the source region 400. The Schottky metal 602 covers the fifth portion.

[0134] like Figure 13 and Figure 14 As shown, the well contact region 500 includes a third partial doping region (not shown in the figure) and a fourth partial doping region (not shown in the figure). Specifically, the third partial doping region and the fourth partial doping region are located on opposite sides of the second JFET region 10 in a direction perpendicular to the third direction E. Based on this, the source region 400, the second partial well region 301, and the fourth portion of the second JFET region 10 are sequentially adjacent in the third direction E; the source region 400, the second partial well region 301, and the sixth portion of the second JFET region 10 are sequentially adjacent in the third direction E; the source region 400, the third partial doping region, the second partial well region 301, and the fourth portion of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the third direction E; and the source region 400, the fourth partial doping region, the second partial well region 301, and the sixth portion of the second JFET region 10 are sequentially adjacent in a direction perpendicular to the third direction E.

[0135] In some embodiments, the Schottky metal may further cover a portion of the second partial well region that is in contact with the fifth portion.

[0136] like Figure 14 As shown, the second gate structure 30 in the gate structure 700 includes a seventh sub-gate structure (not labeled in the figure) and an eighth sub-gate structure (not labeled in the figure) located on opposite sides of the Schottky metal 602 in the third direction E.

[0137] like Figure 13 and Figure 14 As shown, the fourth portion of the second JFET region 10 includes a portion of the fourth portion proximate to the second partial well region 301 and distal to the fifth portion of the second JFET region 10, and a portion of the fourth portion proximate to the fifth portion of the second JFET region 10 and distal to the second partial well region 301. The portion of the fourth portion proximate to the fifth portion of the second JFET region 10 and distal to the second partial well region 301 can be considered the sixth embedded semiconductor region. The seventh sub-gate structure (not labeled in the figure) covers the sixth embedded semiconductor region. The seventh sub-gate structure also covers the portion of the second partial well region 301 that contacts the sixth embedded semiconductor region and the portion of the source region 400 that contacts the sixth embedded well region. The sixth embedded well region is the portion of the second partial well region 301 located on the side of the fourth portion of the second JFET region 10 that is distal to the fifth portion.

[0138] like Figure 13 and Figure 14 As shown, the sixth portion of the second JFET region 10 includes a portion of the sixth portion adjacent to the second partial well region 301 and distal to the fifth portion of the second JFET region 10, and a portion of the sixth portion adjacent to the fifth portion of the second JFET region 10 and distal to the second partial well region 301. The portion of the sixth portion adjacent to the fifth portion of the second JFET region 10 and distal to the second partial well region 301 can be considered a seventh embedded semiconductor region. An eighth sub-gate structure (not labeled in the figure) covers the seventh embedded semiconductor region.

[0139] like Figure 13 and Figure 14 As shown, the eighth sub-gate structure also covers a portion of the second partial well region 301 in contact with the seventh embedded semiconductor region and a portion of the source region 400 in contact with the seventh embedded well region. The seventh embedded well region is a portion of the second partial well region 301 located on the side of the sixth portion of the second JFET region 10 away from the fifth portion.

[0140] like Figure 13 and Figure 14As shown, the source region 400 includes a portion of the source region 400 surrounding the second JFET region 10 and close to the first partial well region 302, and a portion of the source region 400 surrounding the second JFET region 10 and close to the second partial well region 301. The first gate structure 40 surrounds the second JFET region 10, and the seventh sub-gate structure is located on a side of the first gate structure 40 close to the second JFET region 10. The seventh sub-gate structure covers the source region 400, the second partial well region 301, and a portion of the fourth portion of the second JFET region 10 that are sequentially adjacent in the third direction E. Exemplarily, the seventh sub-gate structure covers a portion of the source region 400, a portion of the second partial well region 301, and a portion of the fourth portion of the second JFET region 10.

[0141] like Figure 13 and Figure 14 As shown, the eighth sub-gate structure is located on the other side of the first gate structure 40 close to the second JFET region 10, and the eighth sub-gate structure covers the source region 400, the second partial well region 301, and a portion of the sixth portion of the second JFET region 10 that are sequentially adjacent in the third direction E. Exemplarily, the eighth sub-gate structure covers a portion of the source region 400, a portion of the second partial well region 301, and a portion of the sixth portion of the second JFET region 10.

[0142] like Figure 13 and Figure 14 As shown, the first gate structure 40 covers a portion of the source region 400 surrounding the second JFET region 10 and close to the first partial well region 302 , the first partial well region 302 , and a portion of the first JFET region 20 surrounding the well region 300 .

[0143] For example, Figure 12 and Figure 14 As shown, in order to increase the channel density and ensure the current uniformity, there are two ohmic contact metals 601, and the two ohmic contact metals 601 are located on opposite sides of the Schottky metal 602 in a one-to-one correspondence. Figure 12 As shown, each ohmic contact metal 601 covers a portion of the well contact region 500, a portion of the second partial well region 301 and a portion of the source region 400; Figure 14 As shown, each ohmic contact metal 601 covers a portion of the well contact region 500 and a portion of the source region 400 .

[0144] In addition, according to another aspect of the present application, a method for preparing a MOSFET device is provided, comprising:

[0145] providing a substrate;

[0146] Sequentially forming an epitaxial layer on one side surface of the substrate;

[0147] forming a JFET doped region in the epitaxial layer, wherein a surface of the epitaxial layer away from the substrate is a first surface of the epitaxial layer;

[0148] Optionally, the step of forming the epitaxial layer includes: sequentially forming a first sub-epitaxial layer and a second sub-epitaxial layer on one side surface of the substrate through an epitaxial process;

[0149] Optionally, the step of forming the JFET doped region includes: epitaxially growing a third sub-epitaxial layer on a side of the second sub-epitaxial layer away from the first sub-epitaxial layer to form the JFET doped region.

[0150] Optionally, the step of forming the JFET doping region includes: performing ion implantation on a surface of the second sub-epitaxial layer away from the first sub-epitaxial layer to form a well contact region;

[0151] forming a well region in the epitaxial layer using an ion implantation process, so that the well region extends from the first surface into the epitaxial layer, the epitaxial layer including a first JFET region and a second JFET region, the well region surrounding the second JFET region, the first JFET region being located on at least one side of the well region away from the second JFET region, and the epitaxial layer and the well region having opposite conductivity types;

[0152] forming a source region in the well region using an ion implantation process, so that the source region extends from the first surface into the well region, the source region surrounds the second JFET region, a first partial well region is defined between the source region and the first JFET region, a second partial well region is defined between the source region and the second JFET region, and the well region includes the first partial well region and the second partial well region;

[0153] forming a well contact region in the well region by an ion implantation process, so that the well contact region extends from the first surface into the well region, and the well contact region semi-surrounds the second JFET region, and the well contact region and the well region have the same conductivity type;

[0154] Optionally, before the step of forming the well region by adopting the ion implantation process, the trench region is etched by an etching process, so that the well region, the source region and the well contact region are implanted and formed in the trench;

[0155] It should be noted that after the ion implantation process, a high temperature annealing process at a temperature greater than 1650° C. may be used to activate the implanted impurity ions.

[0156] forming a gate structure on the first surface, the gate structure comprising a gate oxide layer disposed in contact with the first surface, polysilicon located on a side of the gate oxide layer away from the first surface, and a dielectric layer covering the polysilicon;

[0157] forming an ohmic contact metal on the first surface, the ohmic contact metal covering a portion of the surface of the well contact region in the first surface, a portion of the surface of the second partial well region in the first surface, and a portion of the surface of the source region in the first surface;

[0158] forming a Schottky metal on the first surface to cover a portion of the surface of the second JFET region in the first surface;

[0159] forming a front metal layer on a side of the Schottky metal away from the epitaxial layer;

[0160] The substrate is thinned, and a back metal layer is formed on a surface (second surface) of the substrate facing away from the epitaxial layer.

[0161] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0162] The technical solution of the present invention is applied to a cellular structure of a MOSFET device, the cellular structure including a substrate, an epitaxial layer located on one side of the substrate, and a cellular region, the cellular region being located in the epitaxial layer, the cellular region including: a first JFET region and a second JFET region spaced apart, the first JFET region and the second JFET region both being located in the epitaxial layer; a well region located in the epitaxial layer and surrounding the second JFET region, the first JFET region being located on at least one side of the well region away from the second JFET region, the conductivity type of the well region being opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, a first portion of the well region being provided between the source region and the first JFET region, a second portion of the well region being provided between the source region and the second JFET region, the well region including a first portion of the well region being provided between the source region and the first JFET region, and a second portion of the well region being provided between the source region and the second JFET region. A portion of the well region and a second portion of the well region; a well contact region located in the portion of the second portion of the well region, and so that the second portion of the well region has a channel region adjacent to the source region and the second JFET region respectively, the well contact region and the well region have the same conductivity type, and the doping concentration of the well contact region is higher than the doping concentration of the well region; an ohmic contact metal covering at least a portion of the well contact region; a gate structure including a first gate structure and a second gate structure adjacent to each other, the first gate structure covering the first portion of the well region and the portion of the source region respectively adjacent to the first portion of the well region, and at least a portion of the first JFET region, the second gate structure covering a portion of the channel region and the portion of the source region and the portion of the second JFET region respectively adjacent to the portion of the channel region, and the gate structure and the ohmic contact metal are spaced apart. As can be seen, the present application integrates a Schottky diode into the MOSFET device. Since the turn-on voltage of the Schottky diode is lower than that of the traditional body diode, the turn-on time is greatly reduced. Therefore, the present application improves the problem of the high turn-on voltage of the traditional MOSFET, which is beneficial to the conduction of reverse current in the MOSFET. Moreover, since the conduction of the Schottky diode has unipolar conductivity, this will enable the MOSFET to avoid the bipolar degradation effect at low current density and before the PN junction begins to inject, while reducing reverse recovery current and reverse recovery loss. In addition, for the first partial well region located between the first JFET region and the source region and covered by the first gate structure, the first partial well region has a first conductive channel. On this basis, the present application also forms a second conductive channel in the second portion of the well region covered by the second gate structure between the second JFET region and the source region, and then integrates a hybrid PIN Schottky diode (MPS) in the well region of the MOSFET device, so that the channel width in the MOSFET device is increased without increasing the cell width in the MOSFET device and retaining the original first conductive channel in the MOSFET device. Therefore, during the forward conduction period of the MOSFET device, the current density under the well region and the Schottky contact region of the MOSFET device can be increased, so that the MOSFET device has good forward conduction characteristics.Based on this, the present application solves the technical problems of large reverse freewheeling turn-on voltage and high reverse recovery loss when the body diode of the existing MOSFET is used as a freewheeling path.

[0163] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A cell structure of a MOSFET device, characterized in that: The cellular structure includes a substrate, an epitaxial layer and a cellular region located on one side of the substrate, wherein the cellular region is located in the epitaxial layer, and the cellular region includes: a first JFET region and a second JFET region, wherein the first JFET region is located at least on both sides of the second JFET region; a well region, located between the first JFET region and the second JFET region, the well region having a conductivity type opposite to that of the epitaxial layer; a source region located in the well region and surrounding the second JFET region, the well region between the source region and the first JFET region being a first partial well region, and the well region between the source region and the second JFET region being a second partial well region; a well contact region located in a portion of the second partial well region, so that the remaining second partial well region has a channel region adjacent to the source region and the second JFET region, respectively; the well contact region and the well region have the same doping type, and the doping concentration of the well contact region is higher than the doping concentration of the well region; A gate structure includes a first gate structure and a second adjacent gate structure, wherein the first gate structure covers the first partial well region and the portion of the source region and at least the portion of the first JFET region respectively adjacent to the first partial well region, and the second gate structure covers the portion of the channel region and the portion of the source region and the portion of the second JFET region respectively adjacent to the portion of the channel region.

2. The cellular structure according to claim 1, characterized in that The well contact region is adjacent to the source region and part of the second partial well region is adjacent to the well contact region and the second JFET region respectively; or, The well contact region is adjacent to the source region and the second JFET region, respectively.

3. The cellular structure according to claim 2, characterized in that The cellular structure further includes: a Schottky metal covering a portion of the second JFET region; The ohmic contact metal at least covers a portion of the well contact area and is in contact with the ohmic contact metal; wherein, In the case where the well contact region is adjacent to the source region and part of the second partial well region is respectively adjacent to the well contact region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the second partial well region and part of the source region respectively adjacent to the well contact region. In the case where the well contact region is respectively adjacent to the source region and the second JFET region, the ohmic contact metal covers at least part of the well contact region and part of the source region adjacent to the well contact region.

4. The cellular structure according to claim 3, characterized in that The epitaxial layer has a first surface on a side facing away from the substrate, wherein the well contact region is adjacent to the source region and a portion of the second partial well region is adjacent to the well contact region and the second JFET region, respectively. The first surface corresponding to the second JFET region is a first region surface, the first region surface includes a first sub-region and a second sub-region adjacent to each other, and a side of the second sub-region away from the first sub-region is also adjacent to the first surface corresponding to the channel region; The first surface corresponding to the second partial well region is a second region surface, the second region surface includes adjacent third sub-region and fourth sub-region, the third sub-region is the first surface corresponding to the channel region, and the fourth sub-region is the second region surface excluding the third sub-region; The Schottky metal covers the first sub-region and a portion of the fourth sub-region.

5. The cellular structure according to claim 4, characterized in that The first surface corresponding to the first portion of the well region is a third regional surface, the first surface corresponding to the source region is a fourth regional surface, and at least a portion of the fourth regional surface is located between the second regional surface and the third regional surface; The portion of the surface of the first region covered by the second gate structure is a fifth sub-region, the portion of the surface of the fourth region covered by the second gate structure is a sixth sub-region, and the third sub-region is located between the fifth sub-region and the sixth sub-region; The first surface corresponding to the first JFET region is a fifth region surface, a portion of the fifth region surface covered by the first gate structure is a seventh subregion, and the third region surface is located between at least a portion of the fourth region surface and the seventh subregion.

6. The cellular structure according to claim 3, characterized in that The epitaxial layer has a first surface on a side facing away from the substrate, and the well region has a first preset pattern in a cross section parallel to the first surface, wherein the side lines of the first preset pattern are polygonal.

7. The cellular structure according to claim 6, characterized in that In the case where the polygon is a first rectangle, The second JFET region includes a first sub-JFET region and a second sub-JFET region, the second partial well region includes a portion located between the first sub-JFET region and the second sub-JFET region and another portion other than the portion, and the well contact region is provided in a portion of the second partial well region located between the first sub-JFET region and the second sub-JFET region; In a direction perpendicular to a line connecting the first sub-JFET region and the second sub-JFET region, the first partial well region includes a first sub-well region located on the left side of the line and a second sub-well region located on the right side of the line; The Schottky metal includes a first sub-Schottky metal and a second sub-Schottky metal arranged at intervals. When the first sub-JFET region includes a portion of the first sub-JFET region close to the second sub-JFET region, a portion of the first sub-JFET region away from the second sub-JFET region, and another portion of the first sub-JFET region located between the two portions of the first sub-JFET region, the portion of the first sub-JFET region close to the second sub-JFET region in the first sub-JFET region is a first Schottky region, and the first sub-Schottky metal at least covers the first Schottky region. When the second sub-JFET region includes a portion of the second sub-JFET region close to the first sub-JFET region, a portion of the second sub-JFET region away from the first sub-JFET region, and another portion of the second sub-JFET region located between the two portions of the first sub-JFET region, the portion of the second sub-JFET region close to the first sub-JFET region in the second sub-JFET region is a second Schottky region, and the second sub-Schottky metal at least covers the second Schottky region.

8. The cellular structure according to claim 7, characterized in that The second gate structure includes a first sub-gate structure and a second sub-gate structure, the first sub-gate structure is located on a side of the first sub-Schottky metal away from the second sub-Schottky metal, and the second sub-gate structure is located on a side of the second sub-Schottky metal away from the first sub-Schottky metal; A portion of the first sub-JFET region away from the second sub-JFET region is a first embedded semiconductor region, the first sub-gate structure covers the first embedded semiconductor region, a portion of the second partial well region surrounding the first embedded semiconductor region, and a portion of the source region surrounding the first embedded well region, and the first embedded well region is a portion of the second partial well region adjacent to the first embedded semiconductor region; The portion of the second sub-JFET region away from the first sub-JFET region is a second embedded semiconductor region, the second sub-gate structure covers the second embedded semiconductor region, the portion of the second partial well region surrounding the second embedded semiconductor region, and the portion of the source region surrounding the second embedded well region, and the second embedded well region is the portion of the second partial well region adjacent to the second embedded semiconductor region.

9. The cellular structure according to claim 8, characterized in that The first gate structure includes a third sub-gate structure and a fourth sub-gate structure, the third sub-gate structure is located on the left side, the fourth sub-gate structure is located on the right side, the third sub-gate structure is respectively arranged in contact with the first sub-gate structure and the second sub-gate structure, and the first sub-gate structure and the second sub-gate structure are also arranged in contact with the fourth sub-gate structure; The source region includes a portion of the source region on a side of the second partial well region away from the second JFET region and close to the first sub-well region, and a portion of the source region on a side of the second partial well region away from the second JFET region and close to the second sub-well region. The third sub-gate structure covers a portion of the source region on a side of the second partial well region away from the second JFET region and close to the first sub-well region. The third sub-gate structure also covers the first sub-well region and a portion of the first JFET region located on a side of the first sub-well region away from the first sub-JFET region and the second sub-JFET region. The fourth sub-gate structure covers a portion of the source region of the second partial well region away from the second JFET region and close to the second sub-well region. The fourth sub-gate structure also covers the second sub-well region and a portion of the first JFET region located on the side of the second sub-well region away from the first sub-JFET region and the second sub-JFET region.

10. The cellular structure according to claim 7, characterized in that: The epitaxial layer has a first surface on a side facing away from the substrate. The first surface has a trench. At least a portion of the well region extends from a portion of the surface of the trench into the epitaxial layer.

11. The cellular structure according to claim 10, characterized in that A contact surface between the second partial well region and the gate structure includes a {0-33-8} crystal plane.

12. The cellular structure according to claim 10, characterized in that The first surface corresponding to the trench includes a bottom surface and sidewalls, and a portion of the well region extends from a portion of the bottom surface of the trench into the epitaxial layer.

13. The cellular structure according to claim 10, characterized in that The first surface corresponding to the trench includes a bottom surface and sidewalls, and a portion of the well region extends from the entire bottom surface of the trench into the epitaxial layer.

14. The cellular structure according to claim 10, characterized in that The first surface corresponding to the trench includes a bottom surface and side walls, and a portion of the well region extends from the entire bottom surface and a portion of the side walls of the trench into the epitaxial layer.

15. The cellular structure according to claim 10, characterized in that The first surface corresponding to the groove includes a bottom surface and sidewalls, and the cellular structure further includes: A silicon oxide layer covers a portion of the sidewall of the trench where the second partial well region is located.

16. The cellular structure according to claim 6, characterized in that When the polygon is a second rectangle, the well contact region includes a first partial well contact region, a second partial well contact region, and a third partial well contact region that are adjacently arranged, and the first partial well contact region, the second partial well contact region, and the third partial well contact region are located on three sides of the second JFET region in a one-to-one correspondence; In a case where the well contact region is adjacent to the source region and portions of the second partial well region are adjacent to the well contact region and the second JFET region, portions of the second partial well region are adjacent to the first partial well contact region and the second JFET region, portions of the second partial well region are adjacent to the second partial well contact region and the second JFET region, and portions of the second partial well region are adjacent to the third partial well contact region and the second JFET region. In a case where the well contact region is adjacent to the source region and the second JFET region respectively, the second JFET region is disposed adjacent to the first partial well contact region, the second partial well contact region and the third partial well contact region respectively.

17. The cellular structure according to claim 16, characterized in that The second JFET region has a third rectangle in a cross section parallel to the first surface, the third rectangle being located in the second rectangle; The first JFET region surrounds the well region, and the second JFET region has a first end and a second end opposite to each other in a first direction, the first direction being parallel to the first surface; The source region surrounds the second partial well region, and the first partial well region surrounds the source region; The Schottky metal covers a portion of the second JFET region at the first end, and the Schottky metal also covers a portion of the second partial well region that contacts a third Schottky region, the third Schottky region being the portion of the second JFET region at the first end covered by the Schottky metal, and the well contact region is located in the second partial well region and semi-surrounds the second JFET region at the first end; The second gate structure covers a third embedded semiconductor region, a portion of the second partial well region surrounding the third embedded semiconductor region, and a portion of the source region surrounding the third embedded well region, the third embedded semiconductor region being a portion of the second JFET region at the second end, and the third embedded well region being a portion of the second partial well region adjacent to the third embedded semiconductor region; The source region includes a portion of the source region surrounding the second JFET region and close to the first partial well region, and a portion of the source region surrounding the second JFET region and close to the second partial well region. The first gate structure surrounds the second JFET region. The second gate structure is located on a side of the first gate structure close to the second JFET region. The first gate structure covers a portion of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region, and a portion of the first JFET region surrounding the outer periphery of the well region.

18. The cellular structure according to claim 6, characterized in that In the case where the polygon is a first hexagon or a first octagon, The well contact region includes a fourth partial well contact region and a fifth partial well contact region that are spaced apart from each other, and the fourth partial well contact region and the fifth partial well contact region are respectively located on two opposite sides of the second JFET region; In a case where the well contact region is adjacent to the source region and portions of the second partial well region are adjacent to the well contact region and the second JFET region respectively, portions of the second partial well region are located between the fourth partial well contact region and the second JFET region, and portions of the second partial well region are located between the fifth partial well contact region and the second JFET region; When the well contact region is adjacent to the source region and the second JFET region respectively, the fourth partial well contact region is adjacent to part of the source region and the second JFET region respectively, and the fifth partial well contact region is adjacent to part of the source region and the second JFET region respectively.

19. The cellular structure according to claim 18, characterized in that When the polygon is a first hexagon, the second JFET region has a first irregular pattern in a cross section parallel to the first surface, the first irregular pattern is located in the first hexagon, the first irregular pattern includes a second hexagon and two first preset patterns, the two first preset patterns are respectively arranged in contact with two opposite sides of the second hexagon in a second direction, and the second direction is parallel to the first surface; The first JFET region surrounds the well region, and the second JFET region has a first portion, a second portion, and a third portion that are arranged in contact with each other in the second direction. The second portion is located between the first portion and the third portion. The second portion of the well region is respectively arranged in contact with a side of the first portion away from the second portion and a side of the third portion away from the second portion. The first portion and the third portion correspond one-to-one to the two first preset patterns, and the second portion corresponds to the second hexagon. The source region surrounds the second partial well region, and the first partial well region surrounds the source region; The Schottky metal covers at least a portion of the second portion; The well contact region includes a first partial doped region and a second partial doped region, the first partial doped region and the second partial doped region are located on opposite sides of the second JFET region in a direction perpendicular to the second direction, the source region, the second partial well region and the first portion are sequentially adjacent in the second direction, the source region, the second partial well region and the third portion are sequentially adjacent in the second direction, the source region, the first partial doped region, the second partial well region and the second portion are sequentially adjacent in a direction perpendicular to the second direction, and the source region, the second partial doped region, the second partial well region and the second portion are sequentially adjacent in a direction perpendicular to the second direction.

20. The cellular structure according to claim 19, characterized in that The second gate structure includes a fifth sub-gate structure and a sixth sub-gate structure located on opposite sides of the Schottky metal in the second direction; The first portion includes a portion of the first portion close to the second partial well region and away from the second portion, and a portion of the first portion close to the second portion and away from the second partial well region. The fifth sub-gate structure covers a fourth embedded semiconductor region, a portion of the second partial well region in contact with the fourth embedded semiconductor region, and a portion of the source region in contact with the fourth embedded well region. The fourth embedded semiconductor region is a portion of the first portion close to the second partial well region and away from the second portion. The fourth embedded well region is a portion of the second partial well region located on a side of the first portion away from the second portion. The third portion includes a portion of the third portion close to the second partial well region and away from the second portion, and a portion of the third portion close to the second portion and away from the second partial well region. The sixth sub-gate structure covers the fifth embedded semiconductor region, a portion of the second partial well region in contact with the fifth embedded semiconductor region, and a portion of the source region in contact with the fifth embedded well region. The fifth embedded semiconductor region is a portion of the third portion close to the second partial well region and away from the second portion. The fifth embedded well region is a portion of the second partial well region located on a side of the third portion away from the second portion. The source region includes a portion of the source region surrounding the second JFET region and close to the first partial well region, and a portion of the source region surrounding the second JFET region and close to the second partial well region. The first gate structure surrounds the second JFET region. The fifth sub-gate structure is located on a side of the first gate structure close to the second JFET region, and the fifth sub-gate structure covers a portion of the source region, the second partial well region and a portion of the first portion that are sequentially adjacent in the second direction. The sixth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the sixth sub-gate structure covers a portion of the source region, the second partial well region and a portion of the third portion that are sequentially adjacent in the second direction. The first gate structure covers a portion of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region and a portion of the first JFET region surrounding the periphery of the well region.

21. The cellular structure according to claim 18, wherein: When the polygon is a first octagon, the second JFET region has a second irregular pattern in a cross section parallel to the first surface, the second irregular pattern is located in the first octagon, and the second irregular pattern includes a second octagon and two second preset patterns, the two second preset patterns are arranged in contact with each other at two opposite sides of the second octagon in a third direction, and the third direction is parallel to the first surface; The first JFET region surrounds the well region, and the second JFET region has a fourth portion, a fifth portion, and a sixth portion arranged in contact with each other in the third direction, the fifth portion is located between the fourth portion and the sixth portion, a side of the fourth portion away from the fifth portion and a side of the sixth portion away from the fifth portion are respectively arranged in contact with the second portion of the well region, the fourth portion and the sixth portion have a one-to-one correspondence with the two second preset patterns, and the fifth portion corresponds to the second octagon; The source region surrounds the second partial well region, and the first partial well region surrounds the source region; The Schottky metal covers the fifth portion; The well contact region includes a third partial doping region and a fourth partial doping region, the third partial doping region and the fourth partial doping region are located on opposite sides of the second JFET region in a direction perpendicular to the third direction, the source region, the second partial well region and the fourth portion are sequentially adjacent in the third direction, the source region, the second partial well region and the sixth portion are sequentially adjacent in the third direction, the source region, the third partial doping region, the second partial well region and the fourth portion are sequentially adjacent in a direction perpendicular to the third direction, and the source region, the fourth partial doping region, the second partial well region and the sixth portion are sequentially adjacent in a direction perpendicular to the third direction.

22. The cellular structure according to claim 21, characterized in that The second gate structure includes a seventh sub-gate structure and an eighth sub-gate structure located on opposite sides of the Schottky metal in the third direction; The fourth portion includes a portion of the fourth portion close to the second partial well region and away from the fifth portion, and a portion of the fourth portion close to the fifth portion and away from the second partial well region. The seventh sub-gate structure covers the sixth embedded semiconductor region, a portion of the second partial well region in contact with the sixth embedded semiconductor region, and a portion of the source region in contact with the sixth embedded well region. The sixth embedded semiconductor region is the portion of the fourth portion close to the second partial well region and away from the fifth portion. The sixth embedded well region is a portion of the second partial well region located on a side of the fourth portion away from the fifth portion. The sixth portion includes a portion of the sixth portion close to the second partial well region and away from the fifth portion, and a portion of the sixth portion close to the fifth portion and away from the second partial well region. The eighth sub-gate structure covers the seventh embedded semiconductor region, a portion of the second partial well region in contact with the seventh embedded semiconductor region, and a portion of the source region in contact with the seventh embedded well region. The seventh embedded semiconductor region is the portion of the sixth portion close to the second partial well region and away from the fifth portion. The seventh embedded well region is a portion of the second partial well region located on a side of the sixth portion away from the fifth portion. The source region includes a portion of the source region surrounding the second JFET region and close to the first partial well region, and a portion of the source region surrounding the second JFET region and close to the second partial well region. The first gate structure surrounds the second JFET region. The seventh sub-gate structure is located on a side of the first gate structure close to the second JFET region, and the seventh sub-gate structure covers the source region, the second partial well region and a portion of the fourth portion that are sequentially adjacent in the third direction. The eighth sub-gate structure is located on the other side of the first gate structure close to the second JFET region, and the eighth sub-gate structure covers the source region, the second partial well region and a portion of the sixth portion that are sequentially adjacent in the third direction. The first gate structure covers a portion of the source region surrounding the second JFET region and close to the first partial well region, the first partial well region and a portion of the first JFET region surrounding the well region.

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