Semiconductor device, semiconductor package and method of manufacturing same

Abstract

A semiconductor device includes a silicon substrate having a first side and a second side opposite each other, and further having a first region and a second region. The semiconductor device includes a first silicon lens formed in the first region and on a first side of the silicon substrate along a first surface of the silicon substrate. The semiconductor device includes a second silicon lens formed in the first region and on a second side of the silicon substrate along a second surface of the silicon substrate. The semiconductor device includes a photonic die disposed in the first region of the silicon substrate and on the second side. The embodiment of the invention also discloses a semiconductor package and a method for manufacturing the semiconductor package.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices, semiconductor packages, and methods of manufacturing the same. Background Art

[0002] Electrical signal transmission and processing is a technology for signal transmission and processing. In recent years, optical signal transmission and processing have been used in more and more applications, especially due to the use of fiber optic related applications for signal transmission.

[0003] Optical signal transmission and processing are usually combined with electrical signal transmission and processing to provide comprehensive applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission, as well as processing and control. Therefore, devices integrating optical components and electrical components are formed for the conversion between optical signals and electrical signals, and the processing of optical signals and electrical signals. Thus, a package can include an optical (photonic) die containing an optical device and an electronic die containing an electronic device. Summary of the Invention

[0004] According to one aspect of the embodiments of the present application, a semiconductor device is provided, including: a silicon substrate having a first side and a second side opposite to each other, and further having a first region and a second region; a first silicon lens formed in the first region and located on the first side of the silicon substrate along the first surface of the silicon substrate; a second silicon lens formed in the first region and located on the second side of the silicon substrate along the second surface of the silicon substrate; and a photonic die disposed in the first region of the silicon substrate and located on the second side.

[0005] According to another aspect of the embodiments of the present application, a semiconductor package is provided, including: a substrate disposed above a package substrate; a grating coupler disposed above the substrate; a plurality of first conductive components disposed above the grating coupler; an electronic die disposed above the plurality of first conductive components and including a plurality of second conductive components; a first silicon lens formed along the first surface of the silicon substrate; and a second silicon lens formed along the second surface of the silicon substrate, the second surface being opposite to the first surface; wherein, the electronic die is formed along the second surface of the silicon substrate.

[0006] According to yet another aspect of the embodiments of the present application, a method of manufacturing a semiconductor package is provided, including: forming a first silicon lens along the first surface on the first side of the silicon substrate and in the first region on the first side; forming a second silicon lens along the second surface on the opposite side of the silicon substrate and in the first region on the second side; forming an electronic die in the second region on the second side and laterally adjacent to the first region; and attaching a photonic die to the electronic die on the second side, wherein the photonic die includes a grating coupler vertically aligned with at least one of the first silicon lens or the second silicon lens. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] As will be best understood from the following detailed description, when read in conjunction with the accompanying drawings, aspects of the present invention will be best understood. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be increased or decreased arbitrarily.

[0008] Figure 1 A multi-chip system including a plurality of sites is shown in accordance with some embodiments.

[0009] Figure 2 An example arrangement of components of a site of a multi-chip system in accordance with some embodiments is shown. Figure 1 of a site of a multi-chip system in accordance with some embodiments

[0010] Figure 3 A cross-sectional view of a portion of a site in accordance with some embodiments is shown. Figure 1 of a site in accordance with some embodiments

[0011] Figure 4 A detailed cross-sectional view of a portion of a site shown in accordance with some embodiments is shown. Figure 3 of a portion of a site shown in accordance with some embodiments

[0012] Figure 5 A cross-sectional view of a silicon-based lens embedded in a portion of a site shown in accordance with some embodiments is shown. Figure 3 of a portion of a site shown in accordance with some embodiments

[0013] Figure 6 An example flow chart of a method for fabricating a portion of a site shown in accordance with some embodiments is shown. Figure 3 of a portion of a site shown in accordance with some embodiments

[0014] Figure 7 An example flow chart of a method for manufacturing a silicon-based lens shown in accordance with some embodiments is shown. Figure 5 of a silicon-based lens shown in accordance with some embodiments

[0015] Figures 8 - 20 Corresponding cross-sectional views of a portion of a semiconductor package during various manufacturing stages of a method of manufacturing in accordance with some embodiments are shown. Figures 6 - 7 by a method of manufacturing in accordance with some embodiments DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0017] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0018] The present disclosure provides various embodiments of a three-dimensional (3D) package including optical and electronic devices that may be electrically coupled to each other and methods of forming the same. In some embodiments, a system-on-integrated-chip (SoIC) may provide advantages including fine pitch (e.g., relatively high bond density), shorter wire delay for SoIC bonding, or hybrid laser microlens integration and fiber-to-photonic integrated circuit (PIC) assembly in the SoIC system, e.g., to reduce photon packaging resources. The SoIC structure may include or integrate a single system, such as a photonic or optical integrated circuit (IC), radio frequency integrated circuit (RFIC), power IC, analog IC, mixed-mode IC, etc. A grating coupler (GC) (e.g., having a peak wavelength of about 1310 nanometers (nm)) is provided or used to emit a beam that matches a single-mode fiber mode having a spot diameter of about 9.2 μm, although the spot diameter may include or be configured for other sizes greater than or less than 9.2 μm. In some cases, the grating may emit approximately 63% (e.g., 2 dB) of the input power in the upward and downward directions, respectively. The beam emitted in the downward direction may spread as it passes through a substrate (e.g., a silicon material or other type of substrate material).

[0019] In some configurations, a (e.g., micro) silicon lens can be placed or formed on the front side of the chip (or the front side of the substrate) to collimate the divergent beam from the optical GC. Such a silicon-based lens can serve as the optical input / output (I / O) of the optical device. For example, with configurable dimensions and profiles, the silicon-based lens can collimate the received light source and generate a focal point of the light source at the waveguide mode resonance component (e.g., GC) of the optical device. Thus, the optical device can significantly improve the coupling efficiency. Additionally, by adjusting the focal point at the grating coupler, the beam size of the light source can be optimized (e.g., minimized), which in turn can reduce the size of the grating coupler. Therefore, the area occupied by the optical device can be reduced, which can advantageously free up more area to integrate more high-performance (e.g., electrical) devices in the package. In some cases, a collimated beam from an external source with the correct diameter can be emitted or launched onto the lens and focused to a spot (e.g., a spot with a spot diameter of about 9.2 μm) on the GC.

[0020] However, in a single-lens configuration, the GC may not be placed or positioned at the focal point of the lens for beam collimation. In the case where the GC is not located at the focal point of the lens (or where no lens is provided in or on the substrate), the coupling efficiency may be reduced, or a relatively large beam size may be generated. Additionally, the radius of curvature of the lens may not be easily controlled. For example, if the lens is circular, the process variations may be greater than those for planar wiring. According to various embodiments, a package as disclosed herein embeds or otherwise includes a dual-silicon-based (e.g., silicon, silicon nitride) lens optically coupled to the optical device. The dual-silicon lens can be formed on different (opposite) sides of the substrate to improve process variations (including variations in the radius of curvature from having a single silicon-based lens), e.g., for light refraction to accommodate or reduce the light incident angle error using the dual-silicon lens. For example, a package of the technical solutions discussed herein can include a first silicon lens formed along a first surface on a first side of a (e.g., silicon) substrate, and a second silicon lens formed along a second surface on a second side of the substrate, thereby forming a dual lens on different sides of the substrate. By combining or forming the dual-silicon lens, the directivity and coupler efficiency of the SoIC structure can be improved, and the fiber loss can be reduced while maintaining the beam size.

[0021] Figure 1 A multi-chip system 100 is shown in accordance with various embodiments. The multi-chip system 100 is, for example, a high-performance computing (HPC) system and includes a plurality of sites 102, each of which can be a separate computing system. Each site 102 can be formed as (e.g., three-dimensional (3D)) semiconductor packages, e.g., formed on a common package substrate. Although Figure 1 the system 100 shown in has twenty sites 102, it should be understood that the system 100 can include any number of sites 102 while still being within the scope of the present disclosure.

[0022] Site 102 is interconnected by optical path 104, which allows the individual computing systems at site 102 to communicate with each other. For example, optical path 104 can be a closed loop (or ring) that connects to each site 102 of multi-chip system 100. Thus, each site 102 can communicate with any other site 102 via optical path 104. In an embodiment, optical path 104 includes a plurality of waveguides, each waveguide connecting two sites 102 in a point-to-point manner. In some embodiments, optical path 104 is a silicon photonics interconnect, but other types of optical paths can also be used.

[0023] Referring Figure 2 , an example layout or other arrangement of components (e.g., dies, devices, etc.) in each site 102 according to various embodiments is shown. As a Figure 2 non-limiting example shown in, each site 102 can include a processor die 106, a memory die 108, an electronics die (an implementation of an electronic device) 110, and a photonics die (an implementation of an optical device) 112. Optical path 104 extends under (or above according to the arrangement) one or more components of each site 102, but at least extends under the photonics die 112 of each site 102. Sites 102 are interconnected by circuit paths ( Figure 1 or Figure 2 not shown in, but will be described below).

[0024] Processor die 106 can be a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), etc. Memory die 108 can be volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. In the illustrated embodiment, each site 102 includes one processor die 106 and four memory dies 108, but it should be understood that each site 102 can include more or fewer memory dies 108 or more processor dies 106.

[0025] Photonics die 112 can transmit, receive, convert, modulate, demodulate, or otherwise process optical signals. For example, photonics die 112 can convert an electrical signal from processor die 106 into an optical signal and convert the optical signal back into an electrical signal. Photonics die 112 can communicate via optical path 104 ( Figure 1) Communicate such optical signals with one or more other photonic die. According to various embodiments of the present disclosure, the photonic die 112 may receive an optical signal from a silicon-based lens embedded at a corresponding site 102 and transmit and / or receive the optical signal through one or more waveguides of the optical path 104. As will be discussed in further detail below, the silicon-based lens may be optically coupled to the optical path 104 by edge coupling or grating coupling (e.g., through a grating coupler). Such optical signals received through the silicon-based lens may include test signals and / or carrier (e.g., laser) signals configured to test the corresponding photonic die 112, optical path 104, etc. Thus, the photonic die 112 is responsible for the input / output (I / O) of optical signals to the optical path 104. In some embodiments, the optical path 104 or at least a portion thereof may be integrated into the photonic die 112.

[0026] In various embodiments, the photonic die 112 may be a photonic integrated circuit (PIC), and the electronic die 110 (e.g., sometimes referred to as an electrical die) includes the electronic circuitry required to interface the processor die 106 with the photonic die 112. For example, the electronic die 110 may include a controller, a transimpedance amplifier, etc. The electronic die 110 controls the high-frequency signals of the photonic die 112 based on electrical signals (digital or analog) received from the processor die 106. The electronic die 110 may be an electronic integrated circuit (EIC). Although in Figure 2 the non-limiting example the processor die 106, memory die 108, and electronic die 110 are shown as separate dies, it should be understood that the sites 102 may each be a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device / package. Thus, the processing, memory, and / or electronic control functions may be integrated on the same die or the same substrate.

[0027] Figure 3 A cross-sectional view of a portion of one of the sites 102 according to various embodiments is shown. For example, Figure 3 the portion of the site 102 shown in includes an electronic die 110 attached to or otherwise stacked on the optical die 112, and the two stacked dies are disposed on a package substrate 302. Figure 3 The cross-sectional view of the site 102 in is simplified to a schematic diagram, and further details of the site 102 will be shown and discussed in Figure 4 In addition, it should be understood that above the package substrate 302, the site 102 may include any one of various other dies attached thereto, such as one or more memory dies 108, one or more processor dies 106, etc., while still being within the scope of the present disclosure.

[0028] The electronic die 110 is formed over a substrate 304. The substrate 304 can be a semiconductor substrate, such as a bulk semiconductor, etc., which can be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 304 can be a wafer, such as a silicon wafer. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 304 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In one embodiment, the substrate 304 is a silicon wafer, such as a 12-inch silicon wafer. In some embodiments, depending on the configuration, the thickness of the substrate 304 can be from about 300 micrometers (μm) to about 1000 μm or greater than 1000 μm, but is not limited thereto.

[0029] In some embodiments, the substrate 304 can be referred to as having a front side or surface 305A (e.g., sometimes referred to as the second side (or the first side, depending on the arrangement)) and a back side or surface 305B (e.g., sometimes referred to as the first side (or the second side, depending on the arrangement)), as shown. Generally, the electronic die 110 includes a plurality of device components or structures (e.g., transistors) formed along the front surface 305A, and a plurality of conductive components (sometimes referred to as front-side interconnect structures) formed on these device structures on the front side 305A. However, it should be understood that the electronic die 110 can include many other conductive components (sometimes referred to as back-side interconnect structures) formed on the back side 305B while still being within the scope of the present disclosure.

[0030] In addition, the substrate 304 has a plurality of lateral zones or regions, including but not limited to a first region 304B and a second region 304A. In some arrangements, the first region and the second region may be interchanged. In some embodiments, the electronic die 110 may be formed in the second region 304A, while a silicon-based lens 306a (e.g., sometimes referred to as a first silicon lens) is formed in the first region 304B and on the back side 305B of the substrate 304. Specifically, the silicon-based lens 306a may be aligned (e.g., vertically) with a light source / supplier 310 that provides photon energy (e.g., light) 311 to the photon die 112, and a dielectric layer 308 (e.g., silicon oxide, silicon nitride, a combination thereof, etc.) is inserted between the silicon-based lens 306a and the photon die 112. For example, the light source / supplier 310 may include an optical fiber that transmits photon energy. The thickness of the dielectric layer 308 may be formed to be but not limited to from about 0 μm to about 50 μm, or greater than 8 μm, depending on the configuration. After forming the silicon-based lens 306a, a second silicon-based lens 306b is formed on the front side 305A of the substrate 304. In some embodiments, one or both of the silicon-based lenses 306a, 306b may sometimes be referred to as the silicon-based lens 306. The silicon-based lens 306a may be aligned (e.g., vertically) with the silicon-based lens 306b. In some cases, the silicon-based lens 306a may be offset (or laterally displaced) (e.g., vertically) from the silicon-based lens 306b by a predetermined (or configurable) distance, such as but not limited to in the range of from about 0 μm to about 100 μm.

[0031] As a result, there is an optical transmission path extending from the light source / supplier 310 to the silicon-based lens 306. As shown below Figure 4 This optical transmission path has no conductive (e.g., metal) components, thus substantially limiting interference from conductive components. The size and profile (e.g., radius of curvature, thickness, diameter, angle, etc.) of the silicon-based lens 306 (e.g., the silicon-based lens 306a and / or the silicon-based lens 306b) may be configured according to the characteristics of the light source 311 (e.g., wavelength range). The silicon-based lens 306b may be composed of a material similar to that of the silicon-based lens 308a. The silicon-based lens 306b may be formed in a manner similar to that of the silicon-based lens 306a or using similar techniques (e.g., at least one suitable etching technique), such as in combination with but not limited to Figures 5 - 20 as described in at least one of the foregoing. Thus, when the silicon-based lens 306a receives the overlying light source 311, the silicon-based lens 306a may collimate the light source 311 at the focal point at approximately the position of the light source / supplier 310 through the substrate 304, the silicon-based lens 306b, and the dielectric layer 308. For example, using the silicon-based lens 306a and the silicon-based lens 306b can improve the change in the radius of curvature compared to using a single silicon-based lens.

[0032] In various configurations, the silicon-based lens 306 can be composed of at least one suitable material, such as silicon or silicon nitride, etc. The silicon-based lens 306 can be made of a material similar to or different from the substrate 304. In some cases, the silicon-based lens 306 can be formed by using at least one suitable etching technique on the substrate 304. For example, the silicon-based lens 306a can be formed by etching (e.g., directly) various parts of the back side 305B of the substrate 304. The silicon-based lens 306b can be formed by etching various parts of the front side 305A of the substrate 304. The process of forming the silicon-based lens 306 can be described in combination with but not limited to Figures 5 - 20 For example. In some other cases, the silicon-based lens 306 can be formed by using at least one deposition technique. For example, the silicon-based lens 306a can be formed by depositing a material (such as silicon) on the surface of the back side 305B of the substrate 304. The silicon-based lens 306b can be formed by depositing a material (such as silicon) on the surface of the front side 305A of the substrate 304.

[0033] The size of at least one of the silicon-based lenses 306 can be configured or constructed to compensate for potential offsets (or displacements) of an optical fiber (such as an optical fiber or a light source). For example, the diameter of at least one of the silicon-based lenses 306 can be between about 10 μm and about 500 μm, but not limited to this. For example, the maximum diameter of at least one of the silicon-based lenses 306 can be configured to be more than 100 μm. The thickness (e.g., height) of at least one of the silicon-based lenses 306 can be between about 1 μm and about 50 μm, but not limited to this, where the maximum thickness of the silicon-based lens 306 can be, for example, more than 5 μm. At least one of the first curvature radius (R1) of the silicon-based lens 306a or the second curvature radius (R2) of the silicon-based lens 306b can be between about 100 μm and about 500 μm, but not limited to this. At least one of the first curvature radius of the silicon-based lens 306a or the second curvature radius of the silicon-based lens 306b can be greater than but not limited to 290 μm. One or more configurations (such as diameter, thickness, or curvature radius) of the silicon-based lens 306a can be similar to or different from those of the silicon-based lens 306b. For example, the diameter of the silicon-based lens 306a can be similar to or different from the diameter of the silicon-based lens 306b. The thickness (or height) of the silicon-based lens 306a can be similar to or different from the thickness of the silicon-based lens 306b. The curvature radius of the silicon-based lens 306a can be similar to or different from the curvature radius of the silicon-based lens 306b.

[0034] In some cases, the silicon-based lens 306a can be aligned (e.g., vertically) with the silicon-based lens 306b. In some other cases, the silicon-based lens 306a can be offset (e.g., vertically) from the silicon-based lens 306b by a distance (d). For example, the (e.g., vertical) offset distance between the silicon-based lens 306a and the silicon-based lens 306b can be between about 0 μm and about 100 μm, or between about 0 μm and about -100 μm. Depending on the position of at least one of the silicon-based lenses 306, the fiber optic angle can be configured to be, but not limited to, between 5° and 15°. The fiber optic angle can be described or illustrated in conjunction with, but not limited to Figure 3 such that the angle is the orientation or positioning of the fiber optic (e.g., the fiber optic associated with the light source / supplier 310) relative to the silicon-based lens 306a of the site 102, the surface of the substrate 304, or other components. The features of at least one of the silicon-based lenses 306 can be described in conjunction with, but not limited to at least Figure 5 to describe.

[0035] The site 102 also includes a plurality of (first) conductive connectors 312 and a plurality of (second) conductive connectors 314. The first conductive connectors 312 can electrically and / or physically couple various die (e.g., stacked electronic die 110 and optical die 112) to the package substrate 302, and the second conductive connectors 314 can electrically and / or physically couple the package substrate 302 to one or more other devices / packages. For example, the package substrate 302 can be coupled to at least the photon die 112 via one or more first conductive connectors 312. The package substrate 302 can be coupled to one or more other devices / packages via one or more second conductive connectors 314.

[0036] Next, referring to Figure 4 , the electronic die 110 disposed on the second region 304A and the second side 305A of the substrate 304 includes a plurality of device components 402 formed along the front surface of the substrate 304. The device components can be partially or completely covered by a dielectric layer 404. Above the dielectric layer 404 (when flipping Figure 2 the site 102), a plurality of conductive components 406 are formed in the dielectric layer 408. The dielectric layers 404 and 408 can be formed of the same material or different materials respectively selected from the group consisting of silicon oxide, silicon nitride, low-k dielectric materials, and combinations thereof. The conductive components 406 can include lines and vias and can be formed by a damascene process, such as dual damascene, single damascene, etc. The conductive components 406 can be disposed in multiple layers or levels, sometimes referred to as metallization layers. Generally, the metallization layers closest to and farthest from the device components 402 can be referred to as M0 (the bottommost metallization layer) and Mx (the topmost metallization layer), respectively. Above Mx, a plurality of pads (not shown) can be formed to electrically connect the conductive components 406 therein to the conductive components of the photon die 112.

[0037] The photonic die 112 can be formed on a semiconductor-on-insulator (SOI) substrate that includes a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on the semiconductor material, typically a silicon or glass substrate. As Figure 4 shown, layers 412 and 414 can represent such underlying semiconductor material and BOX layer, respectively.

[0038] In addition, the photonic die 112 can include a plurality of device components 416 (such as photodiodes) and a plurality of waveguides 418 (not shown) formed in an overlying semiconductor material. The front side (or surface) of such overlying semiconductor material is patterned to form the waveguides 418. Patterning the overlying semiconductor material can be achieved by acceptable lithography and etching techniques. Specifically, openings are etched in the overlying semiconductor material, and the remaining portion of the overlying semiconductor material can form the waveguides 418. The BOX layer 414 can be used as an etch stop layer for the etching process.

[0039] The waveguides 418 can be disposed on the front surface 305A (e.g., the second side) of the substrate 304. The waveguides 418 can include one or more grating couplers 420 formed on top of the waveguides 418. The grating couplers 420 can allow the waveguides 418 to transmit light to or receive light from an overlying light source or optical signal source (e.g., through the silicon-based lenses 306a and 306b). The grating couplers 420 can be formed by acceptable lithography and etching techniques. In an embodiment, the grating couplers 420 are formed after defining the waveguides 418. The grating couplers 420 can be composed of a silicon-based material. For example, the dimensions of the grating couplers 420 can include but are not limited to a thickness greater than 200 nm, ranging from about 100 nm to 1000 nm. For example, a photoresist can be formed and developed on the front side of the overlying semiconductor material (e.g., on the waveguides 418 and in the recesses defining them). The photoresist can be patterned to have openings corresponding to the grating couplers 420. The patterned photoresist can be used as an etch mask to perform one or more etching processes. Specifically, the front side of the overlying semiconductor material can be etched to form recesses in the waveguides 418, thereby defining the grating couplers 420. The etching process can be anisotropic wet etching or dry etching.

[0040] The photonic die 112 further includes a dielectric layer 422 formed over the device component 416 and the waveguide 418. The dielectric layer 422 may also be formed in the recesses that define the waveguide 418 and the grating coupler 420. The dielectric layer 422 may be formed of silicon oxide, silicon nitride, a combination thereof, etc., and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric process, etc. or a combination thereof. After formation, the dielectric layer 422 may be planarized, for example, by chemical mechanical polishing (CMP) or mechanical grinding, to prevent the pattern of the waveguide 418 from being transferred to the dielectric layer 424. In an embodiment, the dielectric layer 422 is an oxide, such as silicon oxide. Due to the different refractive indices of the materials of the waveguide 418 and the dielectric layer 422, the waveguide 418 has high internal reflection, such that light is confined in the waveguide 418, depending on the wavelength of the light and the reflectivity of the corresponding materials. In an embodiment, the refractive index of the material of the waveguide 418 is higher than the refractive index of the material of the dielectric layer 422.

[0041] Above the dielectric layer 422 (as Figure 2 shown), a plurality of conductive components 424 are formed in the dielectric layer 426. The dielectric layers 422 and 426 may be formed of the same material or different materials respectively selected from the group consisting of silicon oxide, silicon nitride, low-k dielectric materials, and combinations thereof. The refractive index of the material of the waveguide 418 is higher than the refractive index of the material of the dielectric layer 426. The conductive components 424 may include lines and vias, and may be formed by a damascene process, such as dual damascene, single damascene, etc. The conductive components 424 may be disposed in multiple layers or levels, sometimes referred to as metallization layers. Generally, the metallization layers closest to and farthest from the device component 416 may be referred to as M0 (the bottommost metallization layer) and Mx (the topmost metallization layer), respectively. Above Mx, a plurality of pads (not shown) may be formed to electrically connect the conductive components 424 therein to the conductive components 406 of the electronic die 110, i.e., the electronic die 100 is bonded or otherwise attached to the photonic die 112.

[0042] In some embodiments, the bonding between the electronic die 110 and the photonic die 112 may not include any bump structures, i.e., no bumps. However, in some other embodiments, the bonding between the electronic die 110 and the photonic die 112 may be established through a plurality of bump structures. For example, the bonding may be a hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (such as microbumps), etc.

[0043] As a non-limiting example, the electronic die 110 is bonded to the photonic die 112 by hybrid bonding. In such an embodiment, covalent bonds are formed using an oxide layer, such as the dielectric layer 408 of the electronic die 110 and the dielectric layer 426 of the photonic die 112. Prior to performing the bonding, the surface of the electronic die 110 can be treated. Next, a pre-bonding process can be performed, in which the respective pads or conductive components of the electronic die 110 and the photonic die 112 are aligned. The electronic die 110 and the photonic die 112 are pressed together to form a weak bond. After the pre-bonding process, the electronic die 110 and the photonic die 112 are annealed to strengthen the weak bond. During annealing, the OH bonds at the top of the dielectric layer are broken, and Si-O-Si bonds are formed between the electronic die 110 and the photonic die 112, thereby strengthening the bond.

[0044] As Figure 4 shown, there is an optical transmission path extending from the grating coupler 420 of the photonic die 112 to the silicon-based lens 306, including the silicon-based lens 306b (e.g., the second silicon lens) and the silicon-based lens 306a (e.g., the first silicon lens). In this case, the silicon-based lens 306b can be located between the silicon-based lens 308a and the grating coupler 420. In other arrangements, the silicon-based lens 306a can be located between the silicon-based lens 306b and the grating coupler 420. In various embodiments, such an optical transmission path does not have any conductive components 406 or conductive components 424. In other words, along this optical transmission path, there are no components formed of conductive materials, which can substantially limit the interference caused by the conductive components.

[0045] The photonic die 112 also includes a plurality of vias 428 extending through the dielectric layer 422, the BOX layer 414, and the underlying semiconductor material 412. The vias 428 can be formed by filling a plurality of openings extending through the dielectric layer 422, the BOX layer 414, and the underlying semiconductor material 412 with a conductive material. The conductive material is formed in the openings using, for example, electroless plating (ECP) or electroplating. The conductive material can be a metallic material including a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof. A planarization process, such as CMP or mechanical polishing, can be performed to remove the excess conductive material along the surface of the underlying semiconductor material 412 (e.g., the back side). In various embodiments, the vias 428 can electrically couple the conductive components 424 of the photonic die 112 to the conductive connector 312, and the conductive components 424 are electrically coupled to the conductive components 406 of the electronic die 110.

[0046] On the back side surface of the underlying semiconductor material 412, the site 102 also includes conductive pads 430, and some of the conductive pads 430 can be in electrical contact with the vias 428. The conductive pads 430 can be aluminum pads or aluminum-copper pads, but other metal pads can also be used.

[0047] A passivation film 432 can be formed on the back surface of the underlying semiconductor material 412, covering the conductive pad 430. The passivation film 432 can be formed of a dielectric material, such as silicon oxide, silicon nitride, etc., or a combination thereof. An opening is formed through the passivation film 432 to expose a (e.g., central) portion of the conductive pad 430.

[0048] Under bump metallization (UBM) 434 can be formed on the conductive pad 430 and the passivation film 432. The UBM 434 can be formed by forming a blanket conductive layer (e.g., by electroplating) on the passivation film 432 and in the opening. The conductive layer can be formed of copper, copper alloy, silver, gold, aluminum, nickel, etc., and combinations thereof. The conductive layer can be patterned to form the UBM 434.

[0049] A conductive connector 312 is formed on the UBM 434, e.g., disposed on the first side of the photonic die 112 opposite the second side facing the substrate 304. The conductive connector 312 can be a ball grid array (BGA) connector, solder ball, metal post, controlled collapse chip connection (C4) bump, microbump, bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 312 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 312 is formed by initially forming a solder layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 312 is a metal post (e.g., a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal post can be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on the conductive connector 312. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and can be formed by an electroplating process.

[0050] In some embodiments, the site 102 further includes one or more anti-reflection coatings (ACR) 450 formed on at least one of the front surface 305A or the back surface 305B of the substrate 304. The ARC layer 450 can be formed on the silicon-based lens 306a. In some cases, the ARC layer 450 can be formed under (or above, depending on the configuration) the silicon-based lens 306b. The ARC layer 450 can be implemented as a multi-layer anti-reflection material, such as silicon, silicon nitride, silicon oxide, titanium, titanium nitride, aluminum, aluminum oxide, silicon oxynitride, combinations of these materials, etc. For example, the ARC layer 450 can include a first silicon oxide (e.g., having a thickness of about 1000 angstroms ) and a first silicon nitride (e.g., having a thickness of about ), a second silicon oxide (e.g., having a thickness of about ), and a second silicon nitride (e.g., having a thickness of about ). In such an embodiment, the ARC layer 450 (or each of its antireflective materials) can be formed using a deposition process such as CVD, PVD, etc. However, any suitable materials and forming methods can be used.

[0051] Figure 5 An enlarged view of a silicon-based lens 306 (e.g., at least silicon-based lens 306a or silicon-based lens 306b) according to various embodiments is shown. Although Figure 5 the silicon-based lens 306a is provided for exemplary purposes, one or more features of the silicon-based lens 306a can be similarly described for the silicon-based lens 306b, such as the size, radius of curvature, thickness, etc. of the silicon-based lens. As Figure 5 the example of shows, the silicon-based lens 306a (or silicon-based lens 306b) has a hemispherical profile, or sometimes referred to as a plano-convex profile, where one spherical surface protrudes from the dorsal surface 305B and one flat surface is substantially aligned with the dorsal surface 305B. However, it should be understood that the silicon-based lens 306a or silicon-based lens 306b can have any of various other profiles, such as a biconvex profile, a positive meniscus profile, a positive achromatic profile, etc., as long as the silicon-based lens 306a and the silicon-based lens 306b can produce a focal point at the grating coupler 420 ( Figure 4 ), it is still within the scope of the present disclosure. As the silicon-based lens 306a and the silicon-based lens 306b are formed, these two silicon lenses can jointly provide a focal point at the grating coupler 420.

[0052] In addition, various dimensions of the silicon-based lens 306a (or silicon-based lens 306b) can be configured to collimate the light source 311 and focus it at the grating coupler 420. For example, the thickness "e" of the silicon-based lens 306a is defined as the maximum height from the plane to the spherical surface, the angle "θ" is defined as the angle between the tangent at one end of the spherical surface and the end of the plane, the radius of curvature of the spherical surface is "R", and the diameter of the silicon-based lens 306a is "d". As a non-limiting example, the thickness (e) can be in the range of about 1 μm to about 50 μm, the angle (θ) (e.g., the fiber angle) can be in the range of about 5° to about 15°, the radius (R) can be in the range of about 100 μm to about 500 μm, and the diameter (d) can be in the range of about 10 μm to about 500 μm. In some embodiments, the diameter (d) can be formed to be at least 100 μm to compensate for the offset of the light source (e.g., the optical fiber). In some embodiments, the angle (θ) can be formed within the above range to optimize the coupling efficiency of the silicon-based lens 306a. In some embodiments, the radius (R) can be formed to be about or greater than 290 μm, also for optimizing the coupling efficiency of the silicon-based lens 306a. In some embodiments, the radius (R) can be in the range of about 100 μm to about 500 μm.

[0053] Figure 6 FIG. 4 shows a flowchart of an example method 600 for forming at least a portion of a semiconductor package according to some embodiments. It should be noted that method 600 is merely an example and is not intended to limit the present disclosure. Thus, it can be understood that Figure 6 the order of operations of method 600 can be changed, additional operations can be provided before, during, and after Figure 6 method 600, and some other operations may only be briefly described herein.

[0054] Such a semiconductor package fabricated by method 600 can at least include an electronic die and a photonic die that are operatively and physically coupled to each other, and further includes a silicon-based lens operatively (e.g., optically) coupled to the photonic die. For example, as described above, the semiconductor package can include a portion of site 102. Thus, the operations of method 600 will be discussed in conjunction with the components Figures 3 - 5 to be discussed.

[0055] Method 600 begins at operation 602, which is to form a first silicon lens (e.g., 306a) on a first surface along a first side (e.g., 305B, sometimes referred to as the first side surface) of a substrate (e.g., 304). For example, the silicon-based lens 306a is formed on the backside surface (e.g., 305B) of the substrate 304. In addition, the silicon-based lens 306a is formed in a first region (e.g., 304B) of the substrate 304. In some embodiments, the silicon-based lens 306a is formed with a plano-convex profile through some lithography and etching processes, which will be described in Figure 7is discussed in further detail in

[0056] Method 600 proceeds to operation 604, which is to form a second silicon lens (e.g., 306b) along a second surface on a second side (e.g., 305A, sometimes referred to as the second lateral surface) of a substrate (e.g., 304). For example, the silicon-based lens 306b is formed on the front-side surface (e.g., 305A) of the substrate 304. The front-side surface is the side of the substrate 304 opposite to the back-side surface. Additionally, the silicon-based lens 306b is formed in a first region (e.g., 304B) of the substrate 304. In some embodiments, the silicon-based lens 306b is formed with a plano-convex profile through some lithography and etching processes, which will be discussed in further detail in Figure 7 e.g., similar to the silicon-based lens 306a.

[0057] Method 600 proceeds to operation 606, which is to form an electronic die on a second surface (side) (e.g., 305A) of the substrate (e.g., 304). The electronic die can be formed in a second region (e.g., 304A) of the substrate, where the second region is laterally adjacent to the first region of the substrate. For example, an electronic die (e.g., 110) including a plurality of electronic device components (e.g., 402) and conductive components (e.g., 406) can be formed on the front-side surface (e.g., 305A) of the substrate (e.g., 304). Additionally, the electronic die 110 can be formed in a second region (e.g., 304A) of the substrate 304, where the second region is not configured to form the silicon-based lens 306. In some embodiments, the first region of the substrate can be referred to as part of the electronic die 110.

[0058] Method 600 proceeds to operation 608, which is to attach a photonic die to the electronic die (e.g., 305A) on the second side of the substrate. For example, before, simultaneously with, or after forming the electronic die 110 (and the silicon-based lens 306) on the substrate 304, a photonic die (e.g., 112) is formed on the front-side surface (e.g., 305A) of the substrate (e.g., an SOI including underlying semiconductor material 412, BOX 414, and overlying semiconductor material). In some embodiments, the photonic die 112 includes a plurality of optical device components (e.g., 416), a plurality of waveguides (e.g., 418) having at least one grating coupler (e.g., 420), and a plurality of conductive components (e.g., 424). The grating coupler (e.g., 420) can be vertically aligned with at least one of the silicon-based lenses (e.g., 306a or 306b), such as in combination with but not limited to Figures 3 - 4 at least one of those described in

[0059] Continuing with the same example, when forming the photonic die 112 and the electronic die 110, these two dies can be attached to each other through various bonding techniques, such as hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (such as micro-bumps), etc. In some embodiments, the electronic die 110 can be bonded to the photonic die 112, where the conductive component 406 (of the electronic die 100) faces the conductive component 424 (of the photonic die 102). In other words, the electronic die 110 can be bonded to the photonic die 112 such that their respective front-side surfaces face each other, so that the silicon-based lens 306a is disposed on the back (opposite) surface (such as 305B) of the substrate 304 forming the electronic die 100, and the silicon-based lens 306b is disposed on the front (same) surface (such as 305A) of the substrate 304 forming the electronic die 110.

[0060] In some embodiments, the electronic die and the photonic die can be attached to a package substrate. For example, after bonding the photonic die 112 and the electronic die 110 to each other, such bonded dies can be attached to a package substrate (such as 302). In some embodiments, the bonded photonic die 112 and electronic die 110 can be attached to the package substrate 302 through a plurality of bump structures (such as 312). Additionally, the bump structures 312 can be formed on the front (opposite) surface of the substrate forming the photonic die 112.

[0061] As described above, operation 602 (or operation 604) includes a plurality of process steps / operations for forming the silicon-based lens (such as 306a or 306b). Figure 7 A flowchart including such an operation is shown. In some embodiments, the operations of method 700 can be associated with a cross-sectional view of a portion of an example semiconductor package 800 at various manufacturing stages, including an embedded silicon-based lens, as shown respectively Figures 8 - 20 as

[0062] Briefly, method 700 starts with operation 702 of forming a first mask on the first (back) surface / side of a silicon substrate. Method 700 then proceeds to operation 704 of etching the substrate (from the back side) using the first mask. Method 700 proceeds to operation 706 of laterally shrinking the mask (such as the first mask) to form a second mask. Method 700 continues to operation 708 of etching the silicon substrate (from the back side) using the shrunk mask. In various embodiments, at least one of operations 706 and 708 can be repeated a certain number of times until a desired stepped profile is formed on the back side of the first substrate. After forming the stepped profile, method 700 proceeds to operation 710 of rounding the stepped profile to form a silicon-based lens.

[0063] Corresponding to Figure 7 operation 702, Figure 88 is a cross-sectional view and a top view of a semiconductor package 800 according to various embodiments, wherein the back side (eg, back side 305B) of the substrate 304 is covered by a (eg, hard) mask 802 (eg, a first mask in this stage / operation). It should be noted that Figure 8 The substrate 304 of (and the following figures) is shown as being inverted, so that the mask 802 is formed on top of the substrate 304, such as along a first surface or first side of the silicon substrate. In addition, for example, based on the method 600, one or more electronic dies (to form a silicon-based lens) can be formed before or after performing the method 700.

[0064] The mask 802 may include or be composed of silicon nitride, photoresist, or other materials. The mask 802 may be formed into an elliptical, circular, and other suitable shapes for etching the silicon substrate 304. In some embodiments, the mask 802 may be formed into a single structure (e.g., one portion). In some other embodiments, the mask 802 may include multiple portions (not shown) covering different portions along the corresponding surface of the substrate 304. The mask 802 may be formed or positioned on the corresponding surface (side) at or around the first region (e.g., 304B) of the silicon substrate. The silicon-based lens 306a may be referred to as the first silicon lens, and the silicon-based lens 306b may be referred to as the second silicon lens. The corresponding surface of the substrate 304 depends on whether the operation or process is used to form the first silicon lens or the second silicon lens. For example, the mask 802 may be formed on the first side 305B of the silicon substrate to form the first silicon lens, and formed on the second side 305A of the silicon substrate to form the second silicon lens.

[0065] After forming the mask 802, corresponding to Figure 7 Operation 704, Figure 8 A first etching process 804 is shown performed on a surface (e.g., a back surface side or a front surface side) of a substrate 304 using a mask 802 according to various embodiments. The first etching process 804 may be a wet etching process (based on an etchant such as NH4OH, HNO3, or a combination thereof) or a dry etching process (based on an etchant such as NF3, F2, Cl2, or a combination thereof). The amount of the substrate 304 etched by the etching process 804 may be controlled by the length of time (or duration) of the etching process 804. Based on the pattern of the mask 802, the surface may present a donut shape (when viewed from the top), wherein the donut appears as a recessed portion relative to the remaining portion covered by the mask 802. Specifically, the remaining portion and the recess may form a step, for example Figure 8 805 shown in .

[0066] Corresponds to Figure 7 Operation 706, Figure 9800 according to various embodiments, wherein a mask 802 (e.g., a first mask) is reduced, e.g., to form a second mask having a smaller diameter than the first mask. At least one suitable etching technique, such as but not limited to plasma ashing, may be used to reduce (e.g., remove a portion of) the mask 802 without reducing other structures of the semiconductor package 800. The etching technique may be used to uniformly recess or reduce the mask 802. As shown, with Figure 8 Compared with mask 802, Figure 9 The mask 802 includes a relatively small diameter (e.g., before the mask 802 is laterally reduced). For example, the mask 802 is laterally reduced (e.g., in diameter) to expose a further exposed portion (e.g., portion 900) of the surface of the substrate 304. For example, the surface portion exposed due to the lateral reduction of the mask 802 can form a donut shape.

[0067] Corresponds to Figure 7 Operation 708, Figure 10 800 according to various embodiments, wherein a second etching process 806 is performed on the surface of the substrate 304 using a (e.g., reduced) mask 802. The second etching process 806 may be a wet etching process (based on an etchant such as NH4OH, HNO3, or a combination thereof) or a dry etching process (based on an etchant such as NF3, F2, Cl2, or a combination thereof). The second etching process 806 may be similar to the first etching process 804. In various implementations, operation 708 may be similar to Figure 7 The amount of substrate 304 etched by etching process 806 may be controlled by the length of time of etching process 806, for example. Figure 10 As shown, based on the pattern of the (e.g., laterally reduced) mask 802, the surface (e.g., the back surface side for forming the first silicon lens) can present another donut shape (when viewed from the top), wherein the donut appears as a recessed portion relative to the remaining portion covered by the mask 802. Specifically, the remaining portion and the recessed portion can form another step, such as 807, wherein step 805 is disposed below and around step 807, as shown in FIG. Figure 10 shown.

[0068] By repeating operations 706 and 708 once, another step 809 may be formed on a corresponding surface (eg, the back surface side of the first silicon lens or the front surface side of the second silicon lens) through another etching process 808 using a further reduced mask 802, which is respectively Figure 11 and Figure 12 Similarly, step 809 is formed to be disposed above and surrounded by the previous steps (eg, 807 and 805).

[0069] After repeating operations 706 and 708 one or more times, a corresponding number of steps can be found on the respective surfaces of the substrate 304, i.e., a stepped profile can be formed. For example, by using another etching process 810 with a further reduced mask 802, another step 811 can be formed on the respective surface (e.g., the back surface side of the first silicon lens or the front surface side of the second silicon lens), as Figure 13 and Figure 14 shown in the cross-sectional view and top view. Similarly, step 811 is formed to be above and surrounded by the steps in front (e.g., 809, 807, and 805).

[0070] Figure 15 A cross-sectional view of the semiconductor package 800 is shown, where the mask 802 has been removed after forming the desired stepped profile. In some embodiments, the hard mask can be removed by a phosphoric acid solution at a high temperature (e.g., about 170 °C), plasma ashing, wet cleaning, or other suitable techniques to remove the remaining mask 802. In some embodiments, the etching process performed on the substrate (e.g., 304) can define or determine at least one or both of the thickness (e.g., depth or height) or diameter of the first and second silicon lenses. For example, a relatively large number of etching processes (e.g., resulting in more steps) may cause the silicon lenses to be relatively thicker or wider, which may depend on the duration of the respective etching processes or the configuration of the mask 802.

[0071] Corresponding to Figure 7 operation 710, Figure 16 is a cross-sectional view and top view of the semiconductor package 800 according to various embodiments, where an etching process 812 is performed to round the steps of the stepped profile. The etching process 812 can be a wet etching process. In some embodiments, the etching process 812 can include applying at least one of an ammonia solution or a nitric acid solution on the respective surface to round the stepped profile. For example, the etching process 812 can etch the protruding portions of the stepped profile faster than the steps (e.g., 805, 807, 809, or 811). Thus, these protruding portions can be rounded (or smoothed) to form a spherical surface protruding from the respective surface, thereby forming a silicon-based lens (e.g., 306a or 306b) with a plano-convex profile.

[0072] Corresponding to Figure 6 operation 604, can be repeated or iterated Figure 7The operations of method 700 are used to form another silicon lens along the other (opposite) surface side of the silicon substrate. For example, after forming one of the silicon lenses, the silicon substrate (e.g., fixed to a carrier substrate during manufacturing) can be flipped to expose the other surface side of the silicon substrate. After flipping the silicon substrate, the operations of method 700 can be performed to form another silicon lens. The first silicon lens (e.g., 306a) can be formed before or after the second silicon lens (such as 306b). Although the operations of method 700, such as the operations corresponding to Figures 8 - 16 are used to form the first silicon lens (e.g., 306a), in some cases, the operations of method 700 are used to similarly form the second silicon lens (such as 306b). In this case, the second silicon lens can be formed on the front side or the second side (e.g., 305A) of the substrate 304, and the first silicon lens can be formed on the back side or the first side (e.g., 305B) of the substrate 304.

[0073] As Figure 17 shown, corresponding to operations 602 and 604 of Figure 6 , the first silicon lens (e.g., 306a) and the second silicon lens (e.g., 306b) can be formed along the corresponding surfaces (e.g., 304B) on the corresponding sides of the silicon substrate in the first region. For example, the silicon-based lens 306a can be formed along the first surface on the first side 305B of the substrate 304. The silicon-based lens 306b can be formed along the second surface on the second side 305A of the substrate 304. The first side 305B of the substrate 304 is opposite to the second side 305A. The silicon-based lenses 306 (e.g., 306a and 306b) are formed in the first region 304B. The silicon-based lenses 306 can be formed as double convex lenses, for example.

[0074] Corresponding to operation 606, Figure 18 is a cross-sectional view of a semiconductor package 800 according to various embodiments, in which an electronic die and a dielectric layer are formed. For example, after forming the first silicon lens (e.g., 306a) and the second silicon lens (e.g., 306b), an electronic die can be formed in the second region (e.g., 304A) of the silicon substrate. The second region is laterally adjacent to the first region (e.g., 304B) of the silicon substrate where the first and second silicon lenses are formed. For example, an electronic die (e.g., 110) including a plurality of electronic device components (e.g., 402) and conductive components (e.g., 406) can be formed on the front side surface (e.g., 305A) of the substrate (e.g., 304). In addition, the electronic die 110 can be formed in the second region (e.g., 304A) of the substrate 304 that is not configured to form the silicon-based lens 306.

[0075] After forming the electronic die, a dielectric layer (e.g., 308) can be formed, disposed, or deposited along the front side (e.g., 305A) of the silicon substrate and the surface of the electronic die (e.g., 110). As Figure 18As shown, for example, a dielectric layer (such as 308) can be formed or deposited along the surface (such as the second surface) of the silicon substrate and the front side (such as the second side) of the electronic die. The deposited dielectric layer can include a predetermined (e.g., configured) thickness. For example, the thickness of the dielectric layer can include but is not limited to being greater than 8 μm, with a range greater than 0 μm to 50 μm. In some cases, at least one suitable etching technique can be used to remove a portion of the dielectric layer or make it thinner (such as 308).

[0076] Corresponding to operation 608, Figure 19 is a cross-sectional view of a semiconductor package 800 according to various embodiments, in which a photonic die is formed. As shown, the photonic die (e.g., 112) is formed on the front side surface (e.g., 305A) of a substrate (e.g., an SOI including underlying semiconductor material 412, BOX 414, and overlying semiconductor material), or along the front side surface of a dielectric layer (e.g., 308). The front side surface of the dielectric layer is opposite to the back side surface of the dielectric layer (such as 304) facing the substrate. For example, as described herein, the photonic die 112 includes a plurality of optical device components (such as 416), a plurality of waveguides (such as 418) having at least one grating coupler (such as 420), and a plurality of conductive components (such as 424). The grating coupler (such as 420) can be vertically aligned with at least one of the silicon-based lenses (such as 306a or 306b), for example, in combination with but not limited to Figures 3 - 4 at least one of those described. The conductive component (such as 424) can be disposed above the grating coupler (such as 420), but not in the light transmission path.

[0077] The photonic die 112 can be attached to the electronic die 110. The two dies can be attached by various bonding techniques, such as hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (such as microbumps), etc. In some embodiments, for example, using the conductive component, the electronic die 110 can be bonded to the photonic die 112.

[0078] Subsequently, Figure 20FIG. 800 is a cross-sectional view of a semiconductor package according to various embodiments, in which one or more conductive connectors (e.g., 312) are formed. For example, the conductive connector 312 may be formed on the front surface of a substrate (e.g., 304) on which a photonic die 112 is formed. As shown, one or more conductive connectors 312 are formed on a first side of the photonic die 112 (e.g., facing away from the substrate 304), which is opposite to a second side of the photonic die 112 facing the substrate 304. In some embodiments, the conductive connector 312 may be formed by initially forming a solder layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed structurally, reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 312 may be a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solderless and have substantially vertical sidewalls.

[0079] The conductive connector 312 may facilitate or provide a connection between the photonic die 112 and the package substrate (e.g., 302). For example, after the conductive connector 312 is formed, the semiconductor package 800 may be flipped and attached to the package substrate (e.g., 302), as shown in conjunction with but not limited to Figures 3 - 4 at least one of. By flipping the semiconductor package 800 at this stage, for example, as shown in Figures 3 - 4 , the back side (e.g., 305B) of the silicon substrate may face up, and the front side of the silicon substrate (e.g., 305A) may face down. Other structures may be formed, connected, or implemented in combination with the semiconductor package 800, not limited to those described herein.

[0080] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a silicon substrate having a first side and a second side opposite to each other, and also having a first region and a second region. The semiconductor device includes a first silicon lens formed in the first region and located on the first side of the silicon substrate along a first surface of the silicon substrate. The semiconductor device includes a second silicon lens formed in the first region and located on the second side of the silicon substrate along a second surface of the silicon substrate. The semiconductor device includes a photonic die disposed in the first region of the silicon substrate and located on the second side.

[0081] In some embodiments, the semiconductor device further includes a waveguide disposed on the second side of the silicon substrate and having a grating coupler.

[0082] In some embodiments, the grating coupler is configured to allow the waveguide to receive light passing through both the first silicon lens and the second silicon lens.

[0083] In some embodiments, the first silicon lens and the second silicon lens are configured to jointly provide a focal point at the grating coupler.

[0084] In some embodiments, the semiconductor device further includes an electronic die, and the electronic die is disposed in the second region of the silicon substrate and on the second side.

[0085] In some embodiments, the photonic die includes a plurality of conductive components.

[0086] In some embodiments, the optical transmission path of the grating coupler extending from the first silicon lens through the second silicon lens to the photonic die does not have a plurality of conductive components.

[0087] In some embodiments, the semiconductor device further includes a plurality of conductive connectors, and the plurality of conductive connectors are disposed on the first side of the photonic die, and the first side of the photonic die is opposite to the second side facing the silicon substrate.

[0088] In some embodiments, the semiconductor device further includes a package substrate, and the package substrate is coupled to the photonic die via at least a plurality of conductive connectors.

[0089] In some embodiments, the first silicon lens has a first radius of curvature, the second silicon lens has a second radius of curvature, and the first radius of curvature is the same as the second radius of curvature.

[0090] In some embodiments, the first silicon lens has a first radius of curvature, the second silicon lens has a second radius of curvature, and the first radius of curvature is different from the second radius of curvature.

[0091] In some embodiments, the first silicon lens has a first thickness, the second silicon lens has a second thickness, and the first thickness is equal to the second thickness.

[0092] In some embodiments, the first silicon lens has a first thickness, the second silicon lens has a second thickness, and the first thickness is different from the second thickness.

[0093] In another aspect of the present disclosure, a semiconductor package is disclosed. The semiconductor package includes a substrate disposed above the package substrate. The semiconductor package includes a grating coupler disposed above the substrate. The semiconductor package includes a plurality of first conductive components disposed above the grating coupler. The semiconductor package includes an electronic die disposed above the plurality of first conductive components and including a plurality of second conductive components. The semiconductor package includes a first silicon lens formed along a first surface of the silicon substrate. The semiconductor package includes a second silicon lens formed along a second surface of the silicon substrate, and the second surface is opposite to the first surface. The electronic die is formed along the second surface of the silicon substrate.

[0094] In some embodiments, at least one of the first silicon lens or the second silicon lens is vertically aligned with the grating coupler.

[0095] In some embodiments, the first silicon lens and the second silicon lens are laterally offset from each other by a distance, and the distance is between about 0 micrometers (μm) and about 100 μm.

[0096] In some embodiments, the first silicon lens and the second silicon lens are configured to jointly provide a focal point at the grating coupler.

[0097] In some embodiments, both the first silicon lens and the second silicon lens have a hemispherical profile.

[0098] In another aspect of the present disclosure, a method for manufacturing a semiconductor package is disclosed. The method includes forming a first silicon lens along a first surface on a first side of a silicon substrate and in a first region on the first side. The method includes forming a second silicon lens along a second surface on a second side opposite to the first side of the silicon substrate and in a first region on the second side. The method includes forming an electronic die in a second region on the second side and laterally adjacent to the first region. The method includes attaching a photon die to the electronic die on the second side, wherein the photon die includes a grating coupler that is vertically aligned with at least one of the first silicon lens or the second silicon lens.

[0099] In some embodiments, each of the step of forming the first silicon lens and the step of forming the second silicon lens further includes: (a) forming a mask above the corresponding surface of the silicon substrate; (b) etching the silicon substrate using the mask; (c) laterally reducing the mask; (d) etching the silicon substrate using the reduced mask; (e) repeating steps (c) and (d) to form a stepped profile; and (f) rounding the stepped profile.

[0100] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0101] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A silicon substrate having a first side and a second side opposite to each other, and further having a first region and a second region; A first silicon lens formed in the first region and located on the first side of the silicon substrate along the first surface of the silicon substrate; A second silicon lens formed in the first region and located on the second side of the silicon substrate along the second surface of the silicon substrate; And A photonic die disposed in the first region of the silicon substrate and located on the second side.

2. The semiconductor device according to claim 1, further comprising a waveguide disposed on the second side of the silicon substrate and having a grating coupler.

3. The semiconductor device according to claim 2, wherein, The grating coupler is configured to allow the waveguide to receive light passing through both the first silicon lens and the second silicon lens.

4. The semiconductor device according to claim 2, wherein, The first silicon lens and the second silicon lens are configured to jointly provide a focal point at the grating coupler.

5. The semiconductor device according to claim 1, further comprising an electronic die disposed in the second region of the silicon substrate and located on the second side.

6. The semiconductor device according to claim 1, further comprising a plurality of conductive connectors disposed on a first side of the photonic die, the first side of the photonic die being opposite to the second side of the photonic die facing the silicon substrate.

7. A semiconductor package, comprising: A substrate disposed above a package substrate; A grating coupler disposed above the substrate; A plurality of first conductive components disposed above the grating coupler; An electronic die disposed above the plurality of first conductive components and including a plurality of second conductive components; A first silicon lens formed along a first surface of a silicon substrate; And A second silicon lens formed along a second surface of the silicon substrate opposite to the first surface; Wherein, the electronic die is formed along the second surface of the silicon substrate.

8. The semiconductor package according to claim 7, wherein, At least one of the first silicon lens or the second silicon lens is vertically aligned with the grating coupler.

9. A method of manufacturing a semiconductor package, comprising: Forming a first silicon lens along a first surface on a first side of a silicon substrate and in a first region located on the first side; Forming a second silicon lens along a second surface on a second side opposite to the first side of the silicon substrate and in the first region located on the second side; Forming an electronic die located on the second side and in a second region laterally adjacent to the first region; And Attaching a photonic die to the electronic die on the second side, wherein the photonic die includes a grating coupler vertically aligned with at least one of the first silicon lens or the second silicon lens.

10. The method according to claim 9, wherein, Each of the step of forming the first silicon lens and the step of forming the second silicon lens further includes: (a) Form a mask above the corresponding surface of the silicon substrate; (b) Etch the silicon substrate using the mask; (c) Laterally reduce the mask; (d) Etch the silicon substrate using the reduced mask; (e) Repeat steps (c) and (d) to form a stepped profile; and (f) Round the stepped profile.

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