Low-power-consumption high-performance memristor and preparation method and application thereof
By introducing TiN interpolation into the memristor, the interface characteristics between the electrode and the dielectric layer are optimized, and the problems of low Ion/off ratio and high power consumption of existing memristors are solved, and a high performance and low power consumption memristor is realized, suitable for high-density storage and neuromorphic computing.
Patent Information
- Application Number
- CN202510421922.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-22
AI Technical Summary
Existing memristors have problems such as low Ion/off ratio, interface instability and high power consumption, which limit their application.
The TiN interpolation is introduced to optimize the interface characteristics between the electrode and the dielectric layer, and by regulating the degree of interface oxidation, reducing interface defects, and optimizing the formation and fracture behavior of conductive filaments.
It improves the switching ratio of the memristor and reduces the operating voltage of the device, and reduces power consumption by more than 50%. It is suitable for high-density nonvolatile memory devices and neuromorphic calculations.
Smart Images
Figure CN120358929A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a TiN interlayer-based memristor and a preparation method thereof, aiming to improve the on / off ratio (I on / off ) of the memristor and reduce the operating voltage of the device, and is applicable to high-density non-volatile memory devices and neuromorphic computing applications. Background Art
[0002] As a new type of non-volatile memory, the memristor has advantages such as high density, fast read / write, and easy integration, and is regarded as a key technology to break through the bottleneck of the traditional von Neumann architecture. However, existing memristors face many problems, such as a low I on / off ratio, unstable interfaces, and high power consumption, which still limit their applications.
[0003] Currently, the main optimization methods for memristors include:
[0004] (1) Adjusting the electrode material to improve the charge injection characteristics, but this may lead to interfacial reactions or uncontrollable diffusion of oxygen vacancies, affecting the device stability;
[0005] (2) Optimizing the dielectric layer thickness to control the switching behavior, but too thick increases the resistance, and too thin leads to an increase in leakage current;
[0006] (3) Doping regulation to optimize the formation of conductive filaments, but it is difficult to accurately control the doping concentration. Excessive doping may cause device degradation, and too little doping may lead to difficulty in forming conductive filaments and poor device performance;
[0007] (4) High-voltage pretreatment (forming), although it can induce a stable conduction path, it is easy to cause dielectric damage, shorten the device life, and increase the energy consumption.
[0008] These methods have improved the performance of memristors to a certain extent, but generally have problems such as still high power consumption, insufficient device consistency, complex processes, or poor long-term stability. Summary of the Invention
[0009] In view of the deficiencies in the existing memristor technology, the present invention provides a low-power and high-performance memristor. The memristor optimizes the interfacial characteristics of the electrode and the dielectric layer by introducing a TiN interlayer, thereby improving the on / off ratio of the memristor and reducing the operating voltage of the device. At the same time, a preparation method of the memristor is provided.
[0010] The low-power and high-performance memristor of the present invention adopts the following technical solutions.
[0011] The memristor includes a substrate, a bottom electrode, a dielectric layer, and a top electrode. An interlayer is provided between the bottom electrode and the dielectric layer, and the interlayer material is TiN.
[0012] The bottom electrode material is Cu, Mo or W.
[0013] The dielectric layer material is Al2O3, HfO2, ZrO2 or a composite layer thereof.
[0014] The top electrode material is Cu, Mo or W.
[0015] The thickness of the bottom electrode is 50 nm, the thickness of the dielectric layer is 10 nm, and the thickness of the top electrode is 50 nm.
[0016] The thickness of the interlayer is 0.5 nm - 10 nm, preferably 8.8 nm.
[0017] When the bottom electrode material is Mo, the top electrode material is Cu, the dielectric layer material is HfO2, and the interlayer material is TiN with a thickness of 8.8 nm, the performance of the device is optimal, and the on / off ratio (I on / off ) is improved.
[0018] The introduction of the TiN interlayer can effectively improve the interfacial characteristics between the electrode and the dielectric layer, reduce interfacial defects, and improve the conductivity and stability of the device. With the increase of the TiN interlayer thickness, the interfacial oxidation degree can be effectively regulated, the on / off ratio of the device can be improved, and the operating voltage of the device can be reduced. The device can achieve stable switching operation at a low operating voltage of ±1 V to ±3 V. Compared with the structure without an interlayer, its power consumption is reduced by more than 50%. Based on the above low operating voltage (±1 V - ±3 V) and high on / off ratio characteristics, the TiN interlayer memristor of the present invention can be further integrated with a CMOS-compatible transistor to form a high-density 1TnR (1 transistor - n memristor) memory array (as shown in the supplement Figure 1 ). This architecture not only improves the selectivity of the memory cell but also enables ultra-high density storage through three-dimensional stacking technology (supplement Figure 2 ), and is suitable for next-generation non-volatile memories and neuromorphic computing applications.
[0019] The preparation method of the above memristor includes the following steps:
[0020] (1) Cleaning the substrate;
[0021] (2) Depositing a bottom electrode on the substrate;
[0022] (3) Depositing a TiN interlayer on the bottom electrode;
[0023] (4) Depositing a dielectric layer on the TiN interlayer;
[0024] (5) Coating a photoresist on the dielectric layer, exposing and developing to pattern the top electrode;
[0025] (6) Preparing a top electrode on the dielectric layer with the top electrode patterned;
[0026] (7) Remove the photoresist.
[0027] The process of cleaning the substrate in step (1) is to clean the substrate with acetone and anhydrous ethanol in sequence and blow dry with nitrogen; then soak and rinse with deionized water and blow dry with nitrogen.
[0028] The step (2) is to prepare the bottom electrode on the substrate using an electron beam process.
[0029] The step (3) is to deposit an intercalation layer on the bottom electrode using a magnetron sputtering process.
[0030] The step (4) is to prepare a dielectric layer on the intercalation layer using an atomic layer deposition process.
[0031] The preparation process of the top electrode in step (6) includes but is not limited to magnetron sputtering, electron beam sputtering, vacuum thermal evaporation, etc.
[0032] In the step (7), the photoresist is removed by soaking in acetone and anhydrous ethanol in sequence, and then rinsing and drying with deionized water.
[0033] Finally, the fabricated device can be electrically tested using a probe station (Cascade Summit 12000) and a parameter analyzer (Keysight B1500A) to measure IV characteristics and I on / off Compare.
[0034] One use of the memristor of the present invention is to form a three-dimensionally scalable non-volatile memory array, using an array architecture of 1 transistor and n low-power, high-performance memristors, vertically integrating the low-power, high-performance memristors with the transistors to form a three-dimensionally scalable non-volatile memory array.
[0035] Another use of the memristor of the present invention is to form a three-dimensional stacked storage array with ultra-high storage density. The 3D stacked structure is constructed by a multi-layer interconnection process, and the low-power high-performance memristor and the selection transistor are integrated in the vertical direction to form a three-dimensional cross-point storage array with ultra-high storage density.
[0036] The present invention optimizes the interface characteristics between the electrode and the dielectric layer by introducing a TiN intercalation layer, regulates the degree of interface oxidation, reduces interface defects, and optimizes the formation and fracture behavior of conductive filaments, thereby improving the storage performance of the memristor. It has the following characteristics:
[0037] 1. Improvement I on / off The intercalation material optimizes the charge transfer path and enhances the formation of conductive filaments, thereby improving the storage performance of the device;
[0038] 2. By reducing power consumption and optimizing the properties of the intercalation material, the operating voltage and power consumption of the device are effectively reduced, promoting the realization of low-power applications.
[0039] Generally speaking, the intercalation treatment significantly improves the overall performance of the memristor by optimizing the interface and material combination, especially in terms of storage density and power consumption control. Description of the Drawings
[0040] Figure 1 It is a schematic structural diagram of the low-power and high-performance memristor of the present invention.
[0041] Figure 2 It is a flowchart of the preparation method of the low-power and high-performance memristor of the present invention.
[0042] Figure 3 It is a TZDB curve graph of the device with a TiN intercalation thickness of 0 nm (without intercalation).
[0043] Figure 4 It is a TZDB curve graph of the device with a TiN intercalation thickness of 2.2 nm.
[0044] Figure 5 It is a TZDB curve graph of the device with a TiN intercalation thickness of 4.4 nm.
[0045] Figure 6 It is a TZDB curve graph of the device with a TiN intercalation thickness of 8.8 nm.
[0046] Figure 7 It is an I-V test result graph of the device with a TiN intercalation thickness of 0 nm (without intercalation).
[0047] Figure 8 It is an I-V test result graph of the device with a TiN intercalation thickness of 2.2 nm.
[0048] Figure 9 It is an I-V test result graph of the device with a TiN intercalation thickness of 4.4 nm.
[0049] Figure 10 It is an I-V test result graph of the device with a TiN intercalation thickness of 8.8 nm.
[0050] Figure 11 It is a schematic diagram of forming a three-dimensionally expandable non-volatile memory array according to the present invention.
[0051] Figure 12 It is a schematic diagram of forming a three-dimensional cross-point memory array with ultra-high storage density according to the present invention.
[0052] In the figure: 1. Substrate, 2. Bottom electrode, 3. Intercalation layer, 4. Dielectric layer, 5. Top electrode, 6. Memristor, 7. Transistor. Detailed implementation mode
[0053] The low-power and high-performance memristor of the present invention, as Figure 1 shown, sequentially includes a substrate 1, a bottom electrode 2, an interlayer 3, a dielectric layer 4, and a top electrode 5 from bottom to top. The material of the substrate 1 is Si. The material of the bottom electrode 1 is Cu, Mo, or W, and the thickness is 50 nm. The material of the interlayer 3 is TiN, and the thickness is 0.5 nm - 10 nm, preferably 2 nm - 8.8 nm. The material of the dielectric layer 4 is Al2O3, HfO2, or ZrO2, or it can also be a composite layer of these three material dielectric layers, and the thickness is 10 nm. The material of the top electrode 5 is Cu, Mo, or W, and the thickness is 50 nm.
[0054] Figure 2 The preparation process of the low-power and high-performance memristor of the present invention is given.
[0055] The following gives specific embodiments.
[0056] Embodiment 1
[0057] For the memristor in this embodiment, the material of the substrate 1 is Si. The material of the bottom electrode 2 is Mo, and the thickness is 50 nm. The material of the interlayer 3 is TiN, and the material of the top electrode 5 is Cu, and the thickness is 50 nm. The material of the dielectric layer 4 is HfO2, and the thickness is 10 nm.
[0058] Refer to Figure 2 , the preparation process is as follows:
[0059] (1) Clean the Si substrate 1:
[0060] Clean the Si substrate 1 successively with acetone and absolute ethanol, and dry it with nitrogen; then soak and rinse it with deionized water, and finally dry it with nitrogen.
[0061] (2) Prepare the bottom electrode 2:
[0062] On the cleaned Si substrate 1, prepare the Mo bottom electrode 2 by using the existing electron beam process, and the thickness is 50 nm. The power of the DC power supply is 30 W.
[0063] (3) Deposit the TiN interlayer 3:
[0064] Deposit the TiN interlayer 3 on the bottom electrode 2 by using the magnetron sputtering process, and the thickness is 2.2 nm.
[0065] (4) Deposit the HfO2 dielectric layer 4:
[0066] Prepare the HfO2 dielectric layer 4 on the TiN interlayer 3 by using the atomic layer deposition process, and the thickness is 10 nm.
[0067] (5) Coating photoresist on the dielectric layer, exposing and developing:
[0068] Coat positive photoresist on the dielectric layer, pre-bake at 120 °C for 110 s. After exposure and patterning, soak in the developer for 30 - 60 s for development, and rinse and blow dry with deionized water.
[0069] (6) Fabricating the Cu top electrode 5:
[0070] Fabricate the Cu top electrode 5 on the HfO2 dielectric layer 4 by vacuum thermal evaporation process, with a thickness of 50 nm.
[0071] (7) Removing the photoresist:
[0072] Soak in the acetone solution until the photoresist falls off, and clean with absolute ethanol and deionized water; then blow dry with a nitrogen gun.
[0073] (8) Electrical testing:
[0074] Use a probe station (Cascade Summit 12000) and a semiconductor device parameter analyzer (Keysight B1500A) to test the I-V characteristics of the device, such as the on / off ratio of high and low resistance states (I on / off ) and other key performance.
[0075] According to the above process, make the thickness of the TiN interlayer 3 deposited in step (3) be 4.4 nm and 8.8 nm.
[0076] In this embodiment, three kinds of TiN interlayer memristors with the thicknesses of the TiN interlayer 3 being 2.2 nm, 4.4 nm, and 8.8 nm are obtained.
[0077] Example 2
[0078] The difference between the memristor in this example and that in Example 1 is that the material of the bottom electrode 2 is W, the material of the top electrode 5 is Mo, and the thickness of the TiN interlayer 3 is 6 nm. The preparation process is the same as that in Example 1, except that the DC power supply power in step (2) is 25 W.
[0079] In this example, a TiN interlayer memristor with a TiN interlayer thickness of 6 nm is obtained.
[0080] Example 3
[0081] The difference between the memristor in this example and that in Example 1 is that the material of the bottom electrode 2 is Cu, the material of the dielectric layer 4 is Al2O3. The thickness of the interlayer 3 is 0.5 nm. The preparation process is the same as that in Example 1.
[0082] In this example, a TiN interlayer memristor with a TiN interlayer thickness of 0.5 nm is obtained.
[0083] Example 4
[0084] The difference between the memristor in this embodiment and that in Embodiment 1 is that the material of the top electrode 5 is Mo, the material of the dielectric layer 4 is ZrO2, and the thickness of the interlayer 3 is 1 nm.
[0085] This embodiment obtains a TiN interlayer memristor with a TiN interlayer thickness of 1 nm.
[0086] Embodiment 5
[0087] The difference between the memristor in this embodiment and that in Embodiment 1 is that the material of the dielectric layer 4 is a composite layer of a ZrO2 layer and an Al2O3 layer, and the thicknesses of the two layers are the same. The thickness of the interlayer 3 is 3 nm. The preparation process is the same as that in Embodiment 1, except that in step (4), the Al2O3 layer is deposited after the ZrO2 layer is deposited.
[0088] This embodiment obtains a TiN interlayer memristor with a TiN interlayer thickness of 3 nm.
[0089] Embodiment 6
[0090] The difference between the memristor in this embodiment and that in Embodiment 1 is that the material of the dielectric layer 4 is a composite layer of an HfO2 layer, a ZrO2 layer and an Al2O3 layer, and the thicknesses of the three layers are the same. The thickness of the interlayer 3 is 10 nm. The preparation process is the same as that in Embodiment 1, except that in step (4), HfO2, ZrO2 layer and Al2O3 layer are deposited in sequence. The preparation process is the same as that in Embodiment 1.
[0091] This embodiment obtains a TiN interlayer memristor with a TiN interlayer thickness of 10 nm.
[0092] Comparative Example
[0093] The memristor in the comparative example only contains the substrate 1, the bottom electrode 2, the dielectric layer 4 and the top electrode 5, and does not have the TiN interlayer 3. The materials and thicknesses of each layer are the same as those in Embodiment 1. The preparation process is as follows:
[0094] (1) Cleaning the Si substrate 1: The same as step (1) of Embodiment 1.
[0095] (2) Preparing the bottom electrode 2: The same as step (2) of Embodiment 1.
[0096] (3) Depositing the HfO2 dielectric layer 4:
[0097] The HfO2 dielectric layer 4 with a thickness of 10 nm is prepared on the bottom electrode 2 by atomic layer deposition process.
[0098] (4) Coating photoresist on the dielectric layer, exposing and developing: The same as step (5) of Embodiment 1.
[0099] (5) Preparing the Cu top electrode 5:
[0100] The Cu top electrode 5 is prepared on the HfO2 dielectric layer 4 by a vacuum thermal evaporation process, and the thickness is 50 nm.
[0101] (6) Removing the photoresist: The same as step (7) of Example 1.
[0102] (7) Electrical testing: The same as step (8) of Example 1.
[0103] Perform TZDB characteristics testing and I-V testing on the memristors of Example 1 and the comparative example.
[0104] 1. TZDB characteristics testing
[0105] In order to further evaluate the influence of the TiN interlayer on the reliability of the device dielectric layer, time-dependent dielectric breakdown (TZDB) testing was performed on the memristors of Example 1 and the comparative example. This test is used to evaluate the instantaneous breakdown characteristics of the dielectric layer under different voltages, and further analyze the interfacial electric field distribution of the device and the stability of the oxide layer.
[0106] Testing method: During the testing process, an increasing bias voltage is applied to the two devices, and the distribution of the breakdown voltage (V BD ) is recorded. The test environment is kept consistent to ensure the comparability of the data.
[0107] Figure 3 The TZDB curve of the device in the comparative example (without TiN interlayer) is given. Figure 4 The TZDB curve of the device with a TiN interlayer thickness of 2.2 nm is given. Figure 5 The TZDB curve of the device with a TiN interlayer thickness of 4.4 nm is given. Figure 6 The TZDB curve of the device with a TiN interlayer thickness of 8.8 nm is given.
[0108] In Example 1, for the devices with different TiN interlayer thicknesses, the measured breakdown voltages are as follows: when the TiN interlayer thickness is 2.2 nm, the breakdown voltages of the device are -5.18 V and 3.43 V; when the TiN interlayer thickness is 4.4 nm, the breakdown voltages of the device are -4.55 V and 3.15 V; when the TiN interlayer thickness is 8.8 nm, the breakdown voltages of the device are -4.8 V and 3.4 V.
[0109] In contrast, in the comparative example (without TiN interlayer), the measured breakdown voltage of the device is -4.62 V and 3.78 V.
[0110] The above results indicate that the TiN interlayer has a significant impact on both the breakdown voltage and memristive performance of the device. Compared with the comparative example (without TiN interlayer), after introducing the TiN interlayer, the change trend of the negative breakdown voltage indicates that the interfacial oxidation state has been optimized. Among them, the TiN interlayer with a thickness of 2.2 nm exhibits the highest negative breakdown voltage (-5.18 V), indicating that a thinner TiN interlayer can effectively reduce interfacial oxygen vacancy defects and improve the breakdown tolerance. However, when the TiN thickness increases to 4.4 nm, the negative breakdown voltage decreases (-4.55 V), which may be due to the change in the local oxygen vacancy concentration, affecting the interfacial stability. As the TiN thickness further increases to 8.8 nm, the negative breakdown voltage rebounds to -4.8 V, indicating that appropriately increasing the TiN thickness helps to optimize the interfacial characteristics and make the electric field distribution more uniform.
[0111] 2. I-V Test Results
[0112] The I-V characteristics of the memristors in Example 1 and the comparative example were tested. Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 The I-V test results of the devices under the comparative example (without TiN interlayer), TiN interlayer thicknesses of 2.2 nm, 4.4 nm, and 8.8 nm are respectively given.
[0113] For Example 1, when the TiN interlayer thickness is 8.8 nm, the Ion / off ratio reaches 3.51×10 5 , showing excellent switching characteristics. This indicates that the TiN interlayer significantly improves the conductive characteristics of the device and effectively enhances the separation between the high and low resistance states. The test results also show that the device only requires operating voltages of -1 V and 2 V to achieve stable switching operations, which further indicates that the TiN interlayer plays an important role in optimizing the device performance, enabling stable switching at a low operating voltage and significantly improving the low-power storage capacity of the device.
[0114] The test results of Comparative Example 1 show that the I on / off ratio is only 2, indicating that the memristive performance of the device significantly decreases without the TiN interlayer. In this case, the distinction between the high and low resistance states is extremely low, making it difficult for the device to distinguish different conductance states, thereby affecting its storage capacity. In addition, the device in the comparative example requires a relatively high operating voltage (±4 V) to achieve switching operations, indicating that the performance and power consumption of the device are severely affected without the TiN interlayer.
[0115] The low-power and high-performance memristor of the present invention can cooperate with transistors, one is to form a three-dimensionally expandable non-volatile memory array, and the other is to form a three-dimensional cross-point memory array with ultra-high storage density.
[0116] Figure 11 It presents an expansion of high-density integration based on Figure 1 the low-power and high-performance memristor structure shown: adopting a 1TnR array architecture, including 1 transistor 7 and n low-power and high-performance memristors 6 in the present invention, vertically integrating the low-power and high-performance memristor 6 with the transistor 7 to form a non-volatile memory array that can be three-dimensionally expanded.
[0117] Figure 12 It presents an expansion of three-dimensional integration based on Figure 1 the low-power and high-performance memristor structure shown: constructing a 3D stacked structure through a multi-layer interconnection process, realizing the co-integration of the low-power and high-performance memristor 6 and the select transistor 7 in the vertical direction to form a three-dimensional cross-point memory array with ultra-high storage density.
Claims
1. A low-power and high-performance memristor, characterized in that It includes a substrate, a bottom electrode, a dielectric layer and a top electrode. An interlayer is provided between the bottom electrode and the dielectric layer, and the interlayer material is TiN.
2. The low-power and high-performance memristor according to claim 1, characterized in that, The bottom electrode material is Cu, Mo or W; the dielectric layer material is Al2O3, HfO2, ZrO2 or a composite layer thereof; the top electrode material is Cu, Mo or W.
3. The low-power and high-performance memristor according to claim 1, characterized in that, The thickness of the bottom electrode is 50 nm, the thickness of the dielectric layer is 10 nm, and the thickness of the top electrode is 50 nm.
4. The low-power high-performance memristor according to claim 1, characterized in that, The thickness of the interlayer is 0.5 nm - 10 nm.
5. The low-power high-performance memristor according to claim 1, characterized in that, The thickness of the interlayer is 8.8 nm.
6. The low-power and high-performance memristor according to claim 1, characterized in that, The bottom electrode material is Mo, the top electrode material is Cu, the dielectric layer material is HfO2, the interlayer material is TiN and the thickness is 8.8 nm.
7. A preparation method of the low-power high-performance memristor according to any one of claims 1-6, characterized in that, It includes the following steps: (1) Clean the substrate; (2) Deposit the bottom electrode on the substrate; (3) Deposit the TiN interlayer on the bottom electrode; (4) Deposit the dielectric layer on the TiN interlayer; (5) Coat photoresist on the dielectric layer, expose and develop to pattern the top electrode; (6) Fabricate the top electrode on the dielectric layer with the top electrode patterned; (7) Remove the photoresist.
8. The preparation method of the low-power and high-performance memristor according to claim 1, characterized in that, In step (2), the bottom electrode is fabricated on the substrate by an electron beam process. In step (3), the interlayer is deposited on the bottom electrode by a magnetron sputtering process. In step (4), the dielectric layer is fabricated on the interlayer by an atomic layer deposition process. The fabrication process of the top electrode in step (6) includes but is not limited to magnetron sputtering, electron beam sputtering and vacuum thermal evaporation.
9. The application of the low-power high-performance memristor according to any one of claims 1-6 is to form a three-dimensionally expandable non-volatile memory array. An array architecture of 1 transistor and n low-power high-performance memristors is adopted. The low-power high-performance memristor and the transistor are vertically integrated to form a three-dimensionally expandable non-volatile memory array.
10. The application of the low-power high-performance memristor according to any one of claims 1-6 is to form a three-dimensional cross-point memory array with ultra-high storage density. A 3D stacked structure is constructed by a multi-layer interconnection process, and the low-power high-performance memristor and the transistor are integrated in the vertical direction to form a three-dimensional cross-point memory array with ultra-high storage density.