Filter, manufacturing method thereof and electronic equipment

Abstract

Provided is a filter, comprising: a substrate comprising a first surface; the capacitor comprises a first electrode arranged on the first surface and a second electrode arranged on the side, away from the substrate, of the first electrode, and a first insulating layer is arranged between the first electrode and the second electrode; the second insulating layer is arranged on one side, far away from the substrate, of the second electrode, and a first via hole is formed in the second insulating layer; the inductor comprises a first conductive end and a second conductive end, and the first conductive end and the second conductive end are electrically connected to form a coil structure of the inductor; the third insulating layer is arranged on one side, far away from the substrate, of the second insulating layer, and a second via hole is formed in the third insulating layer; the electrode conductive part is arranged on one side, far away from the substrate, of the third insulating layer and is electrically connected with the second electrode through the first via hole and the second via hole; the radial cross-sectional area of the first via hole is smaller than that of the second via hole, and the orthographic projection of the first via hole on the substrate is overlapped with the orthographic projection of the second via hole on the substrate.

Description

Filter and manufacturing method thereof, and electronic equipment Technical Field

[0001] The present disclosure relates to the technical field of passive filtering, and in particular to a filter, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of manufacturing technology and consumer electronics, the miniaturization, high integration, lightweight, comprehensiveness and universality of passive filters are becoming increasingly important. However, due to the limitations of design and manufacturing processes, existing filters cannot achieve miniaturization. During the manufacturing process, due to dimensional deviations and other factors, the functions of the filters are greatly different from the designed functions, resulting in a decrease in the yield of the product.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0004] Summary of the Invention

[0005] In one aspect, a filter is provided, comprising: a substrate, comprising a first surface and a second surface arranged opposite to each other along a thickness direction; a capacitor, comprising a first electrode arranged on the first surface and a second electrode arranged on a side of the first electrode away from the substrate, with a first insulating layer arranged between the first electrode and the second electrode; a second insulating layer, arranged on a side of the second electrode away from the substrate, with a first via provided on the second insulating layer; an inductor, comprising a first conductive end and a second conductive end, the first conductive end and the second conductive end being electrically connected to form a coil structure of the inductor; a third insulating layer, arranged on a side of the second insulating layer away from the substrate, with a second via provided on the third insulating layer; an electrode conductive portion, arranged on a side of the third insulating layer away from the substrate, the electrode conductive portion being electrically connected to the second electrode through the first via and the second via; a radial cross-sectional area of ​​the first via is smaller than a radial cross-sectional area of ​​the second via, and an orthographic projection of the first via on the substrate overlaps with an orthographic projection of the second via on the substrate.

[0006] In some exemplary embodiments of the present disclosure, the orthographic projection of the second electrode on the base substrate is located within the orthographic projection of the first insulating layer on the base substrate; the orthographic projection of the first insulating layer on the base substrate is located within the orthographic projection of the second insulating layer on the base substrate; and the orthographic projection of the second insulating layer on the base substrate is located within the orthographic projection of the third insulating layer on the base substrate.

[0007] In some exemplary embodiments of the present disclosure, the orthographic projection of the second electrode on the base substrate is located within the orthographic projection of the first electrode on the base substrate, and the orthographic projection of the first insulating layer on the base substrate is located within the orthographic projection of the first electrode on the base substrate.

[0008] In some exemplary embodiments of the present disclosure, an orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the second electrode on the base substrate.

[0009] In some exemplary embodiments of the present disclosure, the orthographic projection of the second electrode on the base substrate is located within the orthographic projection of the second via hole on the base substrate.

[0010] In some exemplary embodiments of the present disclosure, the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the first insulating layer on the base substrate, and the orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the second insulating layer on the base substrate.

[0011] In some exemplary embodiments of the present disclosure, the orthographic projection of the first via on the base substrate is located within the orthographic projection of the second via on the base substrate, and the orthographic projection of the second via on the base substrate is located within the orthographic projection of the first insulating layer on the base substrate.

[0012] In some exemplary embodiments of the present disclosure, the orthographic projection of the first via on the base substrate partially overlaps with the orthographic projection of the second via on the base substrate, and the orthographic projection of the second via on the base substrate partially overlaps with the orthographic projection of the first insulating layer on the base substrate.

[0013] In some exemplary embodiments of the present disclosure, a thickness of the third insulating layer is greater than a thickness of the second insulating layer and a thickness of the first insulating layer.

[0014] In some exemplary embodiments of the present disclosure, the thickness of the third insulating layer is in a range from 3 micrometers to 5 micrometers.

[0015] In some exemplary embodiments of the present disclosure, the thickness of the first insulating layer is greater than or equal to 0.1 micrometers; and the thickness of the second insulating layer is greater than or equal to 0.2 micrometers.

[0016] In some exemplary embodiments of the present disclosure, a diameter of the first via hole is greater than or equal to 3 micrometers.

[0017] In some exemplary embodiments of the present disclosure, a diameter of the second via hole is greater than or equal to 15 micrometers.

[0018] In some exemplary embodiments of the present disclosure, the first via hole is formed by a dry etching process, and the second via hole is formed by a photolithography process.

[0019] In some exemplary embodiments of the present disclosure, the first via holes include a plurality of holes, and an array formed by orthographic projections of the plurality of first via holes on the base substrate is located within the orthographic projections of the second via holes on the base substrate.

[0020] In some exemplary embodiments of the present disclosure, the first conductive end includes: a first conductive portion, which is located in the same layer as the first electrode and is electrically connected to the first electrode; a second conductive portion, which is arranged on a side of the third insulating layer away from the base substrate, and the second conductive portion is electrically connected to the first conductive portion through a first connecting via provided on the third insulating layer; a third conductive portion, which is arranged on a side of the base substrate close to the second surface, and the third conductive portion is electrically connected to the first conductive portion through a first substrate via provided on the base substrate; the second conductive end includes: a fourth conductive portion, which is arranged in the same layer as the second conductive portion and the electrode conductive portion; a fifth conductive portion, which is located in the same layer as the third conductive portion, and the fifth conductive portion is electrically connected to the fourth conductive portion through a second substrate via provided on the base substrate and a second connecting via provided on the third insulating layer; a sixth conductive portion, which is arranged between the fourth conductive portion and the fifth conductive portion, and the sixth conductive portion is located in the same layer as the first electrode and the first conductive portion.

[0021] In some exemplary embodiments of the present disclosure, radial cross-sectional areas of the first substrate via hole and the second substrate via hole gradually increase from the thickness center of the base substrate toward the first surface or the second surface.

[0022] In some exemplary embodiments of the present disclosure, a step difference between inner walls of the first substrate via hole and the second substrate via hole is less than 0.1 micrometer.

[0023] In some exemplary embodiments of the present disclosure, the first substrate via hole and the second substrate via hole are filled with a conductive material, and the conductive material includes an adhesion layer, a first conductive layer, and a second conductive layer sequentially arranged from the inner wall of the via hole toward the central axis of the via hole.

[0024] In some exemplary embodiments of the present disclosure, the filter further includes: a first protective layer, arranged on a side of the second conductive part, the fourth conductive part and the electrode conductive part away from the substrate; a connecting pad, arranged on a side of the first protective layer away from the substrate, including a first connecting pad, a second connecting pad and a third connecting pad, the first connecting pad is electrically connected to the electrode conductive part, the second connecting pad is electrically connected to the second conductive part, and the third pad is electrically connected to the fourth conductive part; a second protective layer is arranged on a side of the third conductive part and the fifth conductive part away from the substrate.

[0025] In some exemplary embodiments of the present disclosure, the filter further includes: a fourth insulating layer, arranged on a side of the electrode conductive part away from the substrate; the first conductive end includes: a first conductive part, located on the same layer as the first electrode and electrically connected to the first electrode; a second conductive part, arranged on a side of the third insulating layer away from the substrate, the second conductive part is electrically connected to the first conductive part through a first connecting via provided on the third insulating layer; a third conductive part, arranged on a side of the second conductive part away from the substrate, the third conductive part is electrically connected to the second conductive part through a first conductive via provided on the fourth insulating layer; the second conductive end includes: a fourth conductive part, arranged on the same layer as the second conductive part and the electrode conductive part; a fifth conductive part, located on the same layer as the third conductive part, the fifth conductive part is electrically connected to the fourth conductive part through a second conductive via provided on the fourth insulating layer.

[0026] In some exemplary embodiments of the present disclosure, the filter further includes: a first protective layer, arranged on a side of the third conductive part, the fifth conductive part and the electrode conductive part away from the substrate; a connecting pad, arranged on a side of the first protective layer away from the substrate, including a first connecting pad, a second connecting pad and a third connecting pad, the first connecting pad is electrically connected to the electrode conductive part, the second connecting pad is electrically connected to the third conductive part, and the third connecting pad is electrically connected to the fifth conductive part.

[0027] In some exemplary embodiments of the present disclosure, at least one of the first electrode, the electrode conductive portion, the first conductive portion, the second conductive portion, the third conductive portion, the fourth conductive portion, and the fifth conductive portion includes a first conductive structure; the first conductive structure includes: a first metal layer close to the base substrate, a second metal layer away from the base substrate, and a third metal layer located between the first metal layer and the second metal layer; the third metal layer and the second metal layer use the same metal material, and the grain size of the third metal layer is smaller than the grain size of the second metal layer.

[0028] In some exemplary embodiments of the present disclosure, the second electrode includes a second conductive structure; the second conductive structure includes: a fourth metal layer close to the base substrate, a fifth metal layer away from the base substrate, and a sixth metal layer located between the fourth metal layer and the fifth metal layer.

[0029] In some exemplary embodiments of the present disclosure, the base substrate includes a glass substrate or a high-resistance silicon substrate.

[0030] Another aspect of the embodiments of the present disclosure provides a method for manufacturing a filter, which includes: providing a substrate, including a first surface and a second surface arranged opposite to each other along a thickness direction; forming a capacitor, including forming a first electrode on the first surface and a second electrode on a side of the first electrode away from the substrate, with a first insulating layer formed between the first electrode and the second electrode; forming a second insulating layer, including forming the second insulating layer on a side of the second electrode away from the substrate, with a first via formed on the second insulating layer; forming an inductor, including forming a first conductive end and a second conductive end, with the first conductive end and the second conductive end being electrically connected to form a coil structure of the inductor; forming a third insulating layer, including forming the third insulating layer on a side of the second insulating layer away from the substrate, with a second via formed on the third insulating layer; forming an electrode conductive portion, including forming the electrode conductive portion on a side of the third insulating layer away from the substrate, with the electrode conductive portion being electrically connected to the second electrode through the first via and the second via; the radial cross-sectional area of ​​the first via is smaller than the radial cross-sectional area of ​​the second via, and the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the second via on the substrate.

[0031] In some exemplary embodiments of the present disclosure, the first via hole is formed by dry etching, and the second via hole is formed by a photolithography process.

[0032] Another aspect of the embodiments of the present disclosure provides an electronic device, which includes the filter described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0034] FIG1 is a schematic diagram of a filter circuit according to an exemplary embodiment of the present disclosure;

[0035] FIG2A is a schematic structural diagram of a filter according to an exemplary embodiment of the present disclosure;

[0036] FIG2B is a schematic diagram of a partially enlarged planar structure of a capacitor according to an exemplary embodiment of the present disclosure;

[0037] FIG2C is a schematic diagram of a partially enlarged planar structure of a capacitor according to another exemplary embodiment of the present disclosure;

[0038] FIG2D is a schematic diagram of a partially enlarged planar structure of a capacitor according to another exemplary embodiment of the present disclosure;

[0039] FIG2E is a schematic diagram of a partially enlarged planar structure of a capacitor according to yet another exemplary embodiment of the present disclosure;

[0040] 2F is a schematic diagram of a partially enlarged planar structure in which a second via hole of a capacitor partially overlaps with a second electrode according to an exemplary embodiment of the present disclosure;

[0041] 2G is a schematic diagram of a partially enlarged planar structure of an electrode in which a second via hole partially overlaps with a first via hole according to an exemplary embodiment of the present disclosure;

[0042] 2H is a schematic diagram of a partially enlarged planar structure in which the second electrode of a capacitor is smaller than the second via hole according to an exemplary embodiment of the present disclosure;

[0043] FIG3 is a schematic top view of the inductor of the filter of the embodiment of FIG2A ;

[0044] FIG4 is a schematic structural diagram of a filter according to another exemplary embodiment of the present disclosure;

[0045] FIG5 is a schematic top view of the inductor of the filter of the embodiment of FIG4 ;

[0046] 6A to 6M are flow charts of a process for preparing a filter according to the exemplary embodiment of FIG. 2A of the present disclosure;

[0047] 7A to 7G are top view flow charts of a process for manufacturing an inductor of the filter of the exemplary embodiment of FIG. 2A of the present disclosure;

[0048] 8A to 8K are flow charts of a process for preparing a filter according to the exemplary embodiment of FIG. 4 of the present disclosure;

[0049] FIG9 is a schematic structural diagram of an electronic device according to an exemplary embodiment of the present disclosure.

[0050] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0053] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0054] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0055] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0056] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0057] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0058] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel region, such as the longitudinal and transverse directions of a pixel region, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0059] In the related art, LC filters that generally use glass substrates or high-resistance silicon substrates usually involve multi-layer metal stacking and overlapping. The design of the overlapping holes of each layer of metal and the patterning process during the preparation process directly determine the performance and reliability of the filter. The more metal layers there are, the more difficult the process is, the greater the risk of failure of the prepared filter is, and the yield is low. For example, when it comes to the stacking of multiple layers of metal and multiple layers of insulating materials, vias, and upper and lower metal overlaps, in order to reduce the crosstalk between the upper and lower redistributed layers (RDL), while ensuring the thickness of the RDL traces (for example, a thickness greater than 5 microns) to ensure the performance of the inductor and capacitor, the PI thickness between the RDL layers is usually required to be greater than 5 microns. Since the interlayer PI usually uses negative PI material, the position that needs to be retained is exposed, and then the remaining parts are developed and removed. Due to the reflection and diffraction of the ultraviolet light of the exposure machine, the PI opening is more seriously affected by the surrounding stray ultraviolet light, and the reflection and diffraction effect is more obvious for the glass substrate, which will cause PI residue at the opening or unclean development. In order to ensure the conductivity of the upper and lower RDL layers, it is necessary to ensure that the interlayer PI openings are clean, and there must be no residual PI and developer reactants, etc. When the thicker PI is opened, the opening diameter needs to be greater than a certain size, for example, greater than 15 microns. In addition, due to the alignment deviation of the exposure machine and the offset of the overlay between the layers, the size of the capacitor electrode usually needs to be greater than a certain size of the PI opening to ensure that the PI opening falls completely within the capacitor electrode and that the actual size of the capacitor electrode is consistent with the design value, otherwise the capacitance value will change, thereby causing the filter frequency to shift. In addition, the restriction on the minimum size of the capacitor electrode also greatly limits the design of the LC filter. For example, the design of a small capacitor requires several large capacitors in series, which greatly increases the complexity and size of the device. This results in higher manufacturing costs and lower yields for small-sized capacitors.

[0060] In order to meet the requirements of filters for small-size capacitors, an embodiment of the present disclosure provides a filter, including but not limited to: a substrate, including a first surface and a second surface arranged opposite to each other along the thickness direction; a capacitor, including a first electrode arranged on the first surface and a second electrode arranged on a side of the first electrode away from the substrate, a first insulating layer arranged between the first electrode and the second electrode; a second insulating layer, arranged on a side of the second electrode away from the substrate, a first via arranged on the second insulating layer; an inductor, including a first conductive end and a second conductive end, the first conductive end and the second conductive end being electrically connected to form a coil structure of the inductor; a third insulating layer, arranged on a side of the second insulating layer away from the substrate, a second via arranged on the third insulating layer; an electrode conductive portion, arranged on a side of the third insulating layer away from the substrate, the electrode conductive portion being electrically connected to the second electrode through the first via and the second via; the radial cross-sectional area of ​​the first via is smaller than the radial cross-sectional area of ​​the second via, and the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the second via on the substrate.

[0061] According to the filter of the embodiment of the present disclosure, by providing a second insulating layer on the side of the second electrode away from the substrate, the electrode conductive part and the second electrode are separated, thereby avoiding the influence of the electrode conductive part on the second electrode of the capacitor, ensuring that the capacitance value remains unchanged and the center frequency remains stable. In addition, by providing a first via in the second insulating layer and a second via in the third insulating layer, and the radial cross-sectional area of ​​the first via is smaller than the radial cross-sectional area of ​​the second via, the second electrode of the capacitor can be separated from the electrode conductive part, so that the second electrode of the capacitor can be smaller than the size of the second via, meeting the miniaturization design of the capacitor. The capacitor with this miniaturized design does not need to connect multiple large capacitors in series, and at the same time has a simple structure, low manufacturing cost and high yield.

[0062] FIG1 is a schematic diagram of a filtering circuit according to an exemplary embodiment of the present disclosure.

[0063] As shown in FIG1 , the filter circuit includes an inductor L, a capacitor C, and a resistor R, wherein the inductor L, capacitor C, and resistor R each include a first end and a second end, which are electrically connected to implement the filter circuit function. For example, the second end of the resistor R is electrically connected to the first end of the inductor L, and the second end of the inductor L is electrically connected to the first end of the capacitor C. The resistor R can be implemented by a resistive wire or a high-resistance material, such as tin oxide, nickel-chromium alloy, etc.

[0064] In other optional embodiments, the number of inductors, capacitors, and resistors can be designed according to actual needs, and the present disclosure does not impose any specific limitation on the number of inductors, capacitors, and resistors.

[0065] FIG2A is a schematic structural diagram of a filter according to an exemplary embodiment of the present disclosure.

[0066] As shown in Figure 2A, the filter 100 includes a base substrate BA, which includes a first surface S1 and a second surface S2 arranged along a thickness direction. At least one capacitor C and at least one inductor L are integrated on the base substrate BA.

[0067] The capacitor includes a first electrode C1 disposed on the first surface S1 and a second electrode C2 disposed on a side of the first electrode C1 away from the base substrate BA. A first insulating layer D1 is disposed between the first electrode C1 and the second electrode C2. The first insulating layer D1 is used to separate the first electrode C1 from the second electrode C2. The thickness of the first insulating layer D1 is related to the actual capacitor design to meet the capacitance requirements in different scenarios.

[0068] An inductor includes a first conductive end and a second conductive end, wherein the first conductive end and the second conductive end are electrically connected to form a coil structure of the inductor. A wire located in different film layers is disposed between the first conductive end and the second conductive end, thereby forming a coil structure. For example, the coil includes an inductor having a 3D coil structure and an inductor having a 2D coil structure, as described below.

[0069] The filter 100 further includes a second insulating layer D2 and a third insulating layer D3. The second insulating layer D2 is disposed on a side of the second electrode C2 away from the base substrate BA, and a first via hole vhl is disposed on the second insulating layer D2. The third insulating layer D3 is disposed on a side of the second insulating layer D2 away from the base substrate BA, and a second via hole vh2 is disposed on the third insulating layer D3.

[0070] The filter 100 further includes an electrode conductive portion DE1 , which is disposed on a side of the third insulating layer D3 away from the base substrate BA and is electrically connected to the second electrode C2 through the first via hole vh1 and the second via hole vh2 .

[0071] A radial cross-sectional area of ​​the first via hole vh1 is smaller than a radial cross-sectional area of ​​the second via hole vh2 , and an orthographic projection of the first via hole vh1 on the base substrate overlaps with an orthographic projection of the second via hole vh2 on the base substrate.

[0072] In some embodiments of the present disclosure, the first via hole vh1 and the second via hole vh2 can be holes of regular shape in the radial direction, such as a circular hole, a square hole, an elliptical hole, a rectangular hole, or a polygonal hole. In optional embodiments, they can also be via holes of irregular shape. The first via hole penetrates the second insulating layer, the second via hole penetrates the third insulating layer, and the first via hole and the second via hole form a sleeve hole structure, that is, the first via hole and the second via hole are connected, so that a portion of the electrode conductive portion is located in the first via hole and the second via hole, and the electrode conductive portion is electrically connected to the second electrode through the first via hole and the second via hole.

[0073] Figure 2B is a partially enlarged schematic plan view of a capacitor according to an exemplary embodiment of the present disclosure. Figure 2C is a partially enlarged schematic plan view of a capacitor according to another exemplary embodiment of the present disclosure.

[0074] 2A , 2B and 2C , the specific structure of the area where the capacitor C of the filter 100 is located is that a first electrode C1 , a first insulating layer D1 , a second electrode C2 , a second insulating layer D2 , a third insulating layer D3 and an electrode conductive portion DE1 are sequentially arranged on the first surface S1 of the base substrate BA.

[0075] For example, as shown in Figures 2B and 2C , the orthographic projection of the second electrode C2 on the base substrate BA is located within the orthographic projection of the first insulating layer D1 on the base substrate BA. In other words, the first insulating layer D1 completely separates the first electrode C1 from the second electrode C2, thereby forming a capacitor and preventing a short circuit between the first electrode C1 and the second electrode C2.

[0076] The orthographic projection of the first insulating layer D1 on the base substrate BA is located within the orthographic projection of the second insulating layer D2 on the base substrate BA. That is, the second insulating layer D2 can completely cover the first insulating layer D1, preventing the second electrode C2 between the second insulating layer D2 and the first insulating layer D1 from being affected by the upper electrode conductive portion DE1.

[0077] The orthographic projection of the second insulating layer D2 on the base substrate BA is located within the orthographic projection of the third insulating layer D3 on the base substrate BA. The third insulating layer D3 is used to separate the conductive material of the layer where the electrode conductive portion DE1 is located from the conductive material near the base substrate (e.g., the first electrode and the second electrode), thereby avoiding short circuit problems caused by via overlap. Therefore, the third insulating layer can be configured to completely cover the second insulating layer.

[0078] As shown in Figures 2B and 2C, the orthographic projection of the second electrode C2 on the base substrate BA is located within the orthographic projection of the first electrode C1 on the base substrate BA, and the orthographic projection of the first insulating layer D1 on the base substrate is located within the orthographic projection of the first electrode C1 on the base substrate BA. In this embodiment, the orthographic projection of the first electrode C1 on the base substrate BA is set larger, thereby avoiding dimensional deviations caused by the offset and misalignment of the second electrode C2 due to the alignment deviation with the first electrode C1 during the formation of the second electrode C2, thereby avoiding the problem of deviation between the actual capacitance value and the designed capacitance value due to manufacturing deviation, thereby improving the yield of the product. The first insulating layer can effectively separate the first electrode from the second electrode, thereby forming an effective capacitor.

[0079] As shown in FIG2B , the first via hole vh1 can be set as a round hole, and the second via hole vh2 can be set as a round hole. As shown in FIG2C , the first via hole vh1 can be set as a square hole, and the second via hole vh2 can be set as a round hole.

[0080] In other optional embodiments, the second via hole may also be configured as a square hole, such as a square hole, or a rectangular hole.

[0081] Figure 2D is a partially enlarged schematic plan view of a capacitor according to another exemplary embodiment of the present disclosure. Figure 2E is a partially enlarged schematic plan view of a capacitor according to another exemplary embodiment of the present disclosure.

[0082] For example, the first via holes vh1 include a plurality of holes, and an array formed by orthographic projections of the plurality of first via holes on the substrate is located within the orthographic projections of the second via holes vh2 on the substrate.

[0083] As shown in FIG2D , the plurality of first via holes vh1 are a plurality of circular holes, the orthographic projections of the plurality of circular holes on the base substrate form an array, and the array is located within the orthographic projections of the second via holes vh2 on the base substrate.

[0084] As shown in FIG. 2E , the plurality of first via holes vh1 are a plurality of square holes, the orthographic projections of the plurality of square holes on the base substrate form an array, and the array is located within the orthographic projections of the second via holes on the base substrate.

[0085] In the embodiment of the present disclosure, by providing a plurality of first via holes, the problem of poor contact of individual via holes when forming the metal layer is effectively avoided, thereby improving the reliability of the product.

[0086] Figure 2F is a schematic diagram of a partially enlarged plan view of a capacitor in which a second via partially overlaps with a second electrode according to an exemplary embodiment of the present disclosure. Figure 2G is a schematic diagram of a partially enlarged plan view of an electrode in which a second via partially overlaps with a first via according to an exemplary embodiment of the present disclosure. Figure 2H is a schematic diagram of a partially enlarged plan view of a capacitor in which a second electrode is smaller than a second via according to an exemplary embodiment of the present disclosure.

[0087] 2F to 2H exemplarily illustrate different size relationships between the second electrode and the second via hole according to an embodiment of the present disclosure.

[0088] In one embodiment of the present disclosure, as shown in Figure 2F, the orthographic projection of the first via vh1 on the substrate BA is located within the orthographic projection of the second electrode C2 on the substrate, and the orthographic projection of the first via vh1 on the substrate BA is located within the orthographic projection of the second via vh2 on the substrate BA.

[0089] In the embodiment of the present disclosure, since the orthographic projection of the first via vh1 on the base substrate is located within the orthographic projection of the second electrode C2 on the base substrate, and the orthographic projection of the first via vh1 on the base substrate is located within the orthographic projection of the second via vh2 on the base substrate, the second via vh2 and the first via vh1 form a hole structure that gradually decreases from away from the base substrate toward the base substrate, thereby enabling the capacitor electrode portion DE1 to be electrically connected to the second electrode C2 through the first via vh1 and the second via vh2.

[0090] In related technologies, when the second insulating layer is not provided, when forming the second via, due to process deviation, the second via deviates from the second electrode. At this time, the second via partially overlaps with the orthographic projection of the second electrode on the base substrate. Since the second via is filled with conductive material, the area of ​​the second electrode of the capacitor will increase, and the actual capacitance value will be larger than the theoretical design capacitance value, so that the center frequency will shift to a low frequency, and there will be deviations in the produced products, affecting the yield of the product. In the embodiment of the present disclosure, as described above, since the orthographic projection of the second via on the base substrate is located within the orthographic projection of the second insulating layer on the base substrate, even if the second via deviates from the original position due to the process when forming the second via, due to the insulating effect of the second insulating layer, the area of ​​the second electrode of the capacitor will not increase, resulting in a problem of a larger capacitance value.

[0091] As shown in Figure 2F, the orthographic projection of the first via vh1 on the substrate is located within the orthographic projection of the second via vh2 on the substrate, and the orthographic projection of the second via vh2 on the substrate is also located within the orthographic projection of the first insulating layer D1 on the substrate. Although the second via vh2 is offset, the orthographic projection of the second via vh2 on the substrate BA is still located within the orthographic projection of the first insulating layer D1 on the substrate BA. A second insulating layer D2 is provided between the third insulating layer D3 and the first insulating layer D1. The second insulating layer D2 can eliminate the effect of the metal filling in the second via vh2 on the capacitance value.

[0092] In an optional embodiment, as shown in FIG2G , the orthographic projection of the first via vh1 on the substrate is located within the orthographic projection of the second electrode C2 on the substrate BA, and the orthographic projection of the first via vh1 on the substrate overlaps with the orthographic projection of the second via vh2 on the substrate BA. For example, the orthographic projection of the first via vh1 on the substrate partially overlaps with the orthographic projection of the second via vh2 on the substrate, and the orthographic projection of the second via vh2 on the substrate partially overlaps with the orthographic projection of the first insulating layer D1 on the substrate. That is, the orthographic projections of the first via vh1 and the second via vh2 on the substrate do not completely overlap, but only partially overlap. The orthographic projections of the second via vh2 and the first insulating layer D1 on the substrate also do not completely overlap, but only partially overlap. As a result, even if there are large manufacturing deviations, product defects will not occur.

[0093] In the related art, if the second insulating layer is not provided, when forming the second via, if there is a large manufacturing process deviation, for example, when the second via is offset beyond the edge of the first insulating layer, when the conductive material is filled in the second via, the conductive material will be directly electrically connected to the first electrode of the capacitor, thereby causing the two electrodes of the capacitor to short-circuit, which can easily cause product defects. In the embodiment of the present disclosure, when the second via has a large offset due to the manufacturing process, for example, when the orthographic projection of the second via on the base substrate overlaps with the orthographic projection of the first insulating layer on the base substrate, that is, a part of the orthographic projection of the second via on the base substrate exceeds the orthographic projection of the first insulating layer on the base substrate, since the second insulating layer is provided and the orthographic projection of the first insulating layer on the base substrate is located within the orthographic projection of the second insulating layer on the base substrate, that is, the second insulating layer is larger than the first insulating layer, thereby avoiding the problem of the second electrode and the first electrode being short-circuited due to the offset of the second via caused by the manufacturing process.

[0094] In another embodiment of the present disclosure, as shown in FIG2H , the orthographic projection of the second electrode C2 on the base substrate BA is located within the orthographic projection of the second via hole vh2 on the base substrate BA.

[0095] In some embodiments of the present disclosure, a second insulating layer is provided on the second electrode, so that the electrode conductive portion formed on the side of the second electrode away from the base substrate is separated from the second electrode by a certain distance, and a first via is formed on the second insulating layer, and the radial cross-sectional area of ​​the first via is smaller than the radial cross-sectional area of ​​the second via on the third insulating layer, so that the size of the second electrode of the capacitor can be smaller than the size of the second via, so as to realize the design and manufacture of small-size capacitors, greatly improve production efficiency without increasing manufacturing costs, and ensure product yield.

[0096] The orthographic projection of the first via on the base substrate is located within the orthographic projection of the first insulating layer on the base substrate, and the orthographic projection of the second via on the base substrate is located within the orthographic projection of the second insulating layer on the base substrate. In addition, the orthographic projections of the first via and the second via on the base substrate overlap, for example, including the orthographic projection of the first via on the base substrate being located within the orthographic projection of the second via on the base substrate, or the orthographic projection of the first via on the base substrate partially overlapping the orthographic projection of the second via on the base substrate, to ensure that the conductive portion of the electrode can be electrically connected to the second electrode of the capacitor through the first and second vias.

[0097] In some embodiments of the present disclosure, the thickness of the third insulating layer D3 is greater than the thickness of the second insulating layer D2 and the thickness of the first insulating layer D1 .

[0098] The first insulating layer D1 and the second insulating layer D2 can be an inorganic insulating material, such as an inorganic insulating layer formed by silicon nitride (SiNx), or an inorganic insulating layer formed by silicon dioxide (SiO2), or a composite film layer stacked by several SiNx inorganic insulating layers and SiO2 inorganic insulating layers.

[0099] Exemplarily, the first insulating layer D1 can be, for example, SiNx, which is deposited by standard processes such as plasma enhanced chemical vapor deposition (PECVD). The thickness of the first insulating layer D1 can be designed according to the capacitance value of the capacitor. The capacitance value of the capacitor is proportional to the area of ​​the first electrode and the second electrode of the capacitor, and inversely proportional to the distance between the first electrode and the second electrode of the capacitor.

[0100] For example, the thickness of the first insulating layer D1 is greater than 0.1 micrometers, for example, may be in the range of 0.1 micrometers to 0.12 micrometers.

[0101] Exemplarily, the second insulating layer D2 can be, for example, SiNx, SiNx, and is deposited by a standard process such as plasma enhanced chemical vapor deposition (PECVD). The thickness of the second insulating layer is greater than 0.2 microns, for example, it can be in the range of 0.2 microns to 0.4 microns. By setting the thickness of the second insulating layer, the influence of the electrode conductive part on the capacitance value is avoided. For example, when the thickness of the second insulating layer is thin, the electrode conductive part will affect the first electrode of the capacitor, thereby causing a large difference between the actual capacitance value and the theoretical capacitance value.

[0102] In some embodiments of the present disclosure, the thickness of the third insulating layer D3 is greater than the thickness of the second insulating layer D2 and the thickness of the first insulating layer D1. This ensures that the conductive layers above and below the third insulating layer overlap effectively, preventing interference between traces. For example, the thickness of the third insulating layer is set within a range of 3 to 5 microns.

[0103] The third insulating layer D3 includes a photosensitive organic insulating material and can be patterned, exposed, developed, and other processes to form the second via hole vh2 .

[0104] Illustratively, the third insulating layer may be made of polyimide (PI) material.

[0105] In some embodiments of the present disclosure, the first via hole vh1 is formed by a dry etching process, and the second via hole vh2 is formed by a photolithography process.

[0106] By forming the first via hole through dry etching, it is possible to ensure that the first via hole has a smaller size, thereby meeting the requirements for manufacturing a filter with miniaturized capacitance.

[0107] Exemplarily, the aperture of the first via hole is greater than or equal to 3 microns, and the aperture of the second via hole is greater than or equal to 15 microns. For example, the aperture of the first via hole is in the range of 3 microns to 5 microns, and the aperture of the second via hole is in the range of 15 to 25 microns.

[0108] As shown in FIG. 2A , the inductor of the filter 100 includes a first conductive end and a second conductive end.

[0109] The first conductive end includes a first conductive portion E1 , a second conductive portion E2 , and a third conductive portion E3 .

[0110] The first conductive portion E1 is located on the same layer as the first electrode C1 and is electrically connected to the first electrode C1. The second conductive portion E2 is disposed on a side of the third insulating layer D3 away from the base substrate BA and is electrically connected to the first conductive portion E1 via a first connecting via vh3 provided in the third insulating layer D3. The third conductive portion E3 is disposed on a side of the base substrate BA closer to the second surface S2 and is electrically connected to the first conductive portion E1 via a first substrate via vh5 provided in the base substrate BA.

[0111] The second conductive end includes a fourth conductive portion E4, a fifth conductive portion E5, and a sixth conductive portion E6.

[0112] The fourth conductive portion E4 is provided on the same layer as the second conductive portion E2 and the electrode conductive portion DE1. The fifth conductive portion E5 is provided on the same layer as the third conductive portion E3 and is electrically connected to the fourth conductive portion E4 via a second substrate via vh6 provided on the base substrate BA and a second connection via vh4 provided on the third insulating layer D3. The sixth conductive portion E6 is provided between the fourth conductive portion E4 and the fifth conductive portion E6 and is provided on the same layer as the first electrode C1 and the first conductive portion E1.

[0113] For example, the first conductive portion E1, the sixth conductive portion E6, and the first electrode C1 are located in the same layer and are formed using the same manufacturing process. For example, a metal layer is deposited on the first surface of the substrate and electroplated to form the metal layer where the first conductive portion, the sixth conductive portion, and the first electrode are located. Then, photoresist is applied, exposed, developed, the photoresist is removed, and etching is performed to form the first conductive portion, the sixth conductive portion, and the first electrode.

[0114] The second conductive portion E2, the fourth conductive portion E4, and the electrode conductive portion DE1 are located in the same layer and are formed using the same manufacturing process. For example, a metal layer is deposited on the side of the third insulating layer away from the base substrate and electroplated to form the metal layer containing the second conductive portion, the fourth conductive portion, and the electrode conductive portion. Then, photoresist is applied, exposed, developed, the photoresist is removed, and etching is performed to form the second conductive portion, the fourth conductive portion, and the electrode conductive portion.

[0115] The third conductive portion E3 and the fifth conductive portion E5 are located in the same layer and are manufactured using the same manufacturing process.

[0116] A first substrate via vh5 is provided on the base substrate BA to electrically connect the first conductive portion E1 and the third conductive portion E3 , and a second substrate via vh6 is provided on the base substrate BA to electrically connect the fifth conductive portion E5 and the sixth conductive portion E6 .

[0117] The third insulating layer D3 is provided with a first connection via vh3 to electrically connect the first conductive portion E1 with the second conductive portion E2 , and the third insulating layer D3 is provided with a second connection via vh4 to electrically connect the fourth conductive portion E4 with the sixth conductive portion E6 .

[0118] In this embodiment, a 3D coil structure of the inductor is formed by electrically connecting the third conductive part and the fifth conductive part, electrically connecting the first conductive part and the sixth conductive part, and electrically connecting the second conductive part and the fourth conductive part, and by providing a first connecting via, a second connecting via, a first substrate via, and a second substrate via.

[0119] In this embodiment, as shown in Figure 2A, the radial cross-sectional areas of the first substrate via vh5 and the second substrate via vh6 gradually increase from the center of the thickness of the substrate toward the first surface S1 or the second surface S2. The step difference between the inner walls of the first substrate via vh5 and the second substrate via vh6 is less than 0.1 microns. In other words, the first substrate via vh5 and the second substrate via vh6 have the same shape and exhibit a trumpet-shaped structure when viewed from the center of the thickness toward the first surface or from the center of the thickness toward the second surface.

[0120] In this embodiment, the first substrate via vh5 and the second substrate via vh6 are fabricated using laser-induced etching, for example, with apertures ranging from 50 to 80 microns. Laser-induced etching can achieve smooth inner walls with minimal roughness. For example, the step difference between the inner walls of the first and second substrate vias is less than 0.1 micron. This facilitates the formation of an adhesion layer within the first and second substrate vias, thereby improving the bonding strength between the adhesion layer and the underlying first conductive layer, thereby enhancing the reliability of the conductive structures within the first and second substrate vias.

[0121] The first substrate via hole vh5 and the second substrate via hole vh6 are filled with a conductive material DM, and the conductive material DM includes an adhesive layer, a first conductive layer, and a second conductive layer sequentially arranged from the inner wall of the via hole toward the central axis of the via hole.

[0122] For example, the adhesion layer may be a film layer comprising a metal such as Ti, Ta, W, TiN, or TaN formed by sputtering deposition, with a thickness ranging from 10 nanometers to 300 nanometers. The first conductive layer may be a Cu seed layer formed on the adhesion layer by sputtering deposition, with a thickness ranging from 30 nanometers to 1000 nanometers. The third conductive layer may be a film layer comprising Cu formed by electroplating, for example.

[0123] As shown in Figure 2A, the filter further includes: a first protective layer B1, a connecting pad, and a second protective layer B2. The connecting pad of the embodiment of the present disclosure will be described in detail with reference to Figures 1 and 2A.

[0124] Connecting pads are provided on the side of the first protective layer B1 away from the base substrate BA, including a first connecting pad P1, a second connecting pad P2, and a third connecting pad P3. The first protective layer B1 is provided on the side of the second conductive portion E2, the fourth conductive portion E4, and the electrode conductive portion DE1 away from the base substrate BA. The first connecting pad P1 is electrically connected to the electrode conductive portion DE1, the second connecting pad P2 is electrically connected to the second conductive portion E2, and the third pad P3 is electrically connected to the fourth conductive portion E4. The second protective layer B2 is provided on the side of the third conductive portion E3 and the fifth conductive portion E5 away from the base substrate.

[0125] The connecting pads are used to connect the first electrode and the second electrode of the filter capacitor, the first conductive end and the second conductive end of the filter inductor to an external circuit, thereby realizing the filtering function of the filter.

[0126] In this embodiment, the first protective layer B1 and the second protective layer B2 can be manufactured using the same process, such as polyimide or acrylic materials, to protect the traces near the substrate. The thickness of the first protective layer and the second protective layer is set to be within the range of 5 microns to 10 microns.

[0127] In some specific embodiments, the second protective layer is, for example, a photosensitive organic material.

[0128] FIG. 3 is a schematic top view of an inductor of the filter in the embodiment of FIG. 2A .

[0129] As shown in FIG3 , the filter of this embodiment has a 3D structure.

[0130] As shown in Figure 3, the first conductive end of the inductor is electrically connected to the second connecting pad P2, the second conductive end of the inductor is electrically connected to the third connecting pad P3, and a spiral 3D coil structure is provided between the first conductive end and the second conductive end, which is formed by the part electrically connecting the third conductive part E3 and the fifth conductive part E5, the part connecting the first conductive part E1 and the sixth conductive part E6, and the part connecting the second conductive part E2 and the fourth conductive part E4.

[0131] FIG4 is a schematic structural diagram of a filter according to another exemplary embodiment of the present disclosure.

[0132] In this embodiment, the inductor of the filter includes a 2D coil structure.

[0133] The filter 100' shown in Figure 4 further includes a fourth insulating layer D4. The fourth insulating layer D4 is disposed on a side of the electrode conductive portion DE1 away from the base substrate BA. The inductor of the filter 100' includes a first conductive end and a second conductive end.

[0134] For example, the material of the fourth insulating layer D4 may include BL-301.

[0135] The first conductive end includes a first conductive portion E1 , a second conductive portion E2 , and a third conductive portion E3 .

[0136] The first conductive portion E1 is located on the same layer as the first electrode C1 and is electrically connected to the first electrode C1. The second conductive portion E2 is disposed on a side of the third insulating layer D3 away from the base substrate BA and is electrically connected to the first conductive portion E1 via a first connecting via vh3 provided in the third insulating layer D3. The third conductive portion E3 is disposed on a side of the second conductive portion E2 away from the base substrate BA and is electrically connected to the second conductive portion E2 via a first conductive via vh7 provided in the fourth insulating layer D4.

[0137] The second conductive end includes a fourth conductive portion E4 and a fifth conductive portion E5.

[0138] The fourth conductive portion E4 is provided on the same layer as the second conductive portion E5 and the electrode conductive portion DE1. The fifth conductive portion E5 is provided on the same layer as the third conductive portion E3 and is electrically connected to the fourth conductive portion E4 via a second conductive via vh8 provided on the fourth insulating layer D4.

[0139] In this embodiment, the first conductive portion E1 and the first electrode C1 are located in the same layer and are manufactured using the same manufacturing process. The second conductive portion E2, the fourth conductive portion E4 and the electrode conductive portion DE1 are manufactured using the same manufacturing process.

[0140] In this embodiment, a pad conductive portion DE2 is further provided on the side of the electrode conductive portion DE1 away from the base substrate BA. The pad conductive portion DE2 is used to electrically connect the electrode conductive portion DE1 to the first pad P1. The third conductive portion E3, the fifth conductive portion E5, and the pad conductive portion DE2 are formed using the same manufacturing process.

[0141] In this embodiment, the filter further includes a first protective layer B1. The first protective layer B1 is disposed on a side of the third conductive portion E3, the fifth conductive portion 35, and the pad conductive portion DE2 that is further away from the base substrate BA. In this embodiment, the pad conductive portion DE2 is further away from the base substrate than the electrode conductive portion DE1.

[0142] The first protective layer BA is used to protect the traces near the substrate, preventing water and oxygen from corroding the traces formed on the first surface of the substrate. It also facilitates patterning and exposure of openings after the traces are formed, thereby exposing a portion of the traces for electrical connection to the connection pads. In this embodiment, the first protective layer can be made of, for example, a photosensitive organic material.

[0143] As shown in Figures 1 and 4, in this embodiment, the connection pads are provided on a side of the first protective layer away from the base substrate, and include a first connection pad P1, a second connection pad P2, and a third connection pad P3. The first connection pad P1 is electrically connected to the electrode conductive portion DE1. Specifically, the first connection pad P1 is electrically connected to the electrode conductive portion DE1 via the pad conductive portion DE2. The second connection pad P2 is electrically connected to the third conductive portion E3, and the third connection pad P3 is electrically connected to the fifth conductive portion E5. The connection pads are used to connect the first and second electrodes of the filter capacitor and the first and second conductive ends of the filter inductor to an external circuit, thereby realizing the filtering function of the filter.

[0144] FIG. 5 is a schematic top view of an inductor of the filter in the embodiment of FIG. 4 .

[0145] As shown in FIG5 and FIG4, the 2D structure coil of the inductance of the filter includes a first part consisting of a first conductive part E1 and a second part consisting of a second conductive part E2 and a fourth conductive part E4 electrically connected, thereby forming a coil structure that can achieve the inductance effect.

[0146] In some embodiments of the present disclosure, at least one of the first electrode, the electrode conductive portion, the first conductive portion, the second conductive portion, the third conductive portion, the fourth conductive portion, and the fifth conductive portion includes a first conductive structure.

[0147] The first conductive structure includes: a first metal layer close to the base substrate, a second metal layer far from the base substrate, and a third metal layer located between the first metal layer and the second metal layer.

[0148] For example, the first metal layer is a film layer comprising one of Ti, Ta, W, TiN, and TaN. The first metal layer can be deposited, for example, by a magnetron sputtering process. The thickness of the first metal layer is, for example, in a range of 0.03 microns to 0.05 microns. For example, the first metal layer is Ti.

[0149] The second metal layer may be a film layer deposited by magnetron sputtering. The thickness of the second metal layer may be, for example, in the range of 0.03 microns to 0.05 microns. The material of the second metal layer is different from that of the first metal layer. For example, the material of the second metal layer includes Cu.

[0150] The third metal layer can be, for example, a film layer formed by an electroplating process. The third metal layer can be made of the same material as the second metal layer, for example, the material of the third metal layer includes Cu. The thickness of the third metal layer can be adjusted according to actual needs, for example, the thickness of the third metal layer is 1 micron to 10 microns.

[0151] The third metal layer and the second metal layer are made of the same metal material, and the grain size of the third metal layer is smaller than that of the second metal layer.

[0152] In an embodiment of the present disclosure, when the third metal layer and the second metal layer use the same metal material and adopt different manufacturing processes, in order to ensure good adhesion between the second metal layer and the first metal layer, the grain size of the second metal layer is smaller than the grain size of the third metal layer, thereby ensuring better adhesion.

[0153] For example, the second metal layer and the third metal layer are both made of Cu, the grain size of the second metal layer is less than 100 microns, and the grain size of the third metal layer is greater than 1000 microns.

[0154] In an embodiment of the present disclosure, the second electrode includes a second conductive structure. The second conductive structure includes: a fourth metal layer proximal to the substrate, a fifth metal layer distal to the substrate, and a sixth metal layer located between the fourth and fifth metal layers. For example, the fourth and fifth metal layers may be made of the same material.

[0155] For example, the fourth and fifth metal layers are made of Ti, and the sixth metal layer is made of Cu. The thicknesses of the fourth, fifth, and sixth metal layers can be adjusted according to actual needs. For example, the thickness of the fourth metal layer is 0.03 to 0.05 microns, the thickness of the fifth metal layer is 0.02 to 0.05 microns, and the thickness of the sixth metal layer is 0.2 to 0.5 microns.

[0156] In some embodiments of the present disclosure, the base substrate includes a glass substrate or a high-resistance silicon substrate.

[0157] In some embodiments of the present disclosure, the connection pad may be, for example, a contact point formed by implanting a solder ball into a via hole in the first protective layer, thereby achieving a contact-type electrical connection with an external circuit.

[0158] In another aspect of the present disclosure, a method for manufacturing a filter is provided, comprising:

[0159] Operation S1: providing a substrate, comprising a first surface and a second surface disposed opposite to each other along a thickness direction;

[0160] Operation S2: forming a capacitor, including forming a first electrode on the first surface and forming a second electrode on a side of the first electrode away from the substrate, with a first insulating layer formed between the first electrode and the second electrode;

[0161] Operation S3: forming a second insulating layer, wherein the second insulating layer is formed on a side of the second electrode away from the base substrate, and a first via hole is formed in the second insulating layer;

[0162] Operation S4: forming an inductor, including forming a first conductive end and a second conductive end, wherein the first conductive end and the second conductive end are electrically connected to form a coil structure of the inductor;

[0163] Operation S5: forming a third insulating layer, forming the third insulating layer on a side of the second insulating layer away from the base substrate, wherein a second via hole is formed in the third insulating layer;

[0164] Operation S6: forming an electrode conductive portion, forming an electrode conductive portion on a side of the third insulating layer away from the base substrate, the electrode conductive portion being electrically connected to the second electrode through the first via and the second via; a radial cross-sectional area of ​​the first via is smaller than a radial cross-sectional area of ​​the second via, and an orthographic projection of the first via on the base substrate overlaps with an orthographic projection of the second via on the substrate.

[0165] 6A to 6M are detailed process flow charts of manufacturing the filter of the exemplary embodiment of FIG. 2 of the present disclosure.

[0166] The following describes in detail the process of forming a 3D IPD filter on a glass substrate with reference to FIG. 6A to FIG. 6M .

[0167] In operation S100 , a base substrate BA is provided.

[0168] As shown in FIG6A , the base substrate BA is a glass substrate. The base substrate includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction. In other optional embodiments, the base substrate may also be made of other suitable materials.

[0169] In operation S101 , a first substrate via hole vh5 and a second substrate via hole vh6 are formed on the base substrate BA, penetrating the dielectric substrate 1 in a thickness direction of the base substrate.

[0170] Specifically, as shown in FIG6B , a variety of methods can be used to produce the first substrate via vh5 and the second substrate via vh6 on the base substrate. For example: sandblasting method, photosensitive glass method, focused discharge method, plasma etching method, laser ablation method, electrochemical method, laser induced etching method, etc. Different methods have different advantages and disadvantages and scope of application. For example, for the sandblasting method, its advantage is that the process is simple, and the aperture of the first connecting via made by this method is larger, and it is only suitable for the production of the first substrate via and the second substrate via with an aperture greater than 200 microns. The advantage of the photosensitive glass method is that the process is simple, and high-density, high-aspect ratio first substrate vias and second substrate vias can be produced. The advantage of the focused discharge method is that the hole-forming speed is fast. The side wall roughness of the first substrate via and the second substrate via prepared by the plasma etching method is small. The advantage of the laser ablation method is that it can produce high-density, high-aspect-ratio first substrate vias and second substrate vias. However, due to the thermal effect of the laser, the inner wall of the cylindrical hole is relatively rough, which will affect the deposition of the film layer in the hole and its bonding with the hole wall, and is not conducive to the formation of a high-density adhesion layer (Ti, Ta, W, TiN, TaN) and a seed layer Cu. The advantages of the electrochemical method are low cost, simple equipment, fast hole-forming rate, and larger diameters of the first substrate via and the second substrate via. The advantage of the laser-induced etching method is that it has a fast hole-forming rate and can produce high-density, high-aspect-ratio first substrate vias and second substrate vias without damage to the inside of the through-hole. The disadvantage is that the laser equipment is expensive.

[0171] In the embodiment of the present disclosure, for example, laser-induced etching can be used to produce TGV through-holes, and the through-hole diameter can range from 50 microns to 80 microns. Specifically, when using the laser-induced etching method to produce a post-through hole on the back side, a laser is first used to laser-induced modify the molecular bonds at the locations where the first substrate via hole and the second substrate via hole are to be produced, and then etching is performed using an etching solution. The etching rate of the laser-modified glass increases, forming a through-hole. The through-hole obtained by the laser-induced etching method has a smooth inner wall, which helps to bond the adhesion layer and seed layer to the side wall of the through-hole and enhances reliability. Since the post-through hole can only be produced using a single-sided etching method, the resulting hole can only be an inverted tapered hole, that is, the radial cross-sectional area of ​​the first substrate via hole and the second substrate via hole gradually increases from the thickness center of the substrate toward the first surface or the second surface. Furthermore, the step difference between the inner wall of the first substrate via hole and the second substrate via hole is less than 0.1 micron, thereby ensuring the smooth effect of the inner wall of the through-hole and facilitating the bonding of the adhesion layer and seed layer to the side wall of the through-hole.

[0172] In operation S102 , a conductive material DM is formed within the first and second substrate via holes vh5 and vh6 .

[0173] As shown in Figure 6C, a conductive material is formed in the first substrate via hole to electrically connect the first conductive portion with the third conductive portion, and a conductive material is formed in the second substrate via hole to electrically connect the sixth conductive portion with the fifth conductive portion.

[0174] For example, an adhesion layer is formed by, but not limited to, magnetron sputtering, and then a first conductive layer is formed on the adhesion layer by sputtering. The first conductive layer is used as a seed layer and electroplated to form a conductive material in the first substrate via hole and the second substrate via hole. After the electroplating is completed, excess electroplated copper on the first surface S1 and the second surface S2 is removed by chemical mechanical polishing (CMP) or grinding, thereby forming a conductive material filling the first substrate via hole and the second substrate via hole.

[0175] In operation S103 , a third conductive portion E3 and a fifth conductive portion E5 are formed on the second surface S2 of the base substrate BA.

[0176] In this embodiment, as shown in FIG6D , the third conductive portion E3 and the fifth conductive portion E5 are manufactured using the same process. For example, the third conductive portion E3 and the fifth conductive portion E5 are part of a 3D inductor structure and simultaneously serve to connect the first substrate via vh5 and the second substrate via vh6. They can be manufactured using a subtractive process, wherein a Cu seed layer is first sputtered, followed by electroplating of Cu with a thickness greater than 5 microns across the entire surface, and then patterning is performed to form the third and fifth conductive portions.

[0177] In operation S104 , a second protective layer B2 is formed.

[0178] 6E , a second protective layer B2 may be formed by spin coating on the side of the third conductive portion E3 and the fifth conductive portion 35 away from the substrate. Materials for the second protective layer include, but are not limited to, polyimide, acrylic, and the like.

[0179] In operation S105 , a first electrode C1 of the capacitor, a first conductive portion E1 of the inductor, and a sixth conductive portion E6 are formed on the first surface S1 of the base substrate BA.

[0180] As shown in FIG6F , the first electrode, the first conductive portion, and the sixth conductive portion can be manufactured using the same manufacturing process, for example. The first electrode, the first conductive portion, and the sixth conductive portion are formed on the first surface of the base substrate.

[0181] Specifically, a first metal layer is deposited on the entire surface of the first surface of the substrate. The material of the first metal layer can be titanium (Ti), and the thickness of the first metal layer ranges from 0.03 microns to 0.05 microns. A second metal layer is formed on the side of the first metal layer away from the substrate. The material of the second metal layer can be copper, and the thickness of the second metal layer ranges from 0.3 microns to 0.5 microns. A third metal layer, such as a copper layer, is formed on the side of the second metal layer away from the substrate by electroplating. The copper layer has a thickness range of 2 microns to 4 microns. The photoresist is then spin-coated and exposed using a corresponding mask. The photoresist irradiated with ultraviolet light is denatured. The photoresist irradiated with ultraviolet light is denatured, and then developed. The denatured photoresist is developed and removed, and a copper etching solution is used to etch away the copper in the area not protected by the photoresist. The patterning is completed, and finally the first electrode, the first conductive portion, and the sixth conductive portion are formed.

[0182] The layer where the first electrode, the first conductive portion and the sixth conductive portion are located is very critical in the entire device, and therefore has high requirements for flatness, for example, a surface roughness Ra of less than 0.01 micrometer.

[0183] In operation S106 , a first insulating layer D1 is formed on a side of the first electrode C1 away from the base substrate BA.

[0184] As shown in FIG. 6G , the first insulating layer D1 is an insulating layer between the first electrode C1 and the second electrode C2 .

[0185] In this embodiment, the first insulating layer of the MIM capacitor is formed using materials including, but not limited to, silicon nitride (SiNx). Standard processes such as plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit a high-flatness SiNx film of 0.1 to 0.12 microns to form the first insulating layer of the MIM capacitor, ensuring capacitance uniformity. The first insulating layer is patterned, and dry etching is used to remove excess SiNx to form the final dielectric layer of the capacitor.

[0186] In operation S107 , a second electrode C2 of the capacitor is formed on a side of the first insulating layer D1 away from the base substrate BA.

[0187] As shown in FIG. 6H , the second electrode C2 of the capacitor may be formed by magnetron sputtering.

[0188] For example, a fourth metal layer, such as Ti, with a thickness of 0.03 to 0.05 microns is deposited on the side of the first insulating layer away from the substrate by magnetron sputtering. Then, a sixth metal layer, such as Cu, with a thickness of 0.2 to 0.5 microns is formed on the side of the fourth metal layer away from the substrate. Finally, a fifth metal layer, such as Ti, with a thickness of 0.02 to 0.05 microns is formed on the side of the sixth metal layer away from the substrate.

[0189] In operation S108 , a second insulating layer D2 is formed on a side of the second electrode C2 away from the base substrate.

[0190] For example, as shown in FIG6I , a highly flat SiNx film with a thickness of 0.2 to 0.4 microns is deposited on the second electrode using a standard process such as plasma-enhanced chemical vapor deposition (PECVD) to form a second insulating layer. In this embodiment, to ensure product manufacturing quality, the flatness of the second insulating layer meets the following requirements, such as a surface roughness Ra of less than 0.01 microns. The second insulating layer is patterned, and excess SiNx is removed using dry etching to form the final second insulating layer. This also includes forming the first via hole vh1 in the second insulating layer by dry etching.

[0191] In an optional embodiment, when the Xingheng first via hole is dry-etched, the size of the first via hole is, for example, in the range of 3 microns to 5 microns. In other optional embodiments, the size of the first via hole may be, for example, larger than 5 microns.

[0192] In operation S109 , a third insulating layer D3 is formed on a side of the second insulating layer D2 away from the base substrate BA.

[0193] As shown in FIG6J , the thickness of the third insulating layer D3, which may be, for example, polyimide, is 3 to 5 microns. The formed third insulating layer is exposed, developed, and etched to form the second via hole vh2. To prevent the third insulating layer from remaining in the second via hole, the size of the second via hole is greater than or equal to 15 microns, thereby ensuring a good effect of the second via hole.

[0194] In an embodiment of the present disclosure, a radial cross-sectional area of ​​the first via hole vh1 is smaller than a radial cross-sectional area of ​​the second via hole ch2 , and an orthographic projection of the first via hole vh1 on the base substrate overlaps with an orthographic projection of the second via hole vh2 on the base substrate.

[0195] As shown in Figure 6J, while forming the second via vh2, it also includes forming a first connecting via vh3 and a second connecting via vh4 on the third insulating layer, wherein the first connecting via vh3 is used to electrically connect the first conductive part E1 with the second conductive part E2, and the second connecting via vh4 is used to electrically connect the sixth conductive part E6 with the fourth conductive part E4.

[0196] In operation S110 , an electrode conductive portion DE1 , a second conductive portion E2 , and a fourth conductive portion E4 are formed on a side of the third insulating layer D3 away from the base substrate.

[0197] The electrode conductive portion, the second conductive portion and the fourth conductive portion are located in the same layer and are manufactured using the same process.

[0198] For example, as shown in FIG6K , a method including but not limited to magnetron sputtering is used to deposit a first metal layer on the third insulating layer. The material of the first metal layer can be titanium (Ti), and the thickness of the first metal layer ranges from 0.03 microns to 0.05 microns. A second metal layer is formed on the side of the first metal layer away from the substrate. The material of the second metal layer can be copper, and the thickness of the second metal layer ranges from 0.2 microns to 0.5 microns. A third metal layer, such as a copper layer, is formed on the side of the second metal layer away from the substrate by electroplating. The copper layer has a thickness range of 5 microns to 10 microns. The photoresist is then spin-coated and exposed using a corresponding mask. The photoresist irradiated with ultraviolet light is denatured. The photoresist irradiated with ultraviolet light is denatured, and then developed. The denatured photoresist is developed and removed, and a copper etchant is used to etch away the copper in the area not protected by the photoresist. The patterning is completed, and the electrode conductive portion, the second conductive portion, and the fourth conductive portion are finally formed.

[0199] In operation S111 , a first protection layer B1 is formed on a side of the electrode conductive portion DE1 , the second conductive portion E2 , and the fourth conductive portion E4 away from the base substrate BA.

[0200] As shown in FIG6L , the first protective layer B1 is made of a photosensitive organic material, such as polyimide, and has a thickness of 5 to 10 microns. After forming the first protective layer, an opening is formed on the first protective layer to expose the electrode conductive portion, the second conductive portion, and the fourth conductive portion.

[0201] In operation S112 , a connection pad is formed on a side of the first protection layer B1 away from the base substrate.

[0202] As shown in Figure 6M, the connecting pads can be, for example, transplanted solder balls, and the connecting pads include a first connecting pad P1, a second connecting pad P2 and a third connecting pad P3. The first connecting pad is electrically connected to the electrode conductive part, the second connecting pad is electrically connected to the third conductive part, and the third connecting pad is electrically connected to the fifth conductive part.

[0203] 7A to 7G are top-view flow charts of a second process for preparing an inductor of the filter of the exemplary embodiment of FIG. 2A of the present disclosure.

[0204] As shown in FIG. 7A , a first substrate via hole and a second substrate via hole are formed on the base substrate.

[0205] As shown in FIG. 7B , a third conductive portion E3 and a fifth conductive portion E5 are formed on the second surface S2 of the base substrate.

[0206] As shown in FIG7C , a first electrode C1 of the capacitor, a first conductive portion E1 and a sixth conductive portion E6 are formed on the first surface of the base substrate.

[0207] As shown in FIG. 7D , a second electrode C2 is formed on a side of the first electrode C1 away from the base substrate.

[0208] As shown in FIG. 7E , a second insulating layer D2 is formed on a side of the second electrode C2 away from the base substrate.

[0209] As shown in FIG7F , an electrode conductive portion DE1 , a second conductive portion E2 , and a fourth conductive portion E4 are formed on a side of the second insulating layer D2 away from the base substrate.

[0210] As shown in FIG7G , a first connection pad P1 is formed on the side of the electrode conductive portion DE1 away from the base substrate, a second connection pad P2 is formed on the side of the second conductive portion E2 away from the base substrate, and a third connection pad P3 is formed on the side of the fourth conductive portion E4 away from the base substrate.

[0211] 7A to 7G are simplified top-down descriptions of the structure to facilitate understanding of the present solution. For detailed processes, see FIG. 6A to FIG. 6M .

[0212] 8A to 8K are flowcharts of a process for preparing the filter of the exemplary embodiment of FIG. 4 of the present disclosure.

[0213] The following describes in detail the process of forming a 2D IPD filter on a glass substrate with reference to FIG. 8A to FIG. 8K .

[0214] In operation S200 , a base substrate BA is provided.

[0215] As shown in FIG8A , the base substrate BA is a glass substrate. The base substrate includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction. In other optional embodiments, the base substrate may also be made of other suitable materials.

[0216] In operation S201 , a first electrode C1 of a capacitor and a first conductive portion E1 of an inductor are formed on a first surface of the base substrate BA.

[0217] As shown in FIG8B , the first electrode C1 and the first conductive portion E1 can be manufactured using the same manufacturing process, for example. The first electrode and the first conductive portion are formed on the first surface of the base substrate.

[0218] Specifically, a first metal layer is deposited on the entire surface of the first surface of the substrate. The material of the first metal layer can be titanium (Ti), and the thickness of the first metal layer ranges from 0.03 microns to 0.05 microns. A second metal layer is formed on the side of the first metal layer away from the substrate. The material of the second metal layer can be copper, and the thickness of the second metal layer ranges from 0.3 microns to 0.5 microns; a third metal layer, such as a copper layer, is formed on the side of the second metal layer away from the substrate by electroplating. The copper layer has a thickness range of 2 microns to 4 microns. The photoresist is continuously spin-coated and exposed using a corresponding mask. The photoresist irradiated with ultraviolet light is denatured, and then developed. The denatured photoresist is developed and removed, and a copper etching solution is used to etch away the copper in the area not protected by the photoresist. The patterning is completed, and finally the first electrode and the first conductive portion are formed.

[0219] The layer where the first electrode and the first conductive portion are located is very critical in the entire device, and therefore has high requirements for flatness, for example, the surface roughness Ra is less than 0.01 micrometer.

[0220] In operation S202 , a first insulating layer D1 is formed on a side of the first electrode C1 away from the base substrate.

[0221] As shown in FIG. 8C , the first insulating layer D1 is an insulating layer between the first electrode C1 and the second electrode C2 .

[0222] In this embodiment, the first insulating layer of the MIM capacitor is formed using materials including, but not limited to, silicon nitride (SiNx). Standard processes such as plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit a high-flatness SiNx film of 0.1 to 0.12 microns to form the first insulating layer of the MIM capacitor, ensuring capacitance uniformity. The first insulating layer is patterned, and dry etching is used to remove excess SiNx to form the final dielectric layer of the capacitor.

[0223] In operation S203 , a second electrode C2 of the capacitor is formed on a side of the first insulating layer D1 away from the substrate.

[0224] As shown in FIG8D , the second electrode of the capacitor may be formed by magnetron sputtering.

[0225] For example, a fourth metal layer, such as Ti, with a thickness of 0.03 to 0.05 microns is deposited on the side of the first insulating layer away from the substrate by magnetron sputtering. Then, a sixth metal layer, such as Cu, with a thickness of 0.2 to 0.5 microns is formed on the side of the fourth metal layer away from the substrate. Finally, a fifth metal layer, such as Ti, with a thickness of 0.02 to 0.05 microns is formed on the side of the sixth metal layer away from the substrate.

[0226] In operation S204 , a second insulating layer D2 is formed on a side of the second electrode C2 away from the base substrate.

[0227] For example, as shown in Figure 8E , a highly flat SiNx film with a thickness of 0.2 to 0.4 microns is deposited on the second electrode using a standard process such as plasma-enhanced chemical vapor deposition (PECVD) to form a second insulating layer. In this embodiment, to ensure product manufacturing quality, the flatness of the second insulating layer meets the following requirements, such as a surface roughness Ra of less than 0.01 microns. The second insulating layer is patterned, and excess SiNx is removed using dry etching to form the final second insulating layer. This also includes forming the first via hole vh1 in the second insulating layer by dry etching.

[0228] In an optional embodiment, when the Xingheng first via hole is dry-etched, the size of the first via hole is, for example, in the range of 3 microns to 5 microns. In other optional embodiments, the size of the first via hole may be, for example, larger than 5 microns.

[0229] In operation S205 , a third insulating layer D3 is formed on a side of the second insulating layer D2 away from the base substrate.

[0230] As shown in FIG8F , the thickness of the third insulating layer D3, which may be, for example, polyimide, is 3 to 5 microns. The formed third insulating layer D3 is exposed, developed, and etched to form the second via hole vh2. To prevent the third insulating layer from remaining in the second via hole, the size of the second via hole is greater than or equal to 15 microns, thereby ensuring a good effect of the second via hole.

[0231] In an embodiment of the present disclosure, a radial cross-sectional area of ​​the first via hole is smaller than a radial cross-sectional area of ​​the second via hole, and an orthographic projection of the first via hole on the base substrate overlaps with an orthographic projection of the second via hole on the base substrate.

[0232] As shown in FIG8F , while forming the second via hole vh2 , the process also includes forming a first connecting via hole vh3 on the third insulating layer, wherein the first connecting via hole vh3 is used to electrically connect the first conductive portion E1 with the second conductive portion E2 .

[0233] In operation S206 , an electrode conductive portion DE1 , a second conductive portion E2 , and a fourth conductive portion E4 are formed on a side of the third insulating layer D3 away from the base substrate.

[0234] The electrode conductive portion DE1 , the second conductive portion E2 and the fourth conductive portion E4 are located in the same layer and are manufactured using the same process.

[0235] For example, as shown in FIG8G , a method including but not limited to magnetron sputtering is used. Specifically, a first metal layer is deposited on the third insulating layer. The material of the first metal layer can be titanium (Ti), and the thickness of the first metal layer ranges from 0.03 microns to 0.05 microns. A second metal layer is formed on the side of the first metal layer away from the substrate. The material of the second metal layer can be copper, and the thickness of the second metal layer ranges from 0.2 microns to 0.5 microns. A third metal layer, such as a copper layer, is formed on the side of the second metal layer away from the substrate by electroplating. The copper layer has a thickness range of 5 microns to 10 microns. The photoresist is then spin-coated and exposed using a corresponding mask. The photoresist irradiated with ultraviolet light is denatured. The photoresist irradiated with ultraviolet light is denatured, and then developed. The denatured photoresist is developed and removed, and a copper etchant is used to etch away the copper in the area not protected by the photoresist. The patterning is completed, and the electrode conductive portion, the second conductive portion, and the fourth conductive portion are finally formed.

[0236] In operation S207 , a fourth insulating layer D4 is formed on a side of the electrode conductive portion DE1 , the second conductive portion E2 , and the fourth conductive portion E4 away from the base substrate.

[0237] As shown in Figure 8H, the fourth insulating layer can be made of a material such as BL-301. The fourth insulating layer entirely covers the electrode conductive portion, the second conductive portion, and the fourth conductive portion. The fourth insulating layer is exposed and developed using a photolithography process, thereby forming a first conductive via vh7 and a second conductive via vh8 in the fourth insulating layer. The first conductive via is used to electrically connect the second conductive portion to the third conductive portion. The second conductive via is used to electrically connect the fourth conductive portion to the fifth conductive portion. Furthermore, a via vh9 is included to electrically connect the pad conductive portion DE2 to the electrode conductive portion DE1.

[0238] In operation S208 , a third conductive portion E3 , a fifth conductive portion E5 , and a pad conductive portion DE2 are formed on a side of the fourth insulating layer D4 away from the base substrate.

[0239] As shown in FIG8I , the third conductive portion, the fifth conductive portion, and the pad conductive portion are located in the same layer and are made of the same manufacturing process and materials. For example, a Cu seed layer is first formed by magnetron sputtering, and then Cu is electroplated to form a plating layer with a thickness greater than 5 μm.

[0240] In operation S209 , a first protection layer B1 is formed on a side of the third conductive portion E3 , the fifth conductive portion E5 , and the pad conductive portion DE2 away from the base substrate.

[0241] As shown in FIG8J , the first protective layer is made of a light-sensitive organic material, such as polyimide, and has a thickness of 5 to 10 microns. After the first protective layer is formed, an opening is formed in the first protective layer to expose the pad conductive portion, the third conductive portion, and the fifth conductive portion.

[0242] In operation S210, as shown in Figure 8K, the connecting pads can be, for example, transplanted solder balls, and the connecting pads include a first connecting pad P1, a second connecting pad P2 and a third connecting pad P3. The first connecting pad P1 is electrically connected to the electrode conductive portion DE1 through the pad conductive portion DE2, the second connecting pad P2 is electrically connected to the third conductive portion E3, and the third connecting pad P3 is electrically connected to the fifth conductive portion E5.

[0243] FIG9 is a schematic structural diagram of an electronic device according to an exemplary embodiment of the present disclosure.

[0244] In some embodiments of the present disclosure, as shown in FIG. 9 , an embodiment of the present disclosure further provides an electronic device 200 , which may include the filter 100 described above.

[0245] The beneficial effects that can be achieved by the electronic device in the above embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the above filters, and will not be described in detail here.

[0246] The electronic device may be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0247] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0248] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A filter, wherein, comprising: a substrate, including a first surface and a second surface disposed opposite to each other in the thickness direction; a capacitor, including a first electrode disposed on the first surface and a second electrode disposed on a side of the first electrode away from the substrate, a first insulating layer being disposed between the first electrode and the second electrode; a second insulating layer, disposed on a side of the second electrode away from the substrate, a first via being disposed on the second insulating layer; an inductor, including a first conductive end and a second conductive end, the first conductive end and the second conductive end being electrically connected to form a coil structure of the inductor; a third insulating layer, disposed on a side of the second insulating layer away from the substrate, a second via being disposed on the third insulating layer; an electrode conductive part, disposed on a side of the third insulating layer away from the substrate, the electrode conductive part being electrically connected to the second electrode through the first via and the second via; a radial cross-sectional area of the first via is smaller than a radial cross-sectional area of the second via, and a positive projection of the first via on the substrate overlaps with a positive projection of the second via on the substrate.

2. The filter according to claim 1, wherein, a positive projection of the second electrode on the substrate is located within a positive projection of the first insulating layer on the substrate; a positive projection of the first insulating layer on the substrate is located within a positive projection of the second insulating layer on the substrate; a positive projection of the second insulating layer on the substrate is located within a positive projection of the third insulating layer on the substrate.

3. The filter according to claim 2, wherein, a positive projection of the second electrode on the substrate is located within a positive projection of the first electrode on the substrate, a positive projection of the first insulating layer on the substrate is located within a positive projection of the first electrode on the substrate.

4. The filter according to claim 3, wherein, a positive projection of the first via on the substrate is located within a positive projection of the second electrode on the substrate inside.

5. The filter according to claim 4, wherein, a positive projection of the second electrode on the substrate is located within a positive projection of the second via on the substrate.

6. The filter according to claim 4, wherein, a positive projection of the first via on the substrate is located within a positive projection of the first insulating layer on the substrate, a positive projection of the second via on the substrate is located within a positive projection of the second insulating layer on the substrate.

7. The filter according to claim 6, wherein, a positive projection of the first via on the substrate is located within a positive projection of the second via on the substrate, and a positive projection of the second via on the substrate is located within a positive projection of the first insulating layer on the substrate.

8. The filter according to claim 6, wherein, a positive projection of the first via on the substrate partially overlaps with a positive projection of the second via on the substrate, and a positive projection of the second via on the substrate partially overlaps with a positive projection of the first insulating layer on the substrate.

9. The filter according to any one of claims 1 to 8, wherein, the thickness of the third insulating layer is greater than the thickness of the second insulating layer and the thickness of the first insulating layer.

10. The filter according to claim 8, wherein, the thickness of the third insulating layer is in the range of 3 micrometers to 5 micrometers.

11. The filter according to any one of claims 1 to 8, wherein, the thickness of the first insulating layer is greater than or equal to 0.1 micrometer; the thickness of the second insulating layer is greater than or equal to 0.2 micrometer.

12. The filter according to claim 6, wherein, the aperture diameter of the first via hole is greater than or equal to 3 micrometers.

13. The filter according to claim 6, wherein, the aperture diameter of the second via hole is greater than or equal to 15 micrometers.

14. The filter according to claim 1, wherein, the first via hole is formed by a dry etching process, and the second via hole is formed by a photolithography process.

15. The filter according to claim 1, wherein, the first via hole includes a plurality of them, and the array formed by the orthographic projection of the plurality of first via holes on the substrate is located within the orthographic projection of the second via hole on the substrate.

16. The filter according to claim 1, wherein, the first conductive end includes: a first conductive portion, which is on the same layer as the first electrode and is electrically connected to the first electrode; a second conductive portion, which is disposed on the side of the third insulating layer away from the substrate, and the second conductive portion is electrically connected to the first conductive portion through a first connection via hole provided on the third insulating layer; a third conductive portion, which is disposed on the side of the substrate close to the second surface, and the third conductive portion is electrically connected to the first conductive portion through a first substrate via hole provided on the substrate; the second conductive end includes: a fourth conductive portion, which is on the same layer as the second conductive portion and the electrode conductive portion; a fifth conductive portion, which is on the same layer as the third conductive portion, and the fifth conductive portion is electrically connected to the fourth conductive portion through a second substrate via hole provided on the substrate and a second connection via hole provided on the third insulating layer; a sixth conductive portion, which is disposed between the fourth conductive portion and the fifth conductive portion, and the sixth conductive portion is on the same layer as the first electrode and the first conductive portion.

17. The filter according to claim 16, wherein, the radial cross-sectional areas of the first substrate via hole and the second substrate via hole gradually increase from the thickness center of the substrate towards the first surface or the second surface.

18. The filter according to claim 16, wherein, the step difference of the inner walls of the first substrate via hole and the second substrate via hole is less than 0.1 micrometer.

19. The filter according to claim 18, wherein, the first substrate via hole and the second substrate via hole are filled with a conductive material, and the conductive material includes an adhesion layer, a first conductive layer, and a second conductive layer sequentially arranged from the inner wall of the via hole towards the central axis of the via hole.

20. The filter according to claim 19, wherein, further includes: The first protective layer is disposed on a side of the second conductive portion, the fourth conductive portion, and the electrode conductive portion away from the substrate The connection pads are disposed on a side of the first protective layer away from the substrate, and include a first connection pad, a second connection pad, and a third connection pad. The first connection pad is electrically connected to the electrode conductive portion, and the second connection pad is electrically connected to the second conductive portion, and the third connection pad is electrically connected to the fourth conductive portion; The second protective layer is disposed on a side of the third conductive portion and the fifth conductive portion away from the substrate.

21. The filter according to claim 1, wherein, further comprising: A fourth insulating layer is disposed on a side of the electrode conductive portion away from the substrate; The first conductive end includes: A first conductive portion, which is on the same layer as the first electrode and is electrically connected to the first electrode; A second conductive portion is disposed on a side of the third insulating layer away from the substrate, and the second conductive portion is electrically connected to the first conductive portion through a first connection via provided on the third insulating layer; A third conductive portion is disposed on a side of the second conductive portion away from the substrate, and the third conductive portion is electrically connected to the second conductive portion through a first conductive via provided on the fourth insulating layer; The second conductive end includes: A fourth conductive portion, which is on the same layer as the second conductive portion and the electrode conductive portion; A fifth conductive portion is on the same layer as the third conductive portion, and the fifth conductive portion is electrically connected to the fourth conductive portion through a second conductive via provided on the fourth insulating layer.

22. The filter according to claim 20, wherein, further comprising: A first protective layer is disposed on a side of the third conductive portion, the fifth conductive portion, and the electrode conductive portion away from the substrate; The connection pads are disposed on a side of the first protective layer away from the substrate, and include a first connection pad, a second connection pad, and a third connection pad. The first connection pad is electrically connected to the electrode conductive portion, the second connection pad is electrically connected to the third conductive portion, and the third connection pad is electrically connected to the fifth conductive portion.

23. The filter according to any one of claims 16 to 22, wherein, At least one of the first electrode, the electrode conductive portion, the first conductive portion, the second conductive portion, the third conductive portion, the fourth conductive portion, and the fifth conductive portion includes a first conductive structure; The first conductive structure includes: A first metal layer close to the substrate, A second metal layer away from the substrate, and A third metal layer located between the first metal layer and the second metal layer; The third metal layer and the second metal layer are made of the same metal material, and the grain size of the third metal layer is smaller than the grain size of the second metal layer.

24. The filter according to any one of claims 16 to 22, wherein, The second electrode includes a second conductive structure; The second conductive structure includes: A fourth metal layer close to the substrate, A fifth metal layer away from the substrate, and A sixth metal layer located between the fourth metal layer and the fifth metal layer.

25. The filter according to claim 1, wherein, the substrate includes a glass substrate or a high-resistivity silicon substrate.

26. A manufacturing method of a filter, wherein, it includes: providing a substrate including a first surface and a second surface oppositely arranged along the thickness direction; forming a capacitor, including forming a first electrode on the first surface and forming a second electrode on a side of the first electrode away from the substrate, and forming a first insulating layer between the first electrode and the second electrode; forming a second insulating layer, forming a second insulating layer on a side of the second electrode away from the substrate, and forming a first via hole in the second insulating layer; forming an inductor, including forming a first conductive end and a second conductive end, and electrically connecting the first conductive end and the second conductive end to form a coil structure of the inductor; forming a third insulating layer, forming a third insulating layer on a side of the second insulating layer away from the substrate, and forming a second via hole in the third insulating layer; forming an electrode conductive part, forming an electrode conductive part on a side of the third insulating layer away from the substrate, and electrically connecting the electrode conductive part to the second electrode through the first via hole and the second via hole; a radial cross-sectional area of the first via hole is smaller than a radial cross-sectional area of the second via hole, and a positive projection of the first via hole on the substrate overlaps a positive projection of the second via hole on the substrate.

27. The method according to claim 26, wherein, the first via hole is formed by dry etching, and the second via hole is formed by a photolithography process.

28. An electronic device, wherein, it includes the filter according to any one of claims 1 to 25.

Images