GaN device with uniform electric field

Abstract

An enhanced GaN transistor includes a multi-region field plate (406) that overlaps a gate portion and a barrier offset layer portion. The multi-region field plate includes a section located above a portion of the gate closest to the drain contact and having an increasing height relative to the channel layer and a section located above an edge or transition of the barrier offset layer and having a decreasing height relative to the channel layer, thereby minimizing peak electric fields at corners of the gate and at edges or transitions of the barrier offset layer.

Description

Technical Field

[0001] The present invention relates to the field of group III nitride transistors such as gallium nitride (GaN) transistors. In particular, the present invention relates to GaN transistors having a plurality of insulator-semiconductor interface regions. Background Art

[0002] Gallium nitride (GaN) semiconductor devices are increasingly favored in the field of power semiconductor devices due to their ability to carry large currents and support high voltages. These devices are generally developed for high-power / high-frequency applications. Devices manufactured for such applications are generally based on device structures that exhibit high electron mobility and are known by various names such as heterojunction field effect transistors (HFETs), high electron mobility transistors (HEMTs), modulation-doped field effect transistors (MODFETs), etc.

[0003] GaN HEMT devices include a nitride semiconductor having at least two nitride layers. Different materials formed on the semiconductor or buffer layer result in different bandgaps for each layer. Different materials in adjacent nitride layers also cause polarization, which helps to form a conductive two-dimensional electron gas (2DEG) region near the junction of these two layers, particularly in the layer with a narrower bandgap.

[0004] The nitride layer that causes polarization generally includes an AlGaN barrier layer adjacent to the GaN layer to contain the 2DEG region that enables charge to flow through the device. This barrier layer can be doped or undoped. Since there is a 2DEG region under the gate when the gate bias is zero, nitride devices are inherently normally-on devices, or depletion-mode devices. Devices in which the 2DEG region under the gate is depleted (i.e., eliminated) when the gate bias is zero can be enhancement-mode devices. Enhancement-mode devices are normally-closed devices that provide additional safety and are more easily controlled by a simple and low-cost drive circuit, and thus are more favored. Enhancement-mode devices conduct current only when a positive bias is applied to the gate.

[0005] FIG. 1 shows a cross-sectional view of a conventional enhancement-mode GaN transistor 100 with a single-layer surface passivation insulator (layer) 108, and this transistor is described more fully in U.S. Patent No. 8,076,698, issued to Ueda et al. The device 100 of FIG. 1 includes a substrate 101, which can be made of silicon (Si), silicon carbide (SiC), sapphire, or other materials; a transition layer 102, composed of AlN and AlGaN with a thickness of about 0.1 to about 1.0 μm; a buffer material 103, composed of GaN with a thickness of about 0.5 to about 10 μm; a barrier material 104, composed of AlGaN with a ratio of Al to Ga of about 0.1 to about 0.5 and a thickness of about 0.005 to about 0.03 μm; lightly doped p-type AlGaN 105; heavily doped p-type GaN 106; an isolation region 107; a passivation layer / region 108; ohmic contact metals 109 and 110 for the source and drain, typically composed of Ti and Al with a capping metal such as Ni and Au; and a gate metal 111, typically composed of nickel (Ni) and gold (Au) metal contacts over a p-type GaN gate

[0006] The conventional GaN transistor shown in FIG. 1 has several disadvantages. In most Si devices, the insulator / barrier interface (e.g., FIG. 1) is not a critical parameter, but in GaN transistors, it becomes a key parameter determining device performance. A single-layer surface passivation insulator (e.g., the passivation layer 108 in FIG. 1) can be used to minimize leakage current and gate-drain capacitance, or can be used to achieve a high channel electron density and a low drain field strength, but a single insulating passivation layer cannot achieve both effects simultaneously.

[0007] FIG. 2 shows a cross-sectional view of a prior art GaN transistor device disclosed in U.S. Patent No. 10,096,702, which includes two insulators disposed in parallel between the gate and the drain. The first insulator is disposed between the gate and the drain (close to the gate) to minimize gate leakage and the field strength near the gate that would cause a large gate-drain charge (Qgd). The second insulator is disposed between the first insulator and the drain, and its thickness is reduced compared to the first insulator to minimize the electric field at the drain contact and achieve a high charge density in the channel, thereby reducing the on-resistance. This favorable result is achieved because the net electron donor density above the channel under the thicker first insulator is less than the net electron donor density above the channel under the thinner second insulator, such that the 2DEG density in the channel under the second insulator is greater than the 2DEG density in the channel under the first insulator.

[0008] As shown in FIG. 2, the stepped thickness increase at the transition between the thinner first insulator and the thicker second insulator forms a corner with a higher electric field near the gate, resulting in a problem of a decrease in the breakdown voltage of the device. Accordingly, in order to protect the gate from the influence of a large electric field (including the large electric field at the gate corner), a multi-height metal field plate is provided. The multi-height metal field plate is located above the entire first insulator, but only above a part of the second insulator, and is used to equalize the electric field at the gate corner closest to the drain.

[0009] FIG. 3 is taken from U.S. Patent No. 9,024,324, which shows a prior art GaN transistor having a multi-region field plate 68. The position and shape of the multi-region field plate 68 are defined by one or more pitch parameters including the following parameters: the lateral distance (LPG) between the field plate and the gate edge; the lateral distance (LGD) between the gate edge and the drain structure; and / or the uniform thickness (TGP) between the gate sidewall and the overlying field plate. The multi-region field plate 68 is formed at two different heights of a multi-height insulator stack 63-65 to define a first field plate bottom dimension (LF1) and a second field plate bottom dimension (LF2) at least at the first field plate height (E1) and the second field plate height (E2) that are respectively spaced apart from the underlying substrate, thereby providing a first region of the field plate separated from the substrate by a first distance and a second region of the field plate separated from the substrate by a second distance. The resulting GaN transistor has a smooth shielding transition above the gate, thereby having excellent dynamic Rdson, a smaller gate-drain capacitance (Cgd), a smaller drain-source capacitance (Cds), and a higher breakdown voltage. However, in the GaN transistor of FIG. 3, the multi-region field plate 68 is disposed above a single insulating layer 54 extending under the gate electrode 60, and fails to solve the problem of the large electric field existing at the insulator corner transition (i.e., between the thinner first insulator and the thicker second insulator) in the GaN transistor of FIG. 2 above.

[0010] Therefore, there is a need to provide a GaN transistor having a barrier offset layer (an insulating layer above the barrier layer) and an overlying multi-region field plate to achieve a more uniform electric field at the corner of the barrier offset layer, thereby increasing the breakdown voltage of the device. Summary of the Invention

[0011] In the following various embodiments, the present invention solves the above problems by providing an enhancement-mode GaN transistor including a multi-region field plate that overlaps with the gate portion and overlaps with the barrier offset layer portion. The multi-region field plate includes a section located above the gate portion closest to the drain contact and having a height increasing relative to the channel layer and a section located above the edge or transition of the barrier offset layer and having a height decreasing relative to the channel layer, thereby minimizing the peak electric field at the gate corner and at the edge or transition of the barrier offset layer.

[0012] An additional metal field plate may be provided below and / or above the multi-region field plate. One of the additional field plates may be an ohmic metal contact of the source electrode. Description of the Drawings

[0013] The features, objects, and advantages of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, like reference numerals represent corresponding elements. In the drawings:

[0014] FIG. 1 shows a cross-sectional view of a conventional GaN transistor having a single-layer surface passivation insulator.

[0015] FIG. 2 shows a cross-sectional view of a conventional GaN transistor having two insulators arranged side by side between the gate and the drain and having different thicknesses.

[0016] FIG. 3 shows a cross-sectional view of a conventional GaN transistor having a multi-region field plate.

[0017] Figure 4 FIG. shows a cross-sectional view of a GaN transistor formed according to a first embodiment of the present invention.

[0018] Figure 5 FIG. shows a cross-sectional view of a GaN transistor formed according to a second embodiment of the present invention.

[0019] Figure 6 FIG. shows a cross-sectional view of a GaN transistor formed according to a third embodiment of the present invention.

[0020] Figure 7 FIG. shows a cross-sectional view of a GaN transistor formed according to a fourth embodiment of the present invention.

[0021] Figure 8 FIG. shows a cross-sectional view of a GaN transistor formed according to a fifth embodiment of the present invention. Detailed Description of the Embodiments

[0022] Hereinafter, a detailed description will be given in conjunction with specific embodiments. The following detailed description is only intended to teach those skilled in the art further details for practicing the preferred aspects herein, and is not intended to limit the scope of the claims. Therefore, the combinations of technical features disclosed in the following detailed description may not necessarily be the combinations required for practicing the technical solutions of the present invention in a broad sense, and their purpose is only to specifically describe representative embodiments of the technical solutions of the present invention. It should be understood that other embodiments may be adopted in addition, and various modifications may be made structurally, logically, and electrically.

[0023] Figure 4FIG. 0 shows a cross-sectional view of an enhanced GaN transistor 400 formed according to a first embodiment of the present invention. Above the front barrier layer 404 between the gate and the drain contact, a barrier offset layer (insulator) 402, such as SiN, is provided spaced from the gate. The edge or transition 408 of the barrier offset layer is laterally offset from the gate. The barrier offset layer 402 minimizes the electric field near the drain contact and enables a high charge density (ns) in the underlying channel, thereby achieving a low on-resistance. As Figure 4 shown, the barrier offset layer 402 increases the charge density of the underlying 2DEG, such that the charge amount ns2 below the barrier offset layer 402 is greater than the charge amount ns1 near the gate without the overlying barrier offset layer 402.

[0024] As Figure 4 shown, to address the above-mentioned problem related to the large electric field at the corner or transition of the barrier offset layer 402, the present invention includes a multi-zone metal field plate 406, which protects the gate region from the large electric field and reduces the electric field at the edge or transition 408 of the barrier offset layer 402 near the gate. The multi-zone field plate 406 partially overlaps with the gate and partially overlaps with the barrier offset layer 402. The multi-zone field plate 406 includes a plurality of segments at different heights relative to the barrier layer, including: a minimum height segment (C to B) above the edge or transition 408 of the barrier offset layer 402; a maximum height segment overlapping with the gate; and an intermediate height segment above the portion of the barrier offset layer 402 closest to the drain contact. By combining the barrier offset layer 402 with the multi-zone metal field plate 406, the advantage of making the electric field at the gate corner or at the edge or transition of the barrier offset layer 402 near the gate more uniform can be achieved.

[0025] Figure 5 FIG. 11 shows a second embodiment 500 of the present invention with a multi-zone field plate 506, the multi-zone field plate 506 having two regions, namely Figure 4 in the C to B segment, a step between C to D and D to B. This additional region has a step in height in the field plate 510 above the edge or transition 508 of the barrier offset layer 402, further smoothing the electric field at the edge or transition 508 of the barrier offset layer.

[0026] Figure 6 FIG. 17 shows a third embodiment 600 of the present invention, which has a multi-zone field plate 606 (as in Figure 5 the embodiment) and a stepped field plate 612 supported below and overlapping above the gate. The multi-zone field plate 606 is in Figure 5On the opposite side of the step (i.e., the side closest to the gate), there is a step in height, and this step in height is above the step in height of the underlying field plate 612. By combining the stepped field plate 612 with the stepped multi-region field plate 606, in addition to making the electric field at the edge or transition 508 of the barrier offset layer smoother, it is also used to reduce the electric field at the gate corner near the drain.

[0027] Figure 7 FIG. 700 shows a fourth embodiment 700 of the present invention. Similar to Figure 6 the embodiments, the fourth embodiment 700 has an additional field plate 716 disposed above and overlapping the multi-region field plate 707. The top metal field plate 716 further smoothes the electric field at the edge or transition 708 of the barrier offset layer and reduces this electric field.

[0028] Figure 8 FIG. 800 shows a fifth embodiment 800 of the present invention. This embodiment is similar to Figure 6 the third embodiment 600, but has an additional ohmic metal field plate 818 connected to the source S. The ohmic metal field gate 18 is between the multi-region field plate 806 and the underlying field plate 812, extending over the entire gate and over the entire edge or transition 808 of the barrier offset layer, thereby further reducing the electric field at the gate corner and at the edge or transition 808 of the barrier offset layer.

[0029] The above various embodiments of the present invention preferably employ the above prior art, especially the conventional processes, conventional materials, and parameters described in U.S. Patents Nos. 8,076,698, 10,096,702, and 9,024,324.

[0030] The technical features of any one of the above five embodiments can be combined with the technical features of other embodiments described herein, and such combination methods are also considered to be within the scope and spirit of the present invention.

[0031] The above description and the drawings should be regarded only as an illustration of the specific embodiments capable of achieving the features and advantages described herein. Accordingly, the embodiments of the present invention should not be considered limited to the embodiments described in the above description and the drawings.

[0032] More generally, although the present disclosure and the exemplary embodiments have been described above in connection with various embodiments and with reference to the accompanying drawings, it is to be understood that the present disclosure and the embodiments are not limited thereto. On the contrary, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in a variety of ways, and the resulting modifications do not depart from the scope of the present disclosure. In addition, the terms and descriptions used herein are for illustrative purposes only and are not intended to be limiting. Those skilled in the art should understand that there should also be numerous variations within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents, and that all terms used in the claims and their equivalents should be understood in the broadest possible manner unless otherwise specified.

Claims

1. An enhanced group-III nitride transistor, comprising: A channel including a conductive two-dimensional electron gas (2DEG), which is formed at the connection of the channel layer and the barrier layer in the channel layer; A gate located above the barrier layer, and a drain contact and a source contact, wherein the gate is disposed between the source contact and the drain contact; and A barrier offset layer, the barrier offset layer includes an insulator located above the barrier layer and disposed between the gate and the drain contact, wherein the barrier offset layer has a lateral edge or transition deviating from the gate contact, and the net electron donor density in the channel layer below the barrier offset layer is greater than the net electron donor density in the channel layer closer to the gate without the barrier offset layer, so that the 2DEG density in the channel layer closer to the gate is greater than the 2DEG density in the channel layer below the barrier offset layer; and A multi-region field plate, the multi-region field plate covers and overlaps at least a part of the gate closest to the drain contact, and overlaps with a part of the barrier offset layer, the multi-region field plate has a plurality of sections, including a section located above the part of the gate closest to the drain contact and having an increasing height relative to the channel layer; and a section located above the edge or transition of the barrier offset layer and having a decreasing height relative to the channel layer, Wherein, the multi-region field plate reduces the electric field at the corner of the gate closest to the drain contact and at the edge or transition of the barrier offset layer.

2. The transistor according to claim 1, wherein, The group-III nitride includes GaN.

3. The transistor according to claim 1, wherein, The insulator offset layer includes SiN.

4. The transistor according to claim 1, wherein, The multi-region field plate has a step in height between the gate and the edge or transition of the barrier offset layer to further reduce the electric field at the edge or transition of the barrier offset layer.

5. The transistor according to claim 4, further comprising an additional field plate located below the multi-region field plate and at least partially overlapping with it, the additional field plate includes a step in height, and the multi-region field plate further includes a corresponding step in height located above the additional field plate, whereby, the step in height of the additional field plate and the corresponding step in height of the multi-region field plate are used to reduce the electric field at the corner of the gate closest to the drain contact.

6. The transistor according to claim 5, further comprising another field plate located above the multi-region field plate and at least partially overlapping with it, so as to smooth the electric field at the edge or transition of the barrier offset layer and reduce the electric field.

7. The transistor according to claim 5, further comprising an ohmic metal field plate connected to the source contact, wherein, The ohmic metal field gate extends above the entire gate between the multi-region field plate and the underlying supporting field plate and above the entire gate and the edge or transition of the barrier offset layer to further reduce the electric field at the corner of the gate and at the edge or transition of the barrier offset layer.

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