Fault diagnosis circuit, vibration device, and physical quantity sensor

Abstract

The invention provides a fault diagnosis circuit, a vibration device and a physical quantity sensor, which can reduce the possibility that a circuit generating a reference voltage is misdiagnosed to have a fault even if the reference voltage temporarily changes. The failure diagnosis circuit performs failure diagnosis of the reference voltage generation circuit, monitors the reference voltage supplied from the reference voltage generation circuit to the first circuit, and diagnoses that the reference voltage generation circuit has failed when a state in which the reference voltage is not included in a predetermined range continues for a predetermined time.

Description

Technical Field

[0001] The present invention relates to a fault diagnosis circuit, a vibration device, and a physical quantity sensor. Background Art

[0002] At present, in various systems and electronic devices, physical quantity sensors capable of detecting various physical quantities, such as gyro sensors that detect angular velocity and acceleration sensors that detect acceleration, are widely used. In recent years, for example, in order to construct a system with high reliability such as a system mounted on a vehicle, a physical quantity sensor may be required to have a function of diagnosing its own faults. In addition, in recent years, in order to construct a highly reliable system, a physical quantity sensor that outputs detection information of a physical quantity as digital data with high noise tolerance is used. Generally, such a physical quantity sensor has: a physical quantity detection element; and a physical quantity detection circuit that generates an analog signal corresponding to the detected physical quantity based on a signal output from the physical quantity detection element, and performs digital signal processing after converting it into a digital signal through an analog / digital conversion circuit.

[0003] A power supply monitoring circuit that monitors whether the power supply voltage is within a specified range is described in Patent Document 1. For example, by applying the power supply monitoring circuit described in Patent Document 1, a physical quantity sensor that diagnoses its own faults is realized.

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2021-117072

[0005] However, in a physical quantity sensor to which the power supply monitoring circuit described in Patent Document 1 is applied, when the reference voltage temporarily changes outside the specified range due to the operation of a signal processing circuit that processes a signal output from the physical quantity detection element and an analog / digital conversion circuit that converts the output signal of the signal processing circuit into a digital signal, it may be erroneously determined that a circuit that generates the reference voltage has failed. Summary of the Invention

[0006] One aspect of the fault diagnosis circuit of the present invention is that the fault diagnosis circuit performs fault diagnosis of a reference voltage generation circuit. The fault diagnosis circuit monitors a reference voltage supplied from the reference voltage generation circuit to a first circuit, and diagnoses that the reference voltage generation circuit has failed when the state where the reference voltage is not within a specified range continues for a specified time.

[0007] One aspect of the vibration device of the present invention includes one aspect of the fault diagnosis circuit.

[0008] One aspect of the physical quantity sensor of the present invention includes one aspect of the fault diagnosis circuit. Brief Description of the Drawings

[0009] Figure 1 is a functional block diagram of the physical quantity sensor according to the first embodiment.

[0010] Figure 2 is a diagram showing a structural example of the selection circuit and the analog / digital conversion circuit.

[0011] Figure 3 is a diagram showing an example of the channel structure of the time-division processing of the analog / digital conversion circuit.

[0012] Figure 4 is a diagram showing a structural example of a part of the reference voltage generation circuit and the fault diagnosis circuit in the first embodiment.

[0013] Figure 5 is a diagram showing an example of waveforms of various signals when no fault occurs in the reference voltage generation circuit in the first embodiment.

[0014] Figure 6 is a diagram showing an example of waveforms of various signals when a fault occurs in the reference voltage generation circuit in the first embodiment.

[0015] Figure 7 is a flowchart showing an example of the processing procedure of the fault diagnosis circuit in the first embodiment.

[0016] Figure 8 is a functional block diagram of the physical quantity sensor according to the second embodiment.

[0017] Figure 9 is a diagram showing a structural example of a part of the reference voltage generation circuit and the fault diagnosis circuit in the second embodiment.

[0018] Figure 10 is a diagram showing an example of waveforms of various signals when no fault occurs in the reference voltage generation circuit in the second embodiment.

[0019] Figure 11 is a diagram showing an example of waveforms of various signals when a fault occurs in the reference voltage generation circuit in the second embodiment.

[0020] Figure 12 is a flowchart showing an example of the processing procedure of the fault diagnosis circuit in the second embodiment.

[0021] Reference Numeral Explanation

[0022] 1: Physical quantity sensor; 2: Physical quantity detection circuit; 3: Angular velocity detection element; 4X: Acceleration detection element; 4Y: Acceleration detection element; 10: Angular velocity signal processing circuit; 11: Drive circuit; 12: Detection circuit; 20: Acceleration signal processing circuit; 21: Drive circuit; 22X: Detection circuit; 22Y: Detection circuit; 30: Temperature sensor; 40: Reference voltage generation circuit; 50: Selection circuit; 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n: Low-pass filter; 56: Multiplexer; 60: Analog / digital conversion circuit; 61: Precharge circuit; 62: Programmable gain amplifier; 63: Successive approximation analog / digital converter; 64: SAR control circuit; 70: Digital signal processing circuit; 80: Fault diagnosis circuit; 81: Abnormality determination circuit; 82: Fault diagnosis signal output circuit; 90: Control circuit; 100: Storage unit; 110: Interface circuit; 120: Oscillation circuit; 130: Fault diagnosis circuit; 131: Abnormality determination circuit; 132: Fault diagnosis signal output circuit; 141: Bandgap reference circuit; 142: Resistor; 143: Resistor; 144: Operational amplifier; 145: Bandgap reference circuit; 146: Resistor; 147: Resistor; 148: Operational amplifier; 181: Comparator; 182: Comparator; 183: Logic OR circuit; 184: Counter; 185: Flag mask circuit; 186: D-type flip-flop; 200: Logic circuit; 231: Comparator; 232: Comparator; 233: Logic OR circuit; 234: Counter; 235: Flag mask circuit; 236: D-type flip-flop. Detailed implementation mode

[0023] Hereinafter, preferred implementation modes of the present invention will be described in detail with reference to the drawings. In addition, the implementation modes described below do not unduly limit the content of the present invention described in the claims. Further, not all of the structures described below are necessarily essential components of the present invention.

[0024] Hereinafter, a physical quantity sensor that detects angular velocity and acceleration as physical quantities will be described as an example.

[0025] 1. First implementation mode

[0026] 1-1. Structure of physical quantity sensor

[0027] Figure 1 is a functional block diagram of the physical quantity sensor according to the first implementation mode. The physical quantity sensor 1 according to the first implementation mode includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0028] The acceleration detection elements 4X and 4Y are physical quantity detection elements that detect acceleration as a physical quantity. The acceleration detection element 4X detects the acceleration in the X-axis direction, and the acceleration detection element 4Y detects the acceleration in the Y-axis direction orthogonal to the X-axis. For example, the acceleration detection elements 4X and 4Y can also be elements that have a capacitance configured with drive electrodes and detection electrodes (not shown), the charge amount of the capacitance changes according to the acceleration, and a signal corresponding to the charge amount is output. The acceleration detection elements 4X and 4Y can also be MEMS (Micro Electro Mechanical Systems) elements, for example.

[0029] The angular velocity detection element 3 is a physical quantity detection element that detects angular velocity as a physical quantity. In the present embodiment, the angular velocity detection element 3 detects the angular velocity about the Z-axis orthogonal to the X-axis and the Y-axis. For example, the angular velocity detection element 3 can also be an element that has a vibrating piece configured with drive electrodes and detection electrodes (not shown), the magnitude of the vibration of the vibrating piece changes according to the angular velocity, and a signal corresponding to the magnitude of the vibration is output. The angular velocity detection element 3 can also be an element having a so-called double-T type quartz vibrating piece with two drive vibrating arms of the T type, for example.

[0030] The physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a fault diagnosis circuit 80, a control circuit 90, a storage unit 100, an interface circuit 110, and an oscillation circuit 120. The physical quantity detection circuit 2 can also be implemented by a single-chip integrated circuit, for example. In addition, the physical quantity detection circuit 2 can also be a structure in which some of these elements are omitted or changed, or other elements are added.

[0031] The reference voltage generation circuit 40 generates various reference voltages based on the power supply voltage VDD and the ground voltage VSS supplied from the outside of the physical quantity detection circuit 2. In the present embodiment, the reference voltage generation circuit 40 generates the power supply voltage VGR and the common voltage VCMGR as the reference voltages supplied to the angular velocity signal processing circuit 10. In addition, the reference voltage generation circuit 40 generates the power supply voltage VACC and the common voltage VCMACC as the reference voltages supplied to the acceleration signal processing circuit 20. Further, the reference voltage generation circuit 40 generates the full scale voltage VFSAD and the common voltage VCMAD as the reference voltages supplied to the analog / digital conversion circuit 60. Further, the reference voltage generation circuit 40 generates the power supply voltage VTS and the common voltage VCMTS as the reference voltages supplied to the temperature sensor 30. In addition, the reference voltage generation circuit 40 generates the power supply voltage VLGC as the reference voltage supplied to the logic circuit 200. Further, the reference voltage generation circuit 40 generates the power supply voltage VOSC as the reference voltage supplied to the oscillation circuit 120.

[0032] The oscillation circuit 120 operates based on the power supply voltage VOSC supplied from the reference voltage generation circuit 40 and generates a clock signal MCK. The oscillation circuit 120 can also be configured as, for example, a ring oscillator or a CR oscillation circuit.

[0033] The angular velocity signal processing circuit 10 includes a drive circuit 11 and a detection circuit 12, and operates based on the power supply voltage VGR and the common voltage VCMGR supplied from the reference voltage generation circuit 40.

[0034] The drive circuit 11 generates a drive signal DRVGR for exciting and vibrating the angular velocity detection element 3, and supplies it to the angular velocity detection element 3. For example, the drive signal DRVGR is a rectangular wave signal with the power supply voltage VGR set to a high level and the ground voltage VSS set to a low level. In addition, the drive circuit 11 is input with the oscillation current generated by the exciting vibration of the angular velocity detection element 3, and feedback-controls the amplitude level of the drive signal so that the amplitude of the oscillation current remains fixed. When the angular velocity detection element 3 is applied with an angular velocity about the Z axis in the state of exciting vibration, it detects the angular velocity and outputs a signal corresponding to the angular velocity. In the present embodiment, the signal output from the angular velocity detection element 3 is a differential signal.

[0035] The detection circuit 12 is a detection signal generation circuit that generates a detection signal corresponding to the angular velocity about the Z axis based on the output signal of the angular velocity detection element 3. Specifically, the detection circuit 12 detects the angular velocity component included in the signal output from the angular velocity detection element 3, generates an angular velocity detection signal GRO1 with a voltage level corresponding to the magnitude of the angular velocity component, and outputs it. In addition, the detection circuit 12 detects the vibration leakage component included in the signal output from the angular velocity detection element 3, generates a vibration leakage signal GRO2 with a voltage level corresponding to the magnitude of the vibration leakage component, and outputs it. In the present embodiment, the angular velocity detection signal GRO1 and the vibration leakage signal GRO2 are differential signals with respect to the common voltage VCMGR.

[0036] In this way, the angular velocity signal processing circuit 10 is a physical quantity signal processing circuit that outputs a drive signal DRVGR for driving the angular velocity detection element 3 and generates a detection signal corresponding to the angular velocity about the Z axis, which is one of the physical quantities, based on the output signal of the angular velocity detection element 3.

[0037] The acceleration signal processing circuit 20 includes a drive circuit 21, a detection circuit 22X, and a detection circuit 22Y, and operates based on the power supply voltage VACC and the common voltage VCMACC supplied from the reference voltage generation circuit 40. In addition, the acceleration signal processing circuit 20 is controlled based on n control signals CTL1 to CTLn supplied from the control circuit 90. n is an integer of 1 or more.

[0038] The drive circuit 21 generates a drive signal DRVACC and outputs it to the acceleration detection elements 4X and 4Y to drive the acceleration detection elements 4X and 4Y. For example, the drive signal DRVACC is a rectangular wave signal with the power supply voltage VACC set to a high level and the ground voltage VSS set to a low level. When an acceleration in the X-axis direction is applied in this state, the acceleration detection element 4X detects the acceleration and outputs a signal corresponding to the acceleration. In addition, when an acceleration in the Y-axis direction is applied, the acceleration detection element 4Y detects the acceleration and outputs a signal corresponding to the acceleration. In the present embodiment, the signals output from the acceleration detection elements 4X and 4Y are differential signals.

[0039] The detection circuit 22X is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the X-axis direction based on the output signal of the acceleration detection element 4X. Specifically, the detection circuit 22X detects the acceleration component included in the signal output from the acceleration detection element 4X, generates an X-axis acceleration detection signal AXO with a voltage level corresponding to the magnitude of the acceleration component, and outputs it. In the present embodiment, the X-axis acceleration detection signal AXO is a differential signal with respect to the common voltage VCMACC.

[0040] The detection circuit 22Y is a detection signal generation circuit that generates a detection signal corresponding to the acceleration in the Y-axis direction based on the output signal of the acceleration detection element 4Y. Specifically, the detection circuit 22Y detects the acceleration component included in the signal output from the acceleration detection element 4Y, and generates and outputs a Y-axis acceleration detection signal AYO with a voltage level corresponding to the magnitude of the acceleration component. In the present embodiment, the Y-axis acceleration detection signal AYO is a differential signal with the common voltage VCMACC as a reference.

[0041] In this way, the acceleration signal processing circuit 20 is a physical quantity signal processing circuit that outputs a drive signal DRVACC for driving the acceleration detection elements 4X and 4Y, generates a detection signal corresponding to the acceleration in the X-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4X, and generates a detection signal corresponding to the acceleration in the Y-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4Y.

[0042] The temperature sensor 30 detects the temperature based on the power supply voltage VTS and the common voltage VCMTS supplied from the reference voltage generation circuit 40, and outputs a temperature detection signal TSO with a voltage level corresponding to the temperature. The temperature sensor 30 can also be, for example, a circuit that utilizes the temperature characteristics of a bandgap reference circuit. In the present embodiment, the temperature detection signal TSO is a differential signal with the common voltage VCMTS as a reference.

[0043] The selection circuit 50 selects and outputs any one of the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO according to the selection signal SEL from the control circuit 90. In the present embodiment, the output signal MXO of the selection circuit 50 is a differential signal.

[0044] The analog / digital conversion circuit 60 operates based on the full-scale voltage VFSAD and the common voltage VCMAD supplied from the reference voltage generation circuit 40. The analog / digital conversion circuit 60 converts the analog signal, i.e., the signal MXO, output from the selection circuit 50 into a digital signal ADO and outputs it according to various control signals supplied from the control circuit 90. Specifically, the analog / digital conversion circuit 60 uses the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale, and converts the signal MXO, which is a differential signal, into the digital signal ADO.

[0045] The digital signal processing circuit 70 processes the digital signal ADO output from the analog / digital conversion circuit 60 according to various control signals supplied from the control circuit 90. For example, the digital signal processing circuit 70 outputs a digital signal DSPO that has been digitally filtered and corrected arithmetically from the digital signal ADO.

[0046] The failure diagnosis circuit 80 performs a failure diagnosis of the reference voltage generation circuit 40. Specifically, the failure diagnosis circuit 80 monitors the reference voltage, i.e., the common voltage VCMAD, supplied from the reference voltage generation circuit 40 to the analog / digital conversion circuit 60, and diagnoses that the reference voltage generation circuit 40 has failed when the state where the common voltage VCMAD is not within the specified range continues for a specified time. In addition, the analog / digital conversion circuit 60 is an example of the "first circuit".

[0047] In the present embodiment, the failure diagnosis circuit 80 includes an abnormality determination circuit 81 and a failure diagnosis signal output circuit 82.

[0048] The abnormality determination circuit 81 determines whether the common voltage VCMAD is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may also be a flag signal that becomes high level when the common voltage VCMAD is abnormal and becomes low level when the common voltage VCMAD is normal.

[0049] The failure diagnosis signal output circuit 82 diagnoses whether the reference voltage generation circuit 40 has failed according to the abnormality determination signal FLG1 and outputs a failure diagnosis signal FLG2 indicating the diagnosis result. In the present embodiment, the common voltage VCMAD temporarily changes at least one of the timing when the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50 and the timing when it ends the sampling. Therefore, even if the reference voltage generation circuit 40 has not failed, the abnormality determination circuit 81 may temporarily output the abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal. Therefore, the failure diagnosis signal output circuit 82 diagnoses that the reference voltage generation circuit 40 has failed when the abnormality determination signal FLG1 indicates that the common voltage VCMAD is abnormal for a specified time, so as not to misjudge that the reference voltage generation circuit 40 has failed. For example, the failure diagnosis signal FLG2 may also be a flag signal that becomes high level when the reference voltage generation circuit 40 has failed and becomes low level when the reference voltage generation circuit 40 has not failed.

[0050] The control circuit 90 generates and outputs various control signals, a selection signal SEL, and control signals CTL1 to CTLn for controlling the operations of the analog / digital conversion circuit 60, the digital signal processing circuit 70, etc., and the acceleration signal processing circuit 20.

[0051] The storage unit 100 has a non-volatile memory (not shown), in which various trimming data for the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, etc., and coefficient data for the processing of the digital signal processing circuit 70 are stored. The non-volatile memory can be configured, for example, as a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Also, the storage unit 100 can be configured to have a register (not shown). When the power supply of the physical quantity detection circuit 2 is turned on, i.e., when the voltage of the VDD terminal rises from 0V to a desired voltage, various data stored in the non-volatile memory are transferred to and held in the register, and the various data held in the register are supplied to each circuit.

[0052] The interface circuit 110 processes the output digital signal DSPO and the fault diagnosis signal FLG2 according to requests from external devices. In addition, the interface circuit 110 processes reading and outputting data stored in the non-volatile memory or register of the storage unit 100 and writing data input from external devices to the non-volatile memory or register of the storage unit 100 according to requests from external devices of the physical quantity detection circuit 2. The interface circuit 110 can also be, for example, an interface circuit of an SPI (Serial Peripheral Interface) bus or an I 2 C (Inter-Integrated Circuit) bus.

[0053] The digital signal processing circuit 70, the fault diagnosis signal output circuit 82, the control circuit 90, the storage unit 100, and the interface circuit 110 constitute the logic circuit 200. The logic circuit 200 operates based on the power supply voltage VLGC supplied from the reference voltage generation circuit 40 and by the clock signal MCK.

[0054] 1-2. Structures of the Selection Circuit and the Analog / Digital Conversion Circuit

[0055] Figure 2 is a diagram showing a structural example of the selection circuit 50 and the analog / digital conversion circuit 60. In Figure 2In the example, the selection circuit 50 includes ten low-pass filters 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n and a multiplexer 56.

[0056] The differential signals GRO1_P and GRO1_N that constitute the angular velocity detection signal GRO1 are respectively low-pass filtered by the low-pass filters 51p and 51n and input to the multiplexer 56.

[0057] The differential signals GRO2_P and GRO2_N that constitute the vibration leakage signal GRO2 are respectively low-pass filtered by the low-pass filters 52p and 52n and input to the multiplexer 56.

[0058] The differential signals AXO_P and AXO_N that constitute the X-axis acceleration detection signal AXO are respectively low-pass filtered by the low-pass filters 53p and 53n and input to the multiplexer 56.

[0059] The differential signals AYO_P and AYO_N that constitute the Y-axis acceleration detection signal AYO are respectively low-pass filtered by the low-pass filters 54p and 54n and input to the multiplexer 56.

[0060] The differential signals TSO_P and TSO_N that constitute the temperature detection signal TSO are respectively low-pass filtered by the low-pass filters 55p and 55n and input to the multiplexer 56.

[0061] The multiplexer 56 selects, according to the selection signal SEL, any one of the differential signals GRO1_P and GRO1_N after low-pass filtering, the differential signals GRO2_P and GRO2_N after low-pass filtering, the differential signals AXO_P and AXO_N after low-pass filtering, the differential signals AYO_P and AYO_N after low-pass filtering, and the differential signals TSO_P and TSO_N after low-pass filtering as the differential signals MXO_P and MXO_N for output.

[0062] In Figure 2 the example, the analog / digital conversion circuit 60 includes a precharge circuit 61, a programmable gain amplifier 62, a successive approximation register (SAR) type analog / digital converter 63, and an SAR control circuit 64.

[0063] The precharge circuit 61 charges the input node of the programmable gain amplifier 62 according to the control signal provided by the control circuit 90 before the start of the conversion process of the successive approximation type analog / digital converter 63, thereby assisting in the charging of the differential signals MXO_P and MXO_N.

[0064] The programmable gain amplifier 62 outputs differential signals PO_P and PO_N which are the amplified differential signals MXO_P and MXO_N. The gain of the programmable gain amplifier 62 is variably set according to the control signal supplied from the control circuit 90 and according to the type of the differential signals selected as the differential signals MXO_P and MXO_N.

[0065] The successive approximation type analog / digital converter 63 uses the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale, and converts the voltage difference of the differential signals PO_P and PO_N into a digital signal ADO and outputs it.

[0066] The SAR control circuit 64 operates according to the clock signal MCK, and performs processing such as selecting the voltage to be used as the comparison reference according to the timing of the successive comparison and the comparison result of the successive approximation type analog / digital converter 63.

[0067] 1-3. Channel structure of time-division processing

[0068] As described above, the analog / digital conversion circuit 60 converts the differential signal selected by the selection circuit 50 according to the selection signal SEL into a digital signal ADO and outputs it. That is, the analog / digital conversion circuit 60 performs time-division processing on the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO and converts them into digital signals respectively.

[0069] Figure 3 It is a diagram showing an example of the channel structure of the time-division processing of the analog / digital conversion circuit 60.

[0070] As Figure 3 shown, in the first channel, the 3-bit selection signal SEL is "000", and the angular velocity detection signal GRO1 is selected as the input signal of the analog / digital conversion circuit 60 through the selection circuit 50. Therefore, during the period of the first channel, the analog / digital conversion circuit 60 converts the angular velocity detection signal GRO1, specifically the voltage difference between the differential signals GRO1_P and GRO1_N, into the digital signal ADO. In this way, in the first channel, the processing for the angular velocity detection signal GRO1 is performed.

[0071] In the second channel following the first channel, the 3-bit selection signal SEL is "001", and the vibration leakage signal GRO2 is selected as the input signal of the analog / digital conversion circuit 60 through the selection circuit 50. Therefore, during the period of the second channel, the analog / digital conversion circuit 60 converts the voltage difference between the vibration leakage signal GRO2, specifically the differential signals GRO2_P and GRO2_N, into a digital signal ADO. In this way, in the second channel, processing for the vibration leakage signal GRO2 is performed.

[0072] In the third channel following the second channel, the 3-bit selection signal SEL is "010", and the X-axis acceleration detection signal AXO is selected as the input signal of the analog / digital conversion circuit 60 through the selection circuit 50. Therefore, during the period of the third channel, the analog / digital conversion circuit 60 converts the voltage difference between the X-axis acceleration detection signal AXO, specifically the differential signals AXO_P and AXO_N, into a digital signal ADO. In this way, in the third channel, processing for the X-axis acceleration detection signal AXO is performed.

[0073] In the fourth channel following the third channel, the 3-bit selection signal SEL is "011", and the Y-axis acceleration detection signal AYO is selected as the input signal of the analog / digital conversion circuit 60 through the selection circuit 50. Therefore, during the period of the fourth channel, the analog / digital conversion circuit 60 converts the voltage difference between the Y-axis acceleration detection signal AYO, specifically the differential signals AYO_P and AYO_N, into a digital signal ADO. In this way, in the fourth channel, processing for the Y-axis acceleration detection signal AYO is performed.

[0074] In the fifth channel following the fourth channel, the 3-bit selection signal SEL is "100", and the temperature detection signal TSO is selected as the input signal of the analog / digital conversion circuit 60 through the selection circuit 50. Therefore, during the period of the fifth channel, the analog / digital conversion circuit 60 converts the voltage difference between the temperature detection signal TSO, specifically the differential signals TSO_P and TSO_N, into a digital signal ADO. In this way, in the fifth channel, processing for the temperature detection signal TSO is performed.

[0075] After the fifth channel, it returns to the first channel. That is, the periods of the first channel to the fifth channel are repeated in sequence. In the digital signal processing circuit 70, the order of the digital filter, the coefficient values, the type of calibration operation, the coefficient values, etc. are changed corresponding to the signal to be processed for each channel.

[0076] 1-4. Structure of the Fault Diagnosis Circuit

[0077] Figure 4 It is a diagram showing a structural example of a part of the reference voltage generation circuit 40 and the fault diagnosis circuit 80. InFigure 4 In the example of, the reference voltage generation circuit 40 includes a bandgap reference circuit 141, resistors 142 and 143, and an operational amplifier 144.

[0078] The bandgap reference circuit 141 is a circuit that generates a constant full-scale voltage VFSAD that is stable with respect to changes in temperature and the power supply voltage VDD by using the bandgap voltage of semiconductor elements. The structure of the bandgap reference circuit is well-known, so its illustration and description are omitted.

[0079] The resistors 142 and 143 have the same resistance value R, and the voltage obtained by dividing the full-scale voltage VFSAD by 1 / 2 through the resistors 142 and 143 is supplied to the non-inverting input terminal of the operational amplifier 144.

[0080] The inverting input terminal of the operational amplifier 144 is connected to the output terminal of the operational amplifier 144, and the operational amplifier 144 functions as a voltage follower. Therefore, the output terminal of the operational amplifier 144 is a voltage that is 1 / 2 of the full-scale voltage VFSAD, and this voltage is output as the common voltage VCMAD from the reference voltage generation circuit 40.

[0081] The fault diagnosis circuit 80 includes comparators 181 and 182, a logical OR circuit 183, a counter 184, a flag mask circuit 185, and a D-type flip-flop 186.

[0082] The common voltage VCMAD is supplied to the inverting input terminal of the comparator 181, and a prescribed threshold voltage VL is supplied to the non-inverting input terminal of the comparator 181. The output terminal of the comparator 181 becomes low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL.

[0083] The common voltage VCMAD is supplied to the non-inverting input terminal of the comparator 182, and a prescribed threshold voltage VH that is higher than the threshold voltage VL is supplied to the inverting input terminal of the comparator 182. The output terminal of the comparator 182 becomes low level when the common voltage VCMAD is equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is higher than the threshold voltage VH.

[0084] The logical OR circuit 183 is input with the output signals of the comparator 181 and the comparator 182, and outputs the logical OR signal of these signals. That is, the output signal of the logical OR circuit 183 becomes low level when both the output signal of the comparator 181 and the output signal of the comparator 182 are low level, and becomes high level when at least one of the output signal of the comparator 181 and the output signal of the comparator 182 is high level.

[0085] Therefore, the output signal of the logical OR circuit 183 becomes low level when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH. The abnormality determination circuit 81 is constituted by the comparators 181 and 182 and the logical OR circuit 183, and the output signal of the logical OR circuit 183 becomes the abnormality determination signal FLG1. That is, the abnormality determination circuit 81 determines that the common voltage VCMAD is normal when the common voltage VCMAD is above the threshold voltage VL and below the threshold voltage VH, and determines that the common voltage VCMAD is abnormal when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs the abnormality determination signal FLG1 indicating the determination result.

[0086] In addition, the threshold voltages VL and VH may be fixed values or may be variably set in the storage unit 100.

[0087] At the timing of the rising edge of the clock signal MCK, the counter 184 resets the count value CNT to 0 when the abnormality determination signal FLG1 is low level, and increments the count value CNT by 1 when the abnormality determination signal FLG1 is high level. That is, the counter 184 measures the time during which the abnormality determination signal FLG1 continuously becomes high level with the period of the clock signal MCK, and outputs the count value CNT indicating the measurement result.

[0088] The flag mask circuit 185 compares the count value CNT with the threshold DTH and outputs a flag signal FLG1X indicating the comparison result. Specifically, the flag mask circuit 185 outputs a low-level flag signal FLG1X when the count value CNT is less than the threshold DTH, and outputs a high-level flag signal FLG1X when the count value CNT is equal to or greater than the threshold DTH.

[0089] As described above, even if the reference voltage generation circuit 40 does not malfunction, the abnormality determination circuit 81 may temporarily output the abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal. Therefore, the threshold TH is set to a value larger than the value obtained by dividing the maximum time during which the common voltage VCMAD may temporarily become abnormal by the period of the clock signal MCK. In addition, the threshold DTH may be a fixed value or may be variably set in the storage unit 100.

[0090] The data input terminal D of the D flip-flop 186 is input with the power supply voltage VLGC, and the clock input terminal is input with the flag signal FLG1X. The D flip-flop 186 takes in the power supply voltage VLGC at the timing of the rising edge of the flag signal FLG1X and outputs a high-level fault diagnosis signal FLG2.

[0091] In addition, the D-type flip-flop 186 outputs a low-level fault diagnosis signal FLG2 in the initial state after power-on. Then, once the fault diagnosis signal FLG2 becomes high level, it remains high level continuously. Therefore, when the external device reads the fault diagnosis signal FLG2, if the fault diagnosis signal FLG2 is high level, it can be determined that the reference voltage generation circuit 40 has a fault, and if the fault diagnosis signal FLG2 is low level, it can be determined that the reference voltage generation circuit 40 has no fault.

[0092] In Figure 4 's example, the common voltage VCMAD is the voltage obtained by dividing the full-scale voltage VFSAD by 1 / 2 through the resistors 142 and 143. Therefore, if the full-scale voltage VFSAD is always abnormal, the common voltage VCMAD is also always abnormal, and the abnormality determination signal FLG1 is always high level. Therefore, whether the operational amplifier 144 has a fault and the common voltage VCMAD is always abnormal, or the bandgap reference circuit 141 has a fault and the full-scale voltage VFSAD is always abnormal, the fault diagnosis signal FLG2 becomes high level, and the fault diagnosis circuit 80 can diagnose that the reference voltage generation circuit 40 has a fault.

[0093] Figure 5 is a diagram showing an example of waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 has no fault. In addition, Figure 6 is a diagram showing an example of waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 has a fault.

[0094] In Figure 5 and Figure 6 's example, during the sampling period when the analog / digital conversion circuit 60 samples the voltage of the output signal MXO of the selection circuit 50, the status signal CONV is low level, and during the conversion period when the analog / digital conversion circuit 60 holds the sampled voltage and converts it into the digital signal ADO, the status signal CONV is high level. As Figure 5 and Figure 6 show, the analog / digital conversion circuit 60 alternately repeats the sampling period and the conversion period in synchronization with the repetition of the first to fifth channels. In addition, in the above Figure 1 and Figure 2 , the illustration of the status signal CONV is omitted.

[0095] In the present embodiment, in order to reduce the area of the reference voltage generation circuit 40, the supply ability to supply the full-scale voltage VFSAD to the analog / digital conversion circuit 60 is not necessarily sufficient. Therefore, during the switching between the sampling period and the conversion period of the analog / digital conversion circuit 60, the full-scale voltage VFSAD fluctuates significantly. Along with this, as Figure 5 and Figure 6 show, the common voltage VCMAD also fluctuates significantly. The timing of switching from the conversion period to the sampling period is the timing when the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50. In addition, the timing of switching from the sampling period to the conversion period is the timing when the analog / digital conversion circuit 60 ends sampling the output signal MXO of the selection circuit 50.

[0096] In Figure 5 's example, at the timing of switching between the periodically arriving sampling period and the conversion period, the common voltage VCMAD is lower than the threshold voltage VL. As a result, the phenomenon that the abnormality determination signal FLG1 becomes high level within one period of the clock signal MCK is periodically repeated. Even if the common voltage VCMAD is temporarily lower than the threshold voltage VL at the timing of switching between the sampling period and the conversion period, it does not affect the operation of the analog / digital conversion circuit 60. Therefore, it is not that the reference voltage generation circuit 40 has failed. However, assuming that the fault diagnosis signal output circuit 82 takes in the abnormality determination signal FLG1 at the timing when the common voltage VCMAD fluctuates temporarily and the abnormality determination signal FLG1 becomes high level temporarily, it outputs a high-level fault diagnosis signal FLG2. And when the external device reads out the high-level fault diagnosis signal FLG2 via the interface circuit 110, the external device erroneously determines that the reference voltage generation circuit 40 has failed.

[0097] In addition, in Figure 6 's example, the reference voltage generation circuit 40 has failed and the common voltage VCMAD is higher than the threshold voltage VH. Actually, similar to Figure 5 's example, during the switching between the sampling period and the conversion period of the analog / digital conversion circuit 60, the common voltage VCMAD fluctuates significantly. Therefore, the common voltage VCMAD is temporarily in the range above the threshold voltage VL and below the threshold voltage VH. Therefore, in Figure 6 's example, similar to Figure 5Contrary to the example, during the sampling period and the timing of switching during conversion, the abnormality determination signal FLG1 temporarily becomes low. Therefore, assuming that the fault diagnosis signal output circuit 82 takes in the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes low, a low-level fault diagnosis signal FLG2 is output. And when the external device reads out the low-level fault diagnosis signal FLG2 via the interface circuit 110, the external device erroneously determines that the reference voltage generation circuit 40 has no fault.

[0098] In contrast, in the present embodiment, when the abnormality determination signal FLG1 remains high for a specified time, the fault diagnosis signal output circuit 82 diagnoses that the reference voltage generation circuit 40 has a fault and outputs a high-level fault diagnosis signal FLG2.

[0099] Therefore, in Figure 5 the example, even if the abnormality determination signal FLG1 temporarily becomes high, the fault diagnosis signal FLG2 continues to maintain a low level. Therefore, even if the external device reads out the fault diagnosis signal FLG2 via the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has no fault.

[0100] In addition, in Figure 6 the example, after the fault diagnosis signal FLG2 initially becomes high, even if the abnormality determination signal FLG1 temporarily becomes low, the fault diagnosis signal FLG2 continues to maintain a high level. Therefore, even if the external device reads out the fault diagnosis signal FLG2 via the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has a fault.

[0101] 1-5. Processing Procedure of Fault Diagnosis Circuit

[0102] Figure 7 is a flowchart showing an example of the processing procedure of the fault diagnosis circuit 80. In addition, in Figure 7 the flowchart, the processing of each step can also be appropriately swapped.

[0103] As Figure 7 shown, first, in step S1, the fault diagnosis signal output circuit 82 of the fault diagnosis circuit 80 sets the fault diagnosis signal FLG2 to no fault. Specifically, the fault diagnosis signal output circuit 82 sets the fault diagnosis signal FLG2 to a low level.

[0104] Next, in step S2, the abnormality determination circuit 81 of the failure diagnosis circuit 80 determines whether the common voltage VCMAD is within a specified range. In step S2, when the common voltage VCMAD is within the specified range, that is, when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, in step S3, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to no abnormality. Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a low level.

[0105] On the other hand, in step S2, when the common voltage VCMAD is not within the specified range, that is, when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, in step S4, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to have an abnormality. Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a high level.

[0106] Next, before the elapse of a specified time in step S5, when the common voltage VCMAD returns to the specified range in step S6, in step S3, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to no abnormality. Then, the failure diagnosis circuit 80 performs the processing after step S1 again.

[0107] On the other hand, when the common voltage VCMAD does not return to the specified range in step S6 until the elapse of the specified time in step S5, in step S7, the failure diagnosis signal output circuit 82 sets the failure diagnosis signal FLG2 to a failure. Specifically, the failure diagnosis signal output circuit 82 sets the failure diagnosis signal FLG2 to a high level.

[0108] 1-6. Effects

[0109] In the physical quantity sensor 1 of the first embodiment described above, the physical quantity detection circuit 2 includes a failure diagnosis circuit 80. The failure diagnosis circuit 80 monitors the common voltage VCMAD generated by the reference voltage generation circuit 40 and supplied to the analog / digital conversion circuit 60, performs failure diagnosis of the reference voltage generation circuit 40, and outputs a failure diagnosis signal FLG2 indicating the result of the failure diagnosis. When the state where the common voltage VCMAD is not included in the specified range continues for a specified time, the failure diagnosis circuit 80 diagnoses that a failure has occurred in the reference voltage generation circuit 40. Further, when the common voltage VCMAD temporarily changes along with the operation of the analog / digital conversion circuit 60 and becomes a state not included in the specified range, as long as this state does not continue for the specified time, the failure diagnosis circuit 80 diagnoses that no failure has occurred in the reference voltage generation circuit 40. Therefore, according to the physical quantity sensor 1 of the first embodiment, even if the common voltage VCMAD temporarily changes, the failure diagnosis circuit 80 can reduce the possibility of misdiagnosing that a failure has occurred in the reference voltage generation circuit 40. In particular, even at the timing when the analog / digital conversion circuit 60 starts sampling the signal MXO as an analog signal and at the timing when the sampling ends, and the common voltage VCMAD temporarily changes, the failure diagnosis circuit 80 can reduce the possibility of misjudging that a failure has occurred in the reference voltage generation circuit 40. For example, even if the supply capacity of the common voltage VCMAD of the reference voltage generation circuit 40 is relatively low, since the possibility of misjudgment by the failure diagnosis circuit 80 is reduced, the size of the reference voltage generation circuit 40 can be reduced, which is beneficial to cost reduction.

[0110] Specifically, the failure diagnosis circuit 80 includes: an abnormality determination circuit 81 that determines whether the common voltage VCMAD is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result; and a failure diagnosis signal output circuit 82 that diagnoses whether a failure has occurred in the reference voltage generation circuit 40 based on the abnormality determination signal FLG1 and outputs a failure diagnosis signal FLG2 indicating the diagnosis result. Then, the failure diagnosis signal output circuit 82 diagnoses that a failure has occurred in the reference voltage generation circuit 40 when the abnormality determination signal FLG1 continuously indicates that the common voltage VCMAD is abnormal for a specified time. Therefore, when the common voltage VCMAD temporarily changes, even if the abnormality determination circuit 81 temporarily outputs an abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal, the failure diagnosis signal output circuit 82 can reduce the possibility of erroneously outputting a failure diagnosis signal FLG2 indicating that a failure has occurred in the reference voltage generation circuit 40.

[0111] In addition, in the physical quantity sensor 1 of the first embodiment, when a failure occurs in the reference voltage generation circuit 40, the failure diagnosis signal output circuit 82 can quickly output a failure diagnosis signal FLG2 indicating that a failure has occurred in the reference voltage generation circuit 40. Therefore, for example, the upper-level system can meet the requirement of a short FTTI. FTTI is the abbreviation of Fault Tolerant Time Interval, which is the time from when an abnormality occurs in the system to when it transfers to a safe state.

[0112] In this way, according to this embodiment, the failure diagnosis circuit 80 can reduce the possibility of misjudging that a failure has occurred in the reference voltage generation circuit 40. Therefore, the reliability of the physical quantity sensor 1 can be improved.

[0113] 2. Second Embodiment

[0114] Hereinafter, regarding the physical quantity sensor of the second embodiment, the same reference numerals are assigned to the same structural elements as those in the first embodiment, and the description of the content repeated from the first embodiment is omitted or simplified. The description will mainly focus on the content different from the first embodiment.

[0115] 2-1. Structure of the Physical Quantity Sensor

[0116] Figure 8 FIG. is a functional block diagram of the physical quantity sensor of the second embodiment. The physical quantity sensor 1 of the second embodiment is the same as that of the first embodiment and includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0117] The functions of the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y are the same as those in the first embodiment, so their descriptions are omitted.

[0118] Similar to the first embodiment, the physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a control circuit 90, a storage unit 100, an interface circuit 110, an oscillation circuit 120, and a failure diagnosis circuit 130, and can be implemented by, for example, a single-chip integrated circuit. In addition, the physical quantity detection circuit 2 may also be a structure in which some of these elements are omitted or changed, or other elements are added.

[0119] Since the functions of the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, the temperature sensor 30, the reference voltage generation circuit 40, the selection circuit 50, the analog / digital conversion circuit 60, the digital signal processing circuit 70, the control circuit 90, the storage unit 100, the interface circuit 110, and the oscillation circuit 120 are the same as those in the first embodiment, their descriptions are omitted.

[0120] The failure diagnosis circuit 130 performs failure diagnosis of the reference voltage generation circuit 40. Specifically, the failure diagnosis circuit 130 monitors the common voltage VCMACC, which is the reference voltage supplied from the reference voltage generation circuit 40 to the acceleration signal processing circuit 20, which is one of the physical quantity signal processing circuits. When the state where the common voltage VCMACC is not within the specified range continues for a specified time, it is diagnosed that a failure has occurred in the reference voltage generation circuit 40. In addition, the acceleration signal processing circuit 20 is an example of the "first circuit".

[0121] In the present embodiment, the failure diagnosis circuit 130 includes an abnormality determination circuit 131 and a failure diagnosis signal output circuit 132.

[0122] The abnormality determination circuit 131 determines whether the common voltage VCMACC is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may be a flag signal that becomes high level when the common voltage VCMACC is abnormal and becomes low level when the common voltage VCMACC is normal.

[0123] The failure diagnosis signal output circuit 132 diagnoses whether a failure has occurred in the reference voltage generation circuit 40 based on the abnormality determination signal FLG1, and outputs a failure diagnosis signal FLG2 indicating the diagnosis result. In the present embodiment, the common voltage VCMACC temporarily changes at least at the timing of the rising edge and the falling edge of the drive signal DRVACC for driving the acceleration detection elements 4X and 4Y. In addition, the common voltage VCMACC temporarily changes at least at the timing of the rising edge and the falling edge of the control signals CTL1 to CTLn for controlling the acceleration signal processing circuit 20. Therefore, even if the reference voltage generation circuit 40 has not failed, the abnormality determination circuit 131 may temporarily output an abnormality determination signal FLG1 indicating an abnormality of the common voltage VCMACC. Therefore, when the abnormality determination signal FLG1 continuously indicates an abnormality of the common voltage VCMACC for a specified time, the failure diagnosis signal output circuit 132 diagnoses that a failure has occurred in the reference voltage generation circuit 40, so that it is not erroneously determined that a failure has occurred in the reference voltage generation circuit 40. For example, the failure diagnosis signal FLG2 may also be a flag signal that becomes high level when a failure has occurred in the reference voltage generation circuit 40 and becomes low level when the reference voltage generation circuit 40 has not failed.

[0124] 2-2. Structure of Failure Diagnosis Circuit

[0125] Figure 9 FIG. is a diagram showing a structural example of a part of the reference voltage generation circuit 40 and the failure diagnosis circuit 130. In Figure 9 this example, the reference voltage generation circuit 40 includes a bandgap reference circuit 145, resistors 146 and 147, and an operational amplifier 148.

[0126] The bandgap reference circuit 145 is a circuit that generates a constant power supply voltage VACC that is stable with respect to changes in temperature and the power supply voltage VDD using the bandgap voltage of semiconductor elements. The structure of the bandgap reference circuit is well known, so its illustration and description are omitted.

[0127] The resistors 146 and 147 have the same resistance value R, and the voltage obtained by dividing the power supply voltage VACC by 1 / 2 through the resistors 146 and 147 is supplied to the non-inverting input terminal of the operational amplifier 148.

[0128] The inverting input terminal of the operational amplifier 148 is connected to the output terminal of the operational amplifier 148, and the operational amplifier 148 functions as a voltage follower. Therefore, the output terminal of the operational amplifier 148 is a voltage that is 1 / 2 of the power supply voltage VACC, and this voltage is output as the common voltage VCMACC from the reference voltage generation circuit 40.

[0129] The fault diagnosis circuit 130 includes comparators 231, 232, an OR circuit 233, a counter 234, a flag mask circuit 235, and a D flip-flop 236.

[0130] A common voltage VCMACC is supplied to the inverting input terminal of the comparator 231, and a specified threshold voltage VL is supplied to the non-inverting input terminal of the comparator 231. The output terminal of the comparator 231 becomes low when the common voltage VCMACC is equal to or higher than the threshold voltage VL, and becomes high when the common voltage VCMACC is lower than the threshold voltage VL.

[0131] The common voltage VCMACC is supplied to the non-inverting input terminal of the comparator 232, and a specified threshold voltage VH higher than the threshold voltage VL is supplied to the inverting input terminal of the comparator 232. The output terminal of the comparator 232 becomes low when the common voltage VCMACC is equal to or lower than the threshold voltage VH, and becomes high when the common voltage VCMACC is higher than the threshold voltage VH.

[0132] The OR circuit 233 is input with the output signals of the comparator 231 and the comparator 232, and outputs the logical OR signal of these signals. That is, the output signal of the OR circuit 233 becomes low when both the output signal of the comparator 231 and the output signal of the comparator 232 are low, and becomes high when at least one of the output signal of the comparator 231 and the output signal of the comparator 232 is high.

[0133] Therefore, the output signal of the OR circuit 233 becomes low when the common voltage VCMACC is equal to or higher than the threshold voltage VL and lower than the threshold voltage VH, and becomes high when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH. The comparator 231, 232, and the OR circuit 233 constitute an abnormality determination circuit 131, and the output signal of the OR circuit 233 becomes an abnormality determination signal FLG1. That is, the abnormality determination circuit 131 determines that the common voltage VCMACC is normal when the common voltage VCMACC is equal to or higher than the threshold voltage VL and lower than the threshold voltage VH, and determines that the common voltage VCMACC is abnormal when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs the abnormality determination signal FLG1 indicating the determination result.

[0134] In addition, the threshold voltages VL and VH can be fixed values or can be variably set in the storage unit 100.

[0135] The counter 234 is timed at the rising edge of the clock signal MCK. When the abnormality determination signal FLG1 is at a low level, the count value CNT is reset to 0. When the abnormality determination signal FLG1 is at a high level, the count value CNT is incremented by 1. That is, the counter 234 measures the time during which the abnormality determination signal FLG1 continuously remains at a high level with the period of the clock signal MCK, and outputs the count value CNT representing the measurement result.

[0136] The flag mask circuit 235 compares the count value CNT with the threshold value DTH, and outputs a flag signal FLG1X representing the comparison result. Specifically, the flag mask circuit 235 outputs a flag signal FLG1X at a low level when the count value CNT is less than the threshold value DTH, and outputs a flag signal FLG1X at a high level when the count value CNT is equal to or greater than the threshold value DTH.

[0137] As described above, even if the reference voltage generation circuit 40 does not malfunction, the abnormality determination circuit 131 may temporarily output an abnormality determination signal FLG1 indicating an abnormality of the common voltage VCMACC. Therefore, the threshold value TH is set to a value larger than the value obtained by dividing the maximum time during which the common voltage VCMACC may temporarily become abnormal by the period of the clock signal MCK. In addition, the threshold value DTH may be a fixed value or may be variably set in the storage unit 100.

[0138] The data input terminal D of the D flip-flop 236 is input with the power supply voltage VLGC, and the clock input terminal is input with the flag signal FLG1X. The D flip-flop 236 takes in the power supply voltage VLGC and outputs a fault diagnosis signal FLG2 at the timing of the rising edge of the flag signal FLG1X.

[0139] In addition, the D flip-flop 236 outputs a low-level fault diagnosis signal FLG2 in the initial state after power-on. Then, once the fault diagnosis signal FLG2 becomes high level, it remains high level continuously. Therefore, when the external device reads the fault diagnosis signal FLG2, if the fault diagnosis signal FLG2 is at a high level, it can be determined that the reference voltage generation circuit 40 has malfunctioned, and if the fault diagnosis signal FLG2 is at a low level, it can be determined that the reference voltage generation circuit 40 has not malfunctioned.

[0140] In Figure 9In the example, the common voltage VCMACC is the voltage obtained by dividing the power supply voltage VACC in half through resistors 146 and 147. Therefore, if the power supply voltage VACC is always abnormal, the common voltage VCMACC is also always abnormal, and the abnormality determination signal FLG1 is always at a high level. Thus, whether the operational amplifier 148 fails and the common voltage VCMACC is always abnormal, or the bandgap reference circuit 145 fails and the power supply voltage VACC is always abnormal, the fault diagnosis signal FLG2 becomes high level, and the fault diagnosis circuit 130 can diagnose that the reference voltage generation circuit 40 has failed.

[0141] Figure 10 FIG. is an example of waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 has not failed. In addition, Figure 11 FIG. is an example of waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generation circuit 40 has failed.

[0142] In the present embodiment, in order to reduce the area of the reference voltage generation circuit 40, the supply ability of the power supply voltage VACC of the acceleration signal processing circuit 20 is not necessarily sufficient. Since the high level of the drive signal DRVACC is the power supply voltage VACC, at the timings of the rising edge and the falling edge of the drive signal DRVACC, the power supply voltage VACC changes significantly. Along with this, as Figure 10 and Figure 11 show, the common voltage VCMACC also changes significantly. Similarly, since the high levels of the control signals CTL1 to CTLn are the power supply voltage VACC, at the timings of the rising edge and the falling edge of each of the control signals CTL1 to CTLn, the power supply voltage VACC changes significantly. Along with this, as Figure 10 and Figure 11 show, the common voltage VCMACC also changes significantly.

[0143] In Figure 10In the example, at the timings of the rising and falling edges of the drive signal DRVACC and at the timings of the rising and falling edges of the control signals CTL1 to CTLn, the common voltage VCMACC is lower than the threshold voltage VL. As a result, the phenomenon that the abnormality determination signal FLG1 becomes high level periodically repeats during one cycle of the clock signal MCK. At the timings of these edges, even if the common voltage VCMACC temporarily falls below the threshold voltage VL, it does not affect the operation of the acceleration signal processing circuit 20. Therefore, it is not that the reference voltage generation circuit 40 has failed. However, assuming that the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1 at the timing when the common voltage VCMACC temporarily changes and the abnormality determination signal FLG1 temporarily becomes high level, a high-level fault diagnosis signal FLG2 is output. And when an external device reads out the high-level fault diagnosis signal FLG2 via the interface circuit 110, the external device erroneously determines that the reference voltage generation circuit 40 has failed.

[0144] In addition, in Figure 11 the example, the reference voltage generation circuit 40 fails and the common voltage VCMACC is higher than the threshold voltage VH. Actually, similar to Figure 10 the example, at the timings of the rising and falling edges of the drive signal DRVACC and at the timings of the rising and falling edges of the control signals CTL1 to CTLn, the common voltage VCMACC fluctuates greatly. Therefore, the common voltage VCMACC temporarily falls within the range above the threshold voltage VL and below the threshold voltage VH. Therefore, in Figure 11 the example, contrary to Figure 10 the example, at these edge timings, the abnormality determination signal FLG1 temporarily becomes low level. Therefore, assuming that the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes low level, a low-level fault diagnosis signal FLG2 is output. And when an external device reads out the low-level fault diagnosis signal FLG2 via the interface circuit 110, the external device erroneously determines that the reference voltage generation circuit 40 has not failed.

[0145] In contrast, in the present embodiment, when the abnormality determination signal FLG1 remains high level for a specified time, the fault diagnosis signal output circuit 132 diagnoses that the reference voltage generation circuit 40 has failed and outputs a high-level fault diagnosis signal FLG2.

[0146] Therefore, in Figure 10In the example, the fault diagnosis signal output circuit 132 causes the fault diagnosis signal FLG2 to remain low even if the abnormality determination signal FLG1 temporarily goes high. Therefore, even if the external device reads the fault diagnosis signal FLG2 via the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has no fault.

[0147] In addition, in Figure 11 the example, after the fault diagnosis signal FLG2 initially goes high, the fault diagnosis signal FLG2 remains high even if the abnormality determination signal FLG1 temporarily goes low. Therefore, even if the external device reads the fault diagnosis signal FLG2 via the interface circuit 110 at any timing, it can correctly determine that the reference voltage generation circuit 40 has a fault.

[0148] 2-3. Processing Procedure of Fault Diagnosis Circuit

[0149] Figure 12 is a flowchart showing an example of the processing procedure of the fault diagnosis circuit 130. In addition, in Figure 12 the flowchart, the processing of each step can also be appropriately swapped.

[0150] As Figure 12 shown, first, in step S11, the fault diagnosis signal output circuit 132 of the fault diagnosis circuit 130 sets the fault diagnosis signal FLG2 to no fault. Specifically, the fault diagnosis signal output circuit 132 sets the fault diagnosis signal FLG2 to low level.

[0151] Next, in step S12, the abnormality determination circuit 131 of the fault diagnosis circuit 130 determines whether the common voltage VCMACC is within a specified range. In step S12, when the common voltage VCMACC is within the specified range, that is, when the common voltage VCMACC is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, in step S13, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to no abnormality. Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to low level.

[0152] On the other hand, in step S12, when the common voltage VCMACC is not within the specified range, that is, when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, in step S14, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to having an abnormality. Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to high level.

[0153] Next, before the elapse of the specified time in step S15, when the common voltage VCMACC returns to the specified range in step S16, in step S13, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to no abnormality. Then, the fault diagnosis circuit 130 performs the processing after step S11 again.

[0154] On the other hand, until the elapse of the specified time in step S15, when the common voltage VCMAD does not return to the specified range in step S16, in step S17, the fault diagnosis signal output circuit 132 sets the fault diagnosis signal FLG2 to a fault. Specifically, the fault diagnosis signal output circuit 132 sets the fault diagnosis signal FLG2 to a high level.

[0155] In the physical quantity sensor 1 of the second embodiment described above, the physical quantity detection circuit 2 includes a fault diagnosis circuit 130 that monitors the common voltage VCMACC generated by the reference voltage generation circuit 40 and supplied to the acceleration signal processing circuit 20, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the fault diagnosis result. When the state where the common voltage VCMACC is not included in the specified range continues for the specified time, the fault diagnosis circuit 130 diagnoses that a fault has occurred in the reference voltage generation circuit 40. In addition, when the common voltage VCMAC temporarily changes with the operation of the acceleration signal processing circuit 20 and becomes a state not included in the specified range, as long as this state does not continue for the specified time, the fault diagnosis circuit 130 diagnoses that no fault has occurred in the reference voltage generation circuit 40. Therefore, according to the physical quantity sensor 1 of the second embodiment, even if the common voltage VCMACC temporarily changes, the fault diagnosis circuit 130 can reduce the possibility of misdiagnosing that a fault has occurred in the reference voltage generation circuit 40. In particular, even when the common voltage VCMACC temporarily changes at the rising edge and falling edge of the drive signal DRVACC for driving the acceleration detection elements 4X and 4Y and at the rising edge and falling edge of each of the control signals CTL1 to CTLn for controlling the acceleration signal processing circuit 20, the fault diagnosis circuit 130 can reduce the possibility of misjudging that a fault has occurred in the reference voltage generation circuit 40. For example, even if the supply capacity of the common voltage VCMACC of the reference voltage generation circuit 40 is relatively low, since the possibility of misjudgment by the fault diagnosis circuit 130 is reduced, the size of the reference voltage generation circuit 40 can be reduced, which is beneficial to cost reduction.

[0156] Specifically, the fault diagnosis circuit 130 includes: an abnormality determination circuit 131 that determines whether the common voltage VCMACC is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result; and a fault diagnosis signal output circuit 132 that diagnoses whether a fault has occurred in the reference voltage generation circuit 40 based on the abnormality determination signal FLG1 and outputs a fault diagnosis signal FLG2 indicating the diagnosis result. Further, the fault diagnosis signal output circuit 132 diagnoses that a fault has occurred in the reference voltage generation circuit 40 when the abnormality determination signal FLG1 continuously indicates that the common voltage VCMACC is abnormal for a specified period of time. Therefore, even when the common voltage VCMACC temporarily fluctuates and the abnormality determination circuit 131 temporarily outputs the abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal, the possibility that the fault diagnosis signal output circuit 132 erroneously outputs the fault diagnosis signal FLG2 indicating that a fault has occurred in the reference voltage generation circuit 40 can be reduced.

[0157] In addition, in the physical quantity sensor 1 of the first embodiment, when a fault occurs in the reference voltage generation circuit 40, the fault diagnosis signal output circuit 132 can quickly output the fault diagnosis signal FLG2 indicating that a fault has occurred in the reference voltage generation circuit 40. Therefore, for example, the upper-level system can meet the requirement of a shorter FTTI.

[0158] In this way, according to the present embodiment, the possibility that the fault diagnosis circuit 130 misjudges that a fault has occurred in the reference voltage generation circuit 40 can be reduced, and thus the reliability of the physical quantity sensor 1 can be improved.

[0159] 3. Modification Example

[0160] For example, in the first embodiment described above, the fault diagnosis circuit 80 monitors the common voltage VCMAD, and in the second embodiment, the fault diagnosis circuit 130 monitors the common voltage VCMACC. However, the fault diagnosis circuit may also monitor both the common voltage VCMAD and the common voltage VCMACC. That is, the physical quantity sensor 1 may also have a structure that combines the first embodiment and the second embodiment.

[0161] In addition, in the first embodiment described above, the fault diagnosis circuit 80 monitors the common voltage VCMAD, but it may also monitor the full-scale voltage VFSAD, or may monitor any voltage that varies with the change of the full-scale voltage VFSAD. In the second embodiment described above, the fault diagnosis circuit 130 monitors the common voltage VCMACC, but it may also monitor the power supply voltage VACC, or may monitor any voltage that varies with the change of the power supply voltage VACC. Alternatively, the fault diagnosis circuit may monitor any voltage that varies with the change of the power supply voltage VGR, such as the common voltage VCMGR, or may monitor the power supply voltage VGR.

[0162] In addition, in each of the above-described embodiments, the physical quantity sensor 1 detects both angular velocity and acceleration as physical quantities, but it may also detect either one of the angular velocity and the acceleration. Further, the physical quantity sensor 1 may also detect a physical quantity other than the angular velocity and the acceleration as the physical quantity.

[0163] Moreover, in each of the above-described embodiments, the analog / digital conversion circuit 60 is input with a differential signal and converts the differential signal into a digital signal ADO, but it may also be input with a single-ended signal and convert the single-ended signal into the digital signal ADO.

[0164] Furthermore, in each of the above-described embodiments, the physical quantity sensor 1 includes the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y, but it may also be a sensor having only a part of these physical quantity detection elements. In addition, in each of the above-described embodiments, the angular velocity detection element is only the angular velocity detection element 3 that detects the angular velocity about the Z axis, but it may also further include one or both of an angular velocity detection element that detects the angular velocity about the X axis and an angular velocity detection element that detects the angular velocity about the Y axis, and drive circuits and detection circuits are respectively connected to the angular velocity detection elements. In addition, in each of the above-described embodiments, two acceleration detection elements are provided, namely, the acceleration detection element 4X that detects the acceleration in the X-axis direction and the acceleration detection element 4Y that detects the acceleration in the Y-axis direction, but it may also further include an acceleration detection element that detects the acceleration in the Z-axis direction, and drive circuits and detection circuits are respectively connected to the acceleration detection elements. Further, the physical quantity sensor 1 may also include a physical quantity detection element that detects a physical quantity other than the angular velocity and the acceleration, for example, a physical quantity detection element that detects physical quantities such as angular acceleration, velocity, and force.

[0165] In addition, in each of the above-described embodiments, an example is given in which the vibrating piece of the angular velocity detection element 3 is a double-T-shaped quartz vibrating piece, but the vibrating piece of the physical quantity detection element that detects various physical quantities may be, for example, a tuning fork type, a comb type, or a vibrating piece type having a shape such as a triangular prism, a quadrangular prism, or a cylindrical shape. In addition, as the material of the vibrating piece of the physical quantity detection element, for example, a piezoelectric material such as a piezoelectric single crystal such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), or a piezoelectric ceramic such as lead zirconate titanate (PZT) may be used instead of quartz (SiO2), or a silicon semiconductor may also be used. In addition, the vibrating piece of the physical quantity detection element may also be, for example, a structure in which a piezoelectric thin film such as zinc oxide (ZnO) or aluminum nitride (AlN) sandwiched by drive electrodes is disposed on a part of the surface of the silicon semiconductor.

[0166] In addition, in each of the above-described embodiments, the piezoelectric angular velocity detection element 3 and the electrostatic capacitance type acceleration detection elements 4X and 4Y are exemplified. However, the physical quantity detection elements for detecting various physical quantities are not limited to piezoelectric type and electrostatic capacitance type elements, and may also be electric type, eddy current type, optical type, strain gauge type, etc. Further, the detection method of the physical quantity detection element is not limited to the vibration type, and for example, it may also be an optical type, a rotational type, or a fluid type.

[0167] In addition, in each of the above-described embodiments, physical quantity sensors for detecting angular velocity and acceleration are exemplified. However, the failure diagnosis circuit of the present invention can be applied to any physical quantity sensor that operates based on a reference voltage generated by a reference voltage generation circuit such as a regulator. Examples of such physical quantity sensors include a FOG (Fiber Optic Gyroscope), a temperature sensor, a pressure sensor, a gas sensor, a humidity sensor, etc. Further, the failure diagnosis circuit of the present invention can be applied not only to physical quantity sensors but also to vibration devices. Vibration devices include, for example, vibration type physical quantity sensors in which a physical quantity detection element vibrates, an oscillator that oscillates an oscillator to generate an oscillation signal, etc. Examples of such an oscillator include an oscillator including a quartz oscillator and a silicon MEMS (Micro Electro Mechanical Systems) resonator. Since these vibration devices have the failure diagnosis circuit of the present invention, higher reliability can be achieved.

[0168] The above-described embodiments and modification examples are just examples and are not limited thereto. For example, the respective embodiments and modification examples may be appropriately combined.

[0169] The present invention includes a structure that is substantially the same as the structure described in the embodiment, for example, a structure having the same function, method, and result, or a structure having the same purpose and effect. Further, the present invention includes a structure in which non-essential parts of the structure described in the embodiment are replaced. Further, the present invention includes a structure that exhibits the same effect as the structure described in the embodiment or can achieve the same purpose. Further, the present invention includes a structure in which a well-known technique is added to the structure described in the embodiment.

[0170] The following is derived from the above-described embodiments and modification examples.

[0171] One mode of the failure diagnosis circuit is a failure diagnosis circuit that performs failure diagnosis of a reference voltage generation circuit, monitors the reference voltage supplied from the reference voltage generation circuit to the first circuit, and diagnoses that the reference voltage generation circuit has failed when the state where the reference voltage is not within a specified range continues for a specified time.

[0172] When the state where the reference voltage is not within the specified range continues for a specified time, the fault diagnosis circuit diagnoses that a fault has occurred in the reference voltage generation circuit.

[0173] In addition, when the reference voltage temporarily changes to a state where it is not within the specified range, as long as this state does not continue for the specified time, the fault diagnosis circuit does not diagnose that a fault has occurred in the reference voltage generation circuit. Therefore, according to this fault diagnosis circuit, even if the reference voltage temporarily changes, the possibility of misdiagnosing that a fault has occurred in the reference voltage generation circuit can be reduced. For example, even if the supply ability of the reference voltage of the reference voltage generation circuit is relatively low, since the possibility of misjudgment by the fault diagnosis circuit is also reduced, the size of the reference voltage generation circuit can be reduced.

[0174] In one mode of the fault diagnosis circuit, the first circuit may be an analog / digital conversion circuit that converts an analog signal into a digital signal.

[0175] According to this fault diagnosis circuit, even if the reference voltage temporarily changes with the operation of the analog / digital conversion circuit, the possibility of misjudging that a fault has occurred in the reference voltage generation circuit can be reduced.

[0176] In one mode of the fault diagnosis circuit, the first circuit may be a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element.

[0177] According to this fault diagnosis circuit, even if the reference voltage temporarily changes with the operation of the physical quantity signal processing circuit, the possibility of misjudging that a fault has occurred in the reference voltage generation circuit can be reduced.

[0178] In one mode of the fault diagnosis circuit, the reference voltage may temporarily change at least at one of the timing when the analog / digital conversion circuit starts sampling the analog signal and the timing when it ends sampling the analog signal.

[0179] According to this fault diagnosis circuit, even if the reference voltage temporarily changes at the timing when the analog / digital conversion circuit starts sampling the analog signal and the timing when it ends sampling the analog signal, the possibility of misjudging that a fault has occurred in the reference voltage generation circuit can be reduced.

[0180] In one mode of the fault diagnosis circuit, the reference voltage may temporarily change at least at one of the rising edge and the falling edge of the drive signal.

[0181] According to this fault diagnosis circuit, even if the reference voltage temporarily changes at the rising edge and falling edge of the drive signal of the physical quantity detection element, the possibility of misjudging that the reference voltage generation circuit has failed can be reduced.

[0182] In one mode of the fault diagnosis circuit, it may also be that the reference voltage temporarily changes at the timing of at least one of the rising edge and falling edge of the control signal for controlling the physical quantity signal processing circuit.

[0183] According to this fault diagnosis circuit, even if the reference voltage temporarily changes at the rising edge and falling edge of the control signal of the physical quantity signal processing circuit, the possibility of misjudging that the reference voltage generation circuit has failed can be reduced.

[0184] One mode of the fault diagnosis circuit may also include: an abnormality determination circuit that determines whether the reference voltage is abnormal and outputs an abnormality determination signal indicating the determination result; and a fault diagnosis signal output circuit that diagnoses whether the reference voltage generation circuit has failed based on the abnormality determination signal and outputs a fault diagnosis signal indicating the diagnosis result. When the abnormality determination signal continuously indicates that the reference voltage is abnormal for a specified time, the fault diagnosis signal output circuit diagnoses that the reference voltage generation circuit has failed.

[0185] According to this fault diagnosis circuit, in the case where the reference voltage temporarily changes, even if the abnormality determination circuit temporarily outputs an abnormality determination signal indicating that the reference voltage is abnormal, the possibility that the fault diagnosis signal output circuit erroneously outputs a fault diagnosis signal indicating that the reference voltage generation circuit has failed can be reduced.

[0186] In addition, according to this fault diagnosis circuit, in the case where the reference voltage generation circuit has failed, the fault diagnosis signal output circuit can quickly output a fault diagnosis signal indicating that the reference voltage generation circuit has failed. Therefore, for example, the upper-level system can meet the requirements of a short FTTI.

[0187] One mode of the vibration device has one mode of the fault diagnosis circuit.

[0188] According to this vibration device, since it has a fault diagnosis circuit that can reduce the possibility of misdiagnosing that the reference voltage generation circuit has failed even if the reference voltage temporarily changes, high reliability can be achieved.

[0189] One mode of the physical quantity sensor includes one mode of the fault diagnosis circuit.

[0190] According to this physical quantity sensor, since it is equipped with a fault diagnosis circuit that can reduce the possibility of misdiagnosing a failure in the reference voltage generation circuit even when the reference voltage changes temporarily, high reliability can be achieved.

Claims

1. A fault diagnosis circuit that performs fault diagnosis on a reference voltage generation circuit. The fault diagnosis circuit monitors the reference voltage supplied from the reference voltage generation circuit to the first circuit, and diagnoses that a fault has occurred in the reference voltage generation circuit when the state where the reference voltage is not within a specified range continues for a specified time.

2. The fault diagnosis circuit according to claim 1, wherein the first circuit is an analog / digital conversion circuit that converts an analog signal into a digital signal.

3. The fault diagnosis circuit according to claim 1, wherein the first circuit is a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on the output signal of the physical quantity detection element.

4. The fault diagnosis circuit according to claim 2, wherein at least one of the timing when the analog / digital conversion circuit starts sampling the analog signal and the timing when it ends the sampling, the reference voltage temporarily changes.

5. The fault diagnosis circuit according to claim 3, wherein at least one of the timing of the rising edge and the falling edge of the drive signal, the reference voltage temporarily changes.

6. The fault diagnosis circuit according to claim 3, wherein at least one of the timing of the rising edge and the falling edge of the control signal for controlling the physical quantity signal processing circuit, the reference voltage temporarily changes.

7. The fault diagnosis circuit according to claim 1, wherein the fault diagnosis circuit includes: an abnormality determination circuit that determines whether the reference voltage is abnormal and outputs an abnormality determination signal indicating the determination result; and a fault diagnosis signal output circuit that diagnoses whether a fault has occurred in the reference voltage generation circuit based on the abnormality determination signal and outputs a fault diagnosis signal indicating the diagnosis result, when the abnormality determination signal continuously indicates that the reference voltage is abnormal for a specified time, the fault diagnosis signal output circuit diagnoses that a fault has occurred in the reference voltage generation circuit.

8. A vibration device including the fault diagnosis circuit according to claim 1.

9. A physical quantity sensor including the fault diagnosis circuit according to claim 1.

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