Power supply test circuit and method

Abstract

The present application discloses a power supply test circuit and method, which belongs to the field of power electronics technology. The method includes: the power supply module includes a power management circuit, a full-bridge drive circuit and a transformer circuit connected in sequence, the transformer circuit provides multiple power supply terminals, the multiple power supply terminals are respectively connected to corresponding test modules, and the test module is used to connect the power supply to be tested; the control module is respectively connected to each test module and the drive module, the drive module is respectively connected to each test module, the control module is used to configure the test parameters of the test module to control the drive module to drive the test module to test the power supply to be tested, receive the test data returned by the test module, and determine the test results of the power supply to be tested based on the test data. This method isolates each test module, can eliminate current disturbances and noise defects, simplify the test process and the product parameter setting of the power supply to be tested, shorten the test time, and reduce the investment cost of equipment and instruments.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a power supply testing circuit and method. Background Art

[0002] With the development of technology, the variety and functions of power supply products are increasing, and higher requirements are being placed on power supply performance testing. Power supply products must undergo rigorous testing before leaving the factory to ensure their performance and quality. Currently, there are many problems in the field of power supply testing equipment. Power supply functional testing requires multiple electronic load testers, oscilloscopes, power analyzers, short-circuit testers, PICs, computers, and other equipment to complete the basic functions of qualified power supply testing. These equipment have many disadvantages, such as large space requirements, poor stability, high costs, inconvenient mobility, and complex operation.

[0003] At present, during the power supply testing process, multiple test circuits are set up for the power supply product to be tested. Each test circuit is equipped with modules such as an electronic load tester, an oscilloscope, a fast charging protocol, a power analyzer and a power measurement module.

[0004] However, the test circuits interfere with each other, causing current disturbances and noise. There are also defects such as complex operation and power product parameter settings, long test time, and excessive investment in test instruments. Summary of the Invention

[0005] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a power supply test circuit and method that isolates each test module, eliminates current disturbances and noise defects, simplifies the test process and product parameter setting of the power supply under test, shortens test time, and reduces equipment and instrumentation investment costs.

[0006] In a first aspect, the present application provides a power supply test circuit, which includes: a power supply module, multiple test modules, a control module and a drive module;

[0007] The power module includes a switching power supply circuit, which includes a power management circuit, a full-bridge drive circuit, and a transformer circuit connected in sequence. The transformer circuit provides multiple power supply terminals, each of which is connected to a corresponding test module. The test module is used to connect to the power supply to be tested;

[0008] The control module is respectively connected to each of the test modules and the drive module, and the drive module is respectively connected to each of the test modules. The control module is used to configure test parameters for the test module to control the drive module to drive the test module to test the power supply to be tested, receive test data returned by the test module, and determine the test result of the power supply to be tested based on the test data.

[0009] In a second aspect, the present application provides a power supply testing method, which is applied to the power supply testing circuit of the first aspect, and the method includes:

[0010] Powering the test module through multiple power supply terminals via the power module;

[0011] The control module configures test parameters for the test module to control the drive module to drive the test module to test the power supply to be tested, receives test data returned by the test module, and determines the test result of the power supply to be tested according to the test data.

[0012] Additional aspects and advantages of the present application will be described in part in the following description, and will become apparent from the following description or learned through practice of the present application. The present application provides a power supply test circuit and method that has the following advantages over the prior art:

[0013] (1) The power module provides stable and adjustable multi-terminal power supply, providing independent adaptive power supply for different test modules; the control module configures and manages each test module separately, and each test module works independently, reducing mutual interference and mutual influence, ensuring the accuracy of the test results; isolating each test module can eliminate current disturbances and noise defects;

[0014] (2) Using two transformers, T901 and T902, multiple voltages, such as 485AC, AC1, AC2, AC3, and AC4, are output from the secondary winding side to provide the required voltage levels for different loads. Transformers T901 and T902 provide electrical isolation during the power conversion process, isolating the input power on the primary winding side from the output power on the secondary winding side. This prevents mutual interference between power supplies, improves the safety and stability of the power supply system, and also meets the electrical isolation requirements of different loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0016] Figure 1 1 is a schematic diagram of the structure of the power supply test circuit provided in an embodiment of the present application;

[0017] Figure 2 This is a schematic diagram of the structure of the power module provided in an embodiment of the present application;

[0018] Figure 3 This is a schematic diagram of the structure of the test module provided in the embodiment of the present application;

[0019] Figure 4This is a schematic diagram of the structure of the main control module provided in an embodiment of the present application;

[0020] Figure 5 is a schematic structural diagram of a driving module provided in an embodiment of the present application;

[0021] Figure 6 This is a schematic diagram of the structure of the power supply testing method provided in an embodiment of the present application;

[0022] Description of reference numerals:

[0023] Power supply module 110 ; test module 120 ; control module 130 ; drive module 140 . DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0025] The power supply test circuit and power supply test method provided in the embodiments of the present application are described in detail below with reference to specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0026] like Figure 1 As shown, the power supply test circuit includes: a power supply module 110, a plurality of test modules 120, a control module 130 and a drive module 140;

[0027] The power module 110 includes a switching power supply circuit, which includes a power management circuit, a full-bridge drive circuit, and a transformer circuit connected in sequence. The transformer circuit provides multiple power supply terminals, each of which is connected to a corresponding test module 120. The test module 120 is used to connect to the power supply to be tested;

[0028] The control module 130 is respectively connected to each of the test modules 120 and the drive module 140, and the drive module 140 is respectively connected to each of the test modules 120. The control module 130 is used to configure test parameters for the test module 120 to control the drive module 140 to drive the test module 120 to test the power supply to be tested, receive test data returned by the test module 120, and determine the test result of the power supply to be tested based on the test data.

[0029] Among them, the test parameters include AC input current, voltage, power, static voltage and current, power consumption, output voltage, current, power, ripple, overcurrent OCP, short circuit, PF value, forward and reverse insertion, fast charging protocol deception, etc. In the test module 120, multiple related modules are combined to form a set of functionally complete power parameter detection instruments;

[0030] Test data includes output voltage, output current, ripple and noise, load regulation, line regulation, transient response, startup and shutdown time, overcurrent protection, overvoltage protection, overtemperature protection, power efficiency, hold-up time, insulation resistance, leakage current, etc.

[0031] The test results include power supply performance evaluation results, stability evaluation results, dynamic response evaluation results, as well as efficiency and energy consumption evaluation results.

[0032] After obtaining the test data, it can be determined whether the power supply under test is qualified and the data can be automatically saved in the computer file.

[0033] According to the power supply test circuit provided in the embodiment of the present application, a stable and adjustable multi-terminal power supply is provided through the power supply module, and an adaptive power supply is independently provided for different test modules; the control module configures and manages each test module separately, and each test module works independently, reducing mutual interference and mutual influence, and ensuring the accuracy of the test results; isolating each test module can eliminate current disturbances and noise defects.

[0034] In some embodiments, as Figure 2 As shown, the full-bridge drive circuit includes a high-end arm and a low-end arm, the high-end arm includes a transistor Q901 and a transistor Q902, the low-end arm includes a low-end arm composed of a MOS transistor Q903 and a MOS transistor Q904, and the high-end arm is connected to the power management circuit;

[0035] The transformer circuit includes a transformer T901 and a transformer T902, the primary circuit of the transformer T901 is connected to the low-end arm, the transformer T901 and the transformer T902 are connected in series resonance, and the secondary circuit of the transformer T901 and the secondary circuit of the transformer T902 are both used to provide the power supply end.

[0036] In some embodiments, the first end of the low-end arm is connected to pin 1 of the transformer T901 and pin 1 of the transformer T902, and the second end of the low-end arm is connected to pin 3 of the transformer T901 and pin 3 of the transformer T902.

[0037] On the primary winding side of the transformer T901, pin 1 is connected to pin 3 via a capacitor C908 and a resistor R913 connected in series, and pin 2 of the transformer T901 is connected to terminal VDD1;

[0038] On the secondary winding side of the transformer T901, pin 4 is connected to terminal 485b, pin 5 is connected to terminal 485AC, pin 6 is connected to GND2, pin 7 is connected to terminal AC2, pin 8 is connected to GND1, and pin 9 is connected to terminal AC1;

[0039] On the primary winding side of the transformer T902, pin 1 is connected to pin 3 via a capacitor C909 and a resistor R914 connected in series, and pin 2 of the transformer T902 is connected to terminal VDD2;

[0040] On the secondary winding side of the transformer T902, pin 4 is connected to GND4, pin 5 is connected to terminal AC4, pin 6 is connected to GND3, pin 7 is connected to terminal AC3, pin 8 is connected to terminal vss, and pin 9 is connected to terminal MCUA;

[0041] The terminal AC1, the terminal AC2, the terminal AC3 and the terminal AC4 are the power supply terminals.

[0042] Terminal 485b is connected to GND485.

[0043] In the case grounding circuit, the case of the power supply under test is connected to END through P1, P2, P3, and P4.

[0044] In the switching power supply circuit, pin 1 of DC12V1 on the CON2 port and pin 1 of DC12V2 on the CON2 port are both connected to the power IN+12V, and pin 2 of DC12V1 on the CON2 port and pin 2 of DC12V2 on the CON2 port are both connected to GND.

[0045] Pin 1 of the DC12V1 port of CON2 is connected to the VCC+, C2, and C1 pins of the power management chip U901 through the positive-connected diode D901. The cathode of the diode D901 is connected to the DTC and GND pins of the power management chip U901 through the capacitor C901 and then to GND.

[0046] Among them, the power management chip U901 is TL494C.

[0047] The cathode of diode D901 is connected to pins IN1+ and IN2+ of power management chip U901 through reverse-connected diode ZD901, and the anode of diode D901 is connected to GND through resistor R901.

[0048] Pin IN1- of the power management chip U901 is connected to pin IN2+, pin REF OUT, and pin OUTPUTCTRL respectively. Pin VCC+ of the power management chip U901 is connected to pin DTC via resistor R901. Pin CT of the power management chip U901 is connected to GND via capacitor C902. Pin RT of the power management chip U901 is connected to GND via resistor R902.

[0049] The power supply IN+12V is connected to the terminal VDD1 through the resistor R910, the terminal VDD1 is connected to GND through the capacitor R905, GND is connected to END through the capacitor CY0, the power supply IN+12V is connected to the terminal VDD2 through the resistor R909, and the terminal VDD2 is connected to GND through the capacitor C907.

[0050] Pin E2 of the power management chip U901 is connected to the base of transistor Q901 and to the collector of transistor Q901 through a forward-connected diode D903. The collector of transistor Q901 is connected to the gate of MOS transistor Q903 through resistor R905. Pin E2 is also connected to the emitter of transistor Q901 through resistor R903 and to GND. The gate of MOS transistor Q903 is connected to the emitter of transistor Q901 through resistor R907.

[0051] Pin E1 of the power management chip U901 is connected to the base of transistor Q902, and is connected to the collector of transistor Q902 and the emitter of transistor Q901 through resistor R904. Pin E1 is connected to the emitter of transistor Q902 through a forward-connected diode D904. The emitter of transistor Q902 is connected to the gate of MOS transistor Q904 through resistor R906. The gate of MOS transistor Q904 is connected to the collector of transistor Q902 through resistor R908.

[0052] Transistor Q901, transistor Q902, MOS transistor Q903, and MOS transistor Q904 form a full-bridge circuit, and the source of MOS transistor Q903 is connected to the drain of MOS transistor Q904 and connected to GND;

[0053] During operation, the switching power supply circuit converts the input 12V DC power into multiple output voltage levels. This is isolated and converted via a full-bridge driver circuit and transformer. The power management chip U901 adjusts the pulse width and controls the switching of the full-bridge driver circuit, converting the input 12V DC power into different output voltage levels. On the primary winding side, the input 12V power can be stepped up or down to meet the needs of different loads.

[0054] Using two transformers, T901 and T902, multiple voltages—485VAC, AC1, AC2, AC3, and AC4—are output from the secondary winding, providing the required voltage levels for different loads. Transformers T901 and T902 provide electrical isolation during the power conversion process, isolating the input power on the primary winding from the output power on the secondary winding. This prevents mutual interference between power supplies, improves the safety and stability of the power supply system, and meets the electrical isolation requirements of different loads.

[0055] The TL494C power management chip precisely adjusts pulse width, thereby controlling the output voltage and current, achieving precise control of the power supply. Adjusting the external resistor and capacitor connected to pins CT and RT changes the oscillation frequency to accommodate varying load conditions. The overload protection circuit is comprised of diodes D901, ZD901, and resistor R901.

[0056] At the input, resistors R910 and R909 and capacitors C905 and C907 filter the 12V input power, reducing ripple and noise and improving power stability. On the secondary winding side of the transformer, the output voltage is rectified and filtered, further reducing ripple and providing a more stable power output.

[0057] It can be understood that the circuit structure connected to terminals AC2, AC3, and AC4 is the same as the circuit structure connected to terminal AC1, and the ground terminals of the corresponding circuit structures are connected to GND2, GND3, and GND4 respectively;

[0058] In some embodiments, the power module 110 further includes a grounding circuit, and the grounding circuit includes capacitors CY1, CY2, CY3, and CY4;

[0059] The terminal GND1, the terminal GND2, the terminal GND3 and the terminal GND4 are connected to END via the capacitor CY1, the capacitor CY2, the capacitor CY3 and the capacitor CY4 respectively;

[0060] The terminal GND1 , the terminal GND2 , the terminal GND3 , and the terminal GND4 are connected to the test circuits corresponding to the terminal AC1 , the terminal AC2 , the terminal AC3 , and the terminal AC4 , respectively.

[0061] The capacitance CY1, capacitance CY2, capacitance CY3, and capacitance CY4 are 102N / 1KV.

[0062] During the operation of the ground circuit, the input of each regulator is connected to its own ground line (GND1, GND2, GND3, GND4) through multiple capacitors in parallel, and the output is also connected to the ground line through capacitors for filtering and reducing ripple and noise in the power supply.

[0063] The corresponding terminals of the ground lines GND1, GND2, GND3 and GND4 are connected to the common end (END) through 102N / 1KV capacitors (CY1, CY2, CY3, CY4) to achieve further filtering and decoupling between the ground lines.

[0064] The capacitor configuration at the input and output terminals can effectively filter out high-frequency noise and ripple in the power supply, ensuring output voltage stability. The 102N / 1KV capacitor connected between the ground wire and the common terminal can further reduce the potential difference between the ground wires and high-frequency interference, improving the stability of the entire power supply system.

[0065] In this embodiment, each test module is isolated and independent, and is powered by a separate power supply to achieve isolation. The test modules do not interfere with each other, and multiple products can be tested simultaneously.

[0066] In the first DC voltage regulator circuit, terminal 485AC is connected to pin Vin of the voltage regulator U5 through a forward-connected diode D1. Pin Vin of the voltage regulator U5 is connected to terminal GND485 and pin GND of the voltage regulator U5 through capacitors CRS5 and CRS6 in parallel. Pin Out of the voltage regulator U5 is connected to power supply 485+5V and is connected to terminal GND485 through capacitors CRS7 and CRS8 in parallel.

[0067] Among them, the voltage regulator U5 is ME6231A50M3, and the capacitors CRS5 and CRS8 are positively connected.

[0068] During the operation of the first DC voltage stabilization circuit, the voltage regulator U5 can convert the higher voltage from the terminal 485AC into a stable +5V output to meet the demand of the subsequent circuit for 5V power supply.

[0069] In the power supply circuit, terminal MCUA is connected to pin Vin and pin 4 of the voltage regulator U3 through a forward-connected diode D2. Pin Vin of the voltage regulator U3 is connected to terminal vss and terminal VSS through capacitors CRS9 and CRS10 connected in parallel. Pin -3.3V of the voltage regulator U3 is connected to the power supply +3.3V and terminal +3.3V, and is connected to pin GND of the voltage regulator U3 and terminal VSS through capacitors CRS11 and CRS12 connected in parallel.

[0070] Among them, the voltage regulator U3 is ME6216A10PG50, and the capacitors CRS10 and CRS11 are positively connected.

[0071] The voltage regulator U3 can convert the higher voltage from the terminal MCUA into a stable +3.3V voltage output. The forward connection of the diode D2 can prevent the power supply from being connected in reverse, protecting the subsequent circuit from damage by reverse voltage and improving the safety of the circuit.

[0072] The capacitors at the input and output ends are used to filter the input voltage, remove high-frequency noise and ripple in the voltage, reduce power supply fluctuations, make the output voltage more stable, and provide a purer power supply for subsequent circuits.

[0073] The following describes the embodiment of the present application by taking the circuit structure in which the terminal AC1 is connected as an example.

[0074] In the second DC voltage stabilization circuit, terminal AC1 is connected to the power supply +12V, pin Vin and pin 4 of the voltage regulator U108 through a forward-connected diode D101. Pin Vin is connected to pin GND of the voltage regulator U108 and to GND1 through capacitors C132, C133 and C134 connected in parallel. Pin +5V of the voltage regulator U108 is connected to the power supply +5V1 and to GND1 through capacitor C135.

[0075] Among them, the voltage regulator U108 is ME6216A10PG50, and the capacitors C134 and C135 are positively connected.

[0076] During the operation of the second DC voltage stabilization circuit, the higher input voltage (from terminal AC1) is converted into a stable +5V output (power supply +5V1), providing a stable power supply for the subsequent circuit; the higher input voltage of terminal AC1 is converted into a stable +5V output to meet the subsequent circuit's demand for 5V power supply.

[0077] In some embodiments, as Figure 3 As shown, the test module 120 includes a sub-control module;

[0078] The auxiliary control module includes an auxiliary control board, and a power protection circuit, a first filter circuit, a second filter circuit, a signal modulation circuit and a control protection circuit connected to the auxiliary control board;

[0079] The auxiliary control board is used to control the test of the power supply to be tested based on the configured test parameters;

[0080] The power protection circuit is used to perform PD reverse insertion control on the power supply under test, the first filter circuit is used to perform D+ sampling on the power supply under test, and the second filter circuit is used to perform D- sampling on the power supply under test, and the current and voltage at the VBUS1 end in the signal modulation circuit are obtained through the D+ sampling and D- sampling;

[0081] The signal modulation circuit is used to perform reverse insertion control of D+ and D- on the power supply to be tested, and the control protection circuit is used to perform reverse insertion control of C1 and C2 on the power supply to be tested.

[0082] In the auxiliary control board, in the auxiliary control chip U101, pin L-TX / PA2 is connected to terminal C1-1, pin L-RX / PA3 is connected to terminal C1-2, pin PB13 is connected to terminal SCLK1, pin PB14 is connected to terminal MISO1, pin PB15 is connected to terminal MOSI1, pin PC6 is connected to terminal INT2.1, pin PC7 is connected to terminal INT1.1, pin PC8 is connected to terminal SCL1, pin PC0ADC12_IN10 is connected to terminal pwmCC1, pin PC1 ADC12_IN11 connects to terminal pwmCV1, pin PC13 connects to terminal YL1-1, pin PC14 / OSC32-IN connects to terminal YL1-2, pin PC15 / OSC32-O connects to terminal YL1-3, pin PC3ADC12_IN13 connects to terminal YL1-4, pin PA0 / ADC12_IN1 connects to terminal VD+1, pin PA1 / DC12_IN2 connects to terminal VD-1, pin PA4 / DAC1_OUT1 connects to terminal Adata1, pin PA5 / DAC1_OUT2 connected to terminals YL1-5, pin PA6 / ADC2_IN3 connected to terminals YL1-6, pin PA7 / ADC2_IN4 connected to terminals YL1-7, pin PC4 / ADC2_IN5 connected to terminals YL1-8, pin PC5 / ADC2_IN11 connected to terminals YL1-9, pin PB0 / ADC1_IN15 connected to terminals YL1-10, pin PB2 / ADC2_IN12 connected to terminal V1,

[0083] Pin PF0 / OSC_IN is connected to pin PF1 / OSC_OUT through crystal oscillator Y101, pin PF0 / OSC_IN is connected to GND1 through capacitor C125, and pin PF1 / OSC_OUT is connected to GND1 through capacitor C126;

[0084] Pin NRST is connected to pin GNDA, terminal NRST1 and GNDA1, pin GNDA is connected to GND1 via capacitor C127, and pin GNDA is also connected to GND1 via filter element FB103;

[0085] Pins NTGND, GND, VSS1, VSS2, and VSS3 are all connected to GND1.

[0086] Pin BOOT0 / PB8 connects to terminal KO1, pin PC9 connects to terminal SDA1, pin PA11 connects to terminal ENCC1-1, pin PA12 connects to terminal ENCC1-2, pin PA15 connects to terminal ACSCSN1, pin PC12 connects to terminal ACTXD1, pin PD2 connects to terminal EN-N1,

[0087] Pin PD5 is connected to terminal D+1 through resistor R173, terminal D+1 is connected to pin USART1_TX / PD6 through resistor R174, pin RX3 / PB11 is connected to terminal I2C1, pin TX3 / PB10 is connected to terminal ID-ONF1, pin TX1 / PA9 is connected to terminal TXD1, pin RX1 / PA10 is connected to terminal RXD1, pin RX4 / PC11 is connected to terminal ACRXD1, pin TX4 / PC10 is connected to terminal ACSCLK1, pin RX2 / PD4 is connected to terminal D-1 through resistor R172, pin TX2 / PD3 is connected to terminal X2 / PD3 through resistor R171,

[0088] Pin SWLCK-JICK-PA14 is connected to pin 5 of port CON101. Pin 5 of port CON101 is connected to GND1 through resistor R176. Pin SWDIO-JTMS / PA13 is connected to pin 4 of port CON101 and connected to +3.3V1 through capacitor R175. Pin 1 of port CON101 is connected to +3.3V1. Pin 2 of port CON101 is connected to GND1. Pin 2 of port CON101 is connected to terminal NRST1.

[0089] The two pins VDDA are connected to the terminal VAD1-1, the pin VREF+ is connected to the VREEP1 end, and is connected to GND1 through the capacitor C124. The pins VDD3, VDD2, and VDD1 are all connected to the VBD1 end. The VBD1 end is connected to GND1 through the parallel capacitors C119 and C120. The VBD1 end is connected to the VBAT1 end through the filter element FB101. The VBD1 end is connected to the VREEP1 end through the filter element FB102. The VBD1 end is connected to +3.3V1 and the pin +3.3V1 of the voltage regulator U109 through the inductor L101. The pin +3.3V1 of the voltage regulator U109 is connected to GND1 and the pin GND of the voltage regulator U109 through the capacitor C121. The pin Vin and pin 4 of the voltage regulator U109 are connected to +5V1 and are connected to GND1 through the capacitor C122.

[0090] The sub-control chip U101 is STM32G431RBT6, the voltage regulator U109 is ME6216A10PG50, and the port CON101 is 2.54A-5P.

[0091] The SWLCK-JICK-PA14 and SWDIO-JTMS / PA13 pins are used for debugging interfaces and are connected to the corresponding pins of CON101 to monitor and debug the system.

[0092] D+ and D- are signal lines for data transmission, representing the positive and negative sides of differential signals in USB communication. These lines are controlled by the auxiliary control board, which simulates plugging and unplugging by turning the MOS transistors on and off, allowing for dynamic connection and disconnection of the circuit. This reduces physical plugging and unplugging, extending the life of the interface, saving time, preventing misplugging, and improving efficiency. This allows for rapid switching and automated control of circuit connection states, thereby increasing the efficiency of the entire testing process.

[0093] In port COM102, pin 1 is connected to +12V1, pin 2 is connected to GND1, pin 3 is connected to terminal ACTXD1, pin 4 is connected to terminal ACRXD1, pin 5 is connected to terminal INT2.1, pin 6 is connected to terminal V1, pin 7 is connected to terminal ACSCSN1, and pin 8 is connected to terminal ACSCLK1.

[0094] Port COM102 is connected to 2.54A-8P and is used for data exchange and coordinated control with external devices to ensure the smooth progress of the entire test process.

[0095] In reserved port 1, pin 1 is connected to terminal YL1-1, pin 2 is connected to terminal YL1-2, pin 3 is connected to terminal YL1-3, pin 4 is connected to terminal YL1-4, pin 5 is connected to terminal YL1-5, pin 6 is connected to terminal YL1-6, pin 7 is connected to terminal YL1-7, pin 8 is connected to terminal YL1-8, pin 9 is connected to terminal YL1-9, pin 10 is connected to terminal YL1-10, pin 11 is connected to +5V1, and pin 12 is connected to GND1;

[0096] Port 1 is reserved for 2.54-12P.

[0097] In the auxiliary control module, port 1 is reserved for connecting external devices or modules, providing additional signal connections and power pins, enhancing the flexibility and expansion capabilities of the system, and providing more possibilities and convenience for power supply testing.

[0098] In the voltage feedback circuit, terminal Cvin1 is connected to the output of op amp U104 through resistor R162, and is connected to the reverse input of op amp U104 through parallel resistor R163 and capacitor C117. The positive power supply of op amp U104 is connected to +5V1 and GND1 through capacitor C116. The reverse input of op amp U104 is connected to GND1 through resistors R164, R165, and R166 connected in sequence. The positive input of op amp U104 is connected to terminal VBUS1 through resistors R167, R168, and R169 connected in sequence. The positive input of op amp U104 is connected to the negative power supply of op amp U104 and GND1 through capacitor C118 and resistor R170 connected in parallel. Op amp U104 is LMV721.

[0099] This circuit is used to monitor the input voltage of terminal Cvin1 and compare it with the reference voltage of terminal VBUS1. Through the feedback control of operational amplifier U104, accurate monitoring and stable control of the input voltage are achieved. Through the feedback network formed by resistors R162, R163 and capacitor C117, the circuit can stabilize the output signal and adjust the output voltage to meet the needs of subsequent circuits. The filtering network composed of capacitor C118 and resistor R170 can effectively filter out high-frequency noise in the input signal, improving the signal quality and stability.

[0100] The resistor network (R164, R165, R166 and R167, R168, R169) is used to set the input bias voltage of the op amp to ensure that the op amp operates in the linear region.

[0101] On the auxiliary control board for power supply testing, this circuit primarily monitors and provides feedback on the input voltage, ensuring stable operation of the power supply system. By accurately monitoring the input voltage and comparing it with a reference voltage, the circuit can regulate and control the power supply output, ensuring stability and reliability under various operating conditions.

[0102] In the control protection circuit, terminal C1-1 is connected to GND1 via capacitor C128 and resistor R177 connected in parallel. Terminal C1-1 is connected to terminal CA1-1 and the drain of switch MOS106 via resistor R179. The gate of switch MOS106 is connected to terminal ENCC1-1 via resistor R182.

[0103] Terminal C1-2 is connected to GND1 via a capacitor C129 and a resistor R178 connected in parallel. Terminal C1-2 is connected to terminal CA1-2 and the drain of the switch tube MOS107 via a resistor R180. The gate of the switch tube MOS107 is connected to terminal ENCC1-2 via a resistor R181.

[0104] The source of the switch tube MOS107 is connected to the terminal C1-2 and to the pin 2 of the diode array ZD103. The pin 1 of the diode array ZD103 is connected to the source of the switch tube MOS106 and the terminal CC1-1. The pin 3 of the diode array ZD103 is connected to the GND1 terminal.

[0105] The switch tube MOS106 and the switch tube MOS107 are both AP3404MI, which are used for AC short-circuit protection, and the diode array ZD103 is ESDA25L.

[0106] The low-pass filter composed of capacitors C128, C129 and resistors R177, R178 filters out high-frequency noise in the input signal to ensure the stability and reliability of the input signal.

[0107] Switching transistors MOS106 and MOS107 control the on / off state of the circuit. When terminals ENCC1-1 and ENCC1-2 provide control signals, the MOS transistors conduct, allowing current to flow. When the control signals disappear, the MOS transistors turn off, cutting off the current. This prevents damage to the circuit from overvoltage and abnormal signals, ensuring stable operation of the power supply system.

[0108] In the power protection circuit, in the switch tube U107, pin VCC is connected to +3.3V1, and is connected to pin / OE, pin GND, and pin GND1 through capacitor C130. Pin Sel is connected to terminal ID-ONF1. Pin D+ is connected to terminal D+1 and pin 1 of the diode array ZD103. Pin D- is connected to terminal D-1 and pin 2 of the diode array ZD103. Pin 3 of the diode array ZD103 is connected to pin GND.

[0109] Pin HSD2+ is connected to pin 4 of port PD1, pin HSD2- is connected to pin 5 of port PD1, pin HSD1+ is connected to pin 6 of port PD1, pin HSD1- is connected to pin 7 of port PD1, pin 1 of port PD1 is connected to VBUS1, pin 2 of port PD1 is connected to terminal CC1-1, and pin 8 of port PD1 is connected to GND1.

[0110] The diode array ZD104 is an ESDA25L, which provides overvoltage and electrostatic protection. It quickly clamps overvoltage to ground, protecting subsequent circuits from damage. The switch U107 is an FSUSB42, which controls and manages the power output and input of the USB PD protocol, ensuring proper power negotiation and transmission. Port PD1 is an XH2.54A-8P.

[0111] In the first filtering circuit, the terminal VD+1 is connected to the terminal D+1 through the resistor R189, and the terminal VD+1 is connected to GND1 through the capacitor C133 and the resistor R190 connected in parallel, forming a low-pass filter.

[0112] The first filter circuit plays the role of signal conditioning, filtering and protection in the auxiliary control board, ensuring the quality and stability of the signal and providing reliable support for power supply testing.

[0113] In the second filtering circuit, terminal VD-1 is connected to terminal D-1 through resistor R191, and terminal VD-1 is connected to GND1 through capacitor C134 and resistor R192 connected in parallel, forming a low-pass filter to filter out high-frequency noise and improve signal quality.

[0114] The second filter circuit plays the role of signal conditioning, filtering and protection in the auxiliary control board to ensure the quality and stability of the signal.

[0115] In the signal modulation circuit, in the controller U108, pin D+ is connected to D+1 through resistor R183, pin D- is connected to D-1 through resistor R184, pin CC1 is connected to terminal CA1-1, pin CC2 is connected to terminal CA1-2, pin VDD is connected to +3.3V1 and connected to GND1 through capacitor R132, pin P0RT / DBG_N is connected to GND1 through resistor R185, pin ADDR / ORIENT is connected to GND1 through resistor R186, pin SDA is connected to terminal SDA1, and pin SCL is connected Terminal SCL1, pin INT is connected to terminal INT1.1, pin EN_N is connected to terminal EN_N1, pin VBUS is connected to the source of the switching tube MOS108, pin GND is connected to the GND1 end, and is connected to the gate of the switching tube MOS108 through the diode ZD105, pin GND is connected to the VBUS1 end through the capacitor C131, which is used to connect the power supply to be tested, the VBUS1 end is connected to the drain of the switching tube MOS108 through the resistor R188, and the drain of the switching tube MOS108 is connected to the switching tube MOS108 through the resistor R187.

[0116] The controller U108 is a HUSB238A protocol chip with its own AC input port, which is connected to a fast charging power source to control the power output amplitude. The diode ZD105 is 28V and the switch tube MOS108 is BSS183.

[0117] The secondary control board uses an external HUSB238A to implement PD3.1 functionality. Resistors R183 and R184 connect to D+1 and D-1, respectively, for the USB data line. The resistors limit current to prevent overcurrent damage and stabilize signal levels to ensure reliable data transmission.

[0118] The test module also includes a power measurement module, and the power measurement module also includes a power measurement circuit and a voltage-stabilized power supply circuit.

[0119] In the power measurement circuit, ACGND is connected to ACGND1 through resistor RB15. In relay BY102, pin 6 is connected to AC-L, pin 2 is connected to AC-N, pins 9 and 3 are connected to GND1.1, pins 7 and 10 are connected to the drain of switch tube MOS109, the source of switch tube MOS109 is connected to terminal V1 through resistor RB101, the source of switch tube MOS109 is connected to terminal +12V1, pin 8 is connected to pin 3 of port COM103 and the primary side input pin of current transformer T102, the primary side output pin of current transformer T102 is connected to pin 2 of T103, and pin 1 of port COM103 is connected to ACGND1.

[0120] Pin 4 of relay BY102 is connected to the primary input pin of current transformer T101, and the primary output pin of current transformer T101 is connected to pin 1 of port COM103, and is connected to pin 1 of voltage transformer T103 through resistors RB102, RB103, RB104, RB105, and RB106 connected in sequence;

[0121] The secondary side input pin of the current transformer T101 is connected to the secondary side output pin of the current transformer T101 and ACGND1 through the resistor RB109. The secondary side input pin of the current transformer T101 is connected to the pin IAP of the electric energy meter U111 through the resistor RB108. The secondary side output pin of the current transformer T101 is connected to the pin IAN of the electric energy meter U111 through the resistor RB110.

[0122] The pin IAP of the energy meter U111 is connected to the pin IAN of the energy meter U111 via the capacitors CC101 and CC102 connected in series, and one end of the capacitors CC101 and CC102 is connected to ACGND1;

[0123] The secondary side input pin of the current transformer T102 is connected to the secondary side output pin of the current transformer T102 and ACGND1 through the resistor RB112. The secondary side input pin of the current transformer T102 is connected to the pin IBP of the electric energy meter U111 through the resistor RB111. The secondary side output pin of the current transformer T102 is connected to the pin IBN of the electric energy meter U111 through the resistor RB103.

[0124] Pin IBP of the energy meter U111 is connected to pin IBN of the energy meter U111 via capacitors CC103 and CC104 connected in series. One end of the capacitors CC103 and CC104 is connected to ACGND1. Pin IBP of the energy meter U111 is connected to pin IBN of the energy meter U111 via a bidirectional breakdown diode TVS102.

[0125] Pin VP of the energy meter U111 is connected to pin 4 of the voltage transformer T103 via resistor RB107. Pin VP of the energy meter U111 is connected to pin 3 of the voltage transformer T103 and ACGND1 via capacitor CC105. Pin 4 of the voltage transformer T103 is connected to pin 3 of the voltage transformer T103 via resistor RB115.

[0126] In the energy meter U111, pin GND is connected to GND1.1, pin VREF is connected to GND1.1 through capacitor CC106, pin TX is connected to terminal ACRX1, pin RX is connected to terminal ACTX1, pin SCLK is connected to terminal ACSCLK1, pin SCSN is connected to terminal ACCSSN1, pin CLKI is connected to GND1.1, and is connected to terminal +3.3V1.1 through a parallel bidirectional breakdown diode TVS101 and capacitor CC111, pin INT2 is connected to terminal INT2.1, and pin VDD is connected to terminal +3.3V1.1.

[0127] Current transformers T101 and T102 are both DLHGQ, voltage transformer T103 is DYHGQ, energy meter U111 is HLW8211, bidirectional breakdown diode TVS102 is P0080BE, and bidirectional breakdown diode TVS101 is JEB03D3; current transformers T101 and T102 are respectively used to monitor the two channels of AC current, converting high current into low current proportionally so that energy meter U111 can safely and accurately measure the current size. Voltage transformer T103 is used to monitor AC voltage.

[0128] The electric energy meter U111 is a sampling chip used to receive signals from current transformers and voltage transformers, and perform calculations and processing to accurately measure parameters such as active power, apparent power, voltage, and current. It has multiple communication interfaces such as TX, RX, SCLK, and SCSN for exchanging data with other devices to achieve remote monitoring and data acquisition.

[0129] The bidirectional breakdown diodes TVS101 and TVS102 are used to protect circuits from overvoltage damage, ensuring the safety of energy meters and other components under abnormal voltage conditions.

[0130] When a short circuit or abnormality is detected at the input end of the power supply to be tested, a high level appears at the terminal V1, and the switch tube MOS109 is turned on to provide 12V voltage to pin 7 and pin 10 of the relay BY102 to make the relay work, and the switch of the relay BY102 is turned from pin 4 and pin 8 to pin 5 and pin 1, thereby disconnecting the power supply of the power supply to be tested, thereby realizing the protection function of the power supply to be tested.

[0131] In the voltage regulated power supply circuit, the terminal +12V1 is connected to the pin Vin and pin 4 of the voltage regulator U110 through the positively connected diode D101. The pin Vin of the voltage regulator U110 is connected to GND3.1 through the parallel capacitor CC107 and capacitor CC308. The pin -3.3V of the voltage regulator U110 is connected to the terminal +3.3V3.1 and is connected to GND3.1 through the parallel capacitor CC309 and capacitor CC310. The pin GND of the voltage regulator U110 is connected to GND3.1. The voltage regulator U110 is ME6216A10PG50.

[0132] The +12V1 voltage is converted to a stable +3.3V output through voltage regulator U110 to avoid voltage fluctuations, meet the power supply requirements of the power measurement modules, and ensure the normal operation and measurement accuracy of each module. In port COM104, pin 1 is connected to terminal +12V1, pin 2 is connected to GND1.1 through resistor RB114, pin 3 is connected to terminal ACTX1, pin 4 is connected to terminal ACRX1, pin 5 is connected to terminal INT2.1, pin 6 is connected to terminal V1, pin 7 is connected to terminal ACCSSN1, and pin 8 is connected to terminal ACSCLK1.

[0133] Port COM104 is 2.54. In the power measurement module, port COM104 is used to exchange data and transmit control signals with other devices or systems to ensure the coordinated operation of the entire test system.

[0134] A separate short-circuit test is performed between the auxiliary control board, MOS tube, and relay. The auxiliary control board and sampling chip U111 detect and calculate AC voltage, AC current, and AC power, and perform AC input power, no-load power consumption, and power factor (PF) product effectiveness testing.

[0135] The auxiliary control board and digital power monitor U102 sample and analyze DC voltage, current, and power to implement OCP overcurrent protection and VPP wave detection. The auxiliary control board controls the three MOS tubes of the protection circuit and signal modulation circuit to implement the forward and reverse insertion functions of D+, D-, C1, and C2.

[0136] In some embodiments, the control module includes a host computer and a main control module connected to each other;

[0137] like Figure 4 As shown, the main control module includes a first isolation circuit, a second isolation circuit and a main control board. The host computer is connected to the main control board through the first isolation circuit, and the main control board is connected to the corresponding test module through the output end of the second isolation circuit.

[0138] The main control board is used to receive the test data sent by the test module;

[0139] The host computer is used to configure test parameters for the test module through the main control board, and generate the test results corresponding to the test data;

[0140] The main control module further includes a filtering and voltage stabilizing circuit connected to the main control board, and the filtering and voltage stabilizing circuit is used to supply power to the main control module.

[0141] In the first isolation circuit, pin 1 of the RS485 port is connected to the GND485 terminal and the two pins GNDB of the isolator URS1, the GND485 terminal is connected to pin B of the isolator URS1 through a resistor R17, pin 1 of the RS485 port is connected to 485+5V and the pin VCCB of the isolator URS1 through a capacitor CRS1, the pin VCCB of the isolator URS1 is connected to pin A of the isolator URS1 through a resistor R15, pin 2 of the RS485 port is connected to pin B of the isolator URS1 through a resistor R19, pin B of the isolator URS1 is connected to pin A of the isolator URS1 through a resistor R16, pin 3 of the RS485 port is connected to pin A of the isolator URS1 through a resistor R18, and pin GNDB of the isolator URS1 is connected to the GND485 terminal;

[0142] Pin VDDA of isolator URS1 is connected to +3.3V and to the VSS terminal through capacitor C16. Pin GNDA and two GNDA pins of isolator URS1 are both connected to the VSS terminal. Pin RO of isolator URS1 is connected to terminal RX-B through resistor R11. Pin RE and pin DE of isolator URS1 are both connected to the VSS terminal through resistor R14. Pin RE of isolator URS1 is also connected to +3.3V through resistor R13 and to terminal RTD through resistor R10. Pin DI of isolator URS1 is connected to terminal TX-A through resistor R12.

[0143] The host computer and the main control board communicate with each other through the SR485 port.

[0144] During the operation of the first isolation circuit, electrical isolation is achieved between the RS485 bus and the main control board through the isolator URS1, preventing noise and interference on the RS485 bus from affecting the main control board, avoiding overvoltage and overcurrent on the RS485 bus from damaging the main control board, improving the reliability and safety of the system, and converting the differential signal on the RS485 bus into a logic level signal that can be processed by the main control board.

[0145] The VCCB pin of isolator URS1 is connected to 485+5V via capacitor CRS1, providing power to the isolated circuit and achieving power isolation. Resistor R15 and capacitor C16 are used for filtering, stabilizing the power supply voltage, and reducing the impact of power supply noise on the circuit.

[0146] Connect the RE and DE pins to +3.3V and VSS through resistors R13 and R14 to control the receive and transmit enable. Connect the RO pin to RX-B through resistor R11 to enable data reception; connect the DI pin to TX-A through resistor R12 to enable data transmission.

[0147] In the main control board, in the main control chip U2, pin L-TX / PA2 is connected to terminal TX-A, pin L-RX / PA3 is connected to terminal RX-B, pin L-RTD / PB1 is connected to terminal RTD, pin PC0 ADC12_IN10 is connected to terminal NT1, pin PC1ADC12_IN11 is connected to terminal NT2,

[0148] Pin PC4 / ADC2_IN5 is connected to terminal TX1, and pin PC5 / ADC2_IN11 is connected to terminal RX1.

[0149] Pin PF0 / OSC_IN is connected to pin PF1 / OSC_OUT through crystal oscillator Y1, pin PF0 / OSC_IN is connected to GNDA terminal through capacitor C20, and pin PF1 / OSC_OUT is connected to GNDA terminal through capacitor C21.

[0150] Pin NRST is connected to terminal NRST and connected to VSS terminal through capacitor C8.

[0151] Pin GNDA, pin NTGND, pin GND, pin VSS1, pin VSS2, and pin VSS3 are all connected to the GNDA terminal and connected to the terminal VSS through the filter element FB2. Pin BOOT0 / PB8 is connected to the terminal VSS through the resistor R1.

[0152] Pin PA15 connects to terminal RX2, pin RX3 / PB11 connects to terminal RX3, pin TX3 / PB10 connects to terminal TX3, pin RX4 / PC11 connects to terminal RX4, pin TX4 / PC10 connects to terminal TX4, pin TX2 / PD3 connects to terminal TX2,

[0153] Pin SWLCK-JICK-PA14 is connected to pin 5 of port CON1 and connected to VSS through resistor R3.

[0154] Pin SWDIO-JTMS / PA13 is connected to pin 4 of port CON1, and is connected to +3.3V and pin 1 of port CON1 through resistor R2. Pin 1 of port CON1 is connected to pin 2 of port CON1 and the VSS terminal through capacitor C7. Pin 3 of port CON1 is connected to terminal NRST, pin PD9 / FAN is connected to terminal FAN, pin VDDA and pin VREF+ are connected to VREEP, pins VDD3, VDD2, VDD1, and VDDA are all connected to the VDD terminal, and pin Vbat is connected to the VBAT terminal.

[0155] The main control chip U2 is STM32G431RBT6, and the model of port CON1 is 2.54A-5P, which is used to connect debugging tools or other external devices.

[0156] In the filter and voltage stabilization circuit, the VDD terminal is connected to the VSS terminal through the parallel capacitors C1, C2, and C3. The VDD terminal is also connected to +3.3V through the filter element FB1. The VREEP terminal is connected to the VSS terminal through the parallel capacitors C4 and C5. The VREEP terminal is also connected to +3.3V through the filter element FB4. The VBAT terminal is connected to the VSS terminal through the capacitor C6 and is connected to +3.3V through the filter element FB3.

[0157] Capacitors are used to filter out high-frequency noise and ripple in the power supply, and filtering elements further suppress high-frequency noise. Through the combination of capacitors and filtering elements, high-frequency noise and ripple in the power supply can be effectively filtered out, improving the stability and purity of the power supply, ensuring that the power supply voltage received by the main control chip U2 is stable, avoiding system instability or data errors caused by power supply fluctuations, protecting the main control board from interference and noise on the power line, and improving the system's anti-interference ability.

[0158] The filter element can suppress the surge current at the moment the power is turned on and protect the circuit from large current shocks.

[0159] Independent filtering of VDD, VREEP and VBAT provides filtering for different power pins respectively, ensuring the voltage stability of each power pin and meeting the strict requirements of the main control chip U2 for different power needs.

[0160] In some embodiments, the main control module further includes a temperature measurement circuit and a fan drive circuit;

[0161] The main control board is connected to the temperature measurement circuit and the fan drive circuit;

[0162] The temperature measurement circuit is used to collect temperature data of the test module, the main control board is used to generate a fan control instruction based on the temperature data, and the fan drive circuit is used to control the fan in response to the fan control instruction, and the fan acts on the test module.

[0163] In the temperature measurement circuit, terminal NT1 is connected to the VSS terminal through the parallel thermistor NT01 and capacitor C18, terminal NT1 is connected to +3.3V through resistor RT1, terminal NT2 is connected to the VSS terminal through the parallel thermistor NT02 and capacitor C19, terminal NT2 is connected to +3.3V through resistor RT2,

[0164] The thermistor is used to monitor temperature changes. Resistors RT1 and RT2 are used to provide bias current so that the thermistor can operate within a suitable voltage range. The capacitor is used to filter out high-frequency noise in the thermistor signal and improve the accuracy of temperature measurement.

[0165] In the second isolation circuit, terminal TX1 is connected to pin VI1 TX of isolator U105 through resistor R6. In isolator U105, pin VDDA is connected to VSS through capacitor C9, pin VO2 RX is connected to terminal RX1, pin VDDB is connected to +3.3V1, and pins GNDB and GND1 are connected through capacitor C105. Pin RX VO1 is connected to terminal RXD1, and pin TX VI2 is connected to terminal TXD1.

[0166] Terminal TX2 is connected to pin VI1 TX of isolator U205 through resistor R7. In isolator U205, pin VDDA is connected to VSS terminal through capacitor C10, pin VO2 RX is connected to terminal RX2, pin VDDB is connected to +3.3V1, and is connected to pin GNDB and GND2 terminal through capacitor C205. Pin RX VO1 is connected to terminal RXD2, and pin TX VI2 is connected to terminal TXD2.

[0167] Terminal TX3 is connected to pin VI1 TX of isolator U305 through resistor R8. In isolator U305, pin VDDA is connected to VSS terminal through capacitor C11, pin VO2 RX is connected to terminal RX3, pin VDDB is connected to +3.3V1, and is connected to pin GNDB and GND3 terminal through capacitor C305. Pin RX VO1 is connected to terminal RXD3, and pin TX VI2 is connected to terminal TXD13.

[0168] Terminal TX4 is connected to pin VI1 TX of isolator U405 through resistor R9. In isolator U405, pin VO2 RX is connected to terminal RX4, pin VDDB is connected to +3.3V1, and pin GNDB and GND4 are connected through capacitor C405. Pin RX VO1 is connected to terminal RXD4, and pin TX VI2 is connected to terminal TXD4.

[0169] Pins VDDA of isolator U105, VDDA of isolator U205, VDDA of isolator U305, and VDDA of isolator U405 are all connected to +3.3V. Pins GNDA of isolator U105, GNDA of isolator U205, GNDA of isolator U305, and GNDA of isolator U405 are all connected to VSS. Isolator U105, isolator U205, isolator U305, and isolator U405 are CA-IS3721-HS.

[0170] Each isolator electrically isolates the circuits on both sides during signal transmission, protecting the control circuit from interference on the communication lines while also preventing interference from entering the communication lines. Four sets of isolators correspond to four communication channels, each with its own isolation. This prevents interference between channels when multiple signals are transmitted simultaneously, ensuring the accuracy and stability of multi-channel communication. The control circuit can send signals via the VI1 TX pin. After isolation, the signals are received by the VO2 RX pin and passed to subsequent circuits, enabling remote control and monitoring of the power supply test process. Signals from other devices are received and responded to via the RX VO1 and TX VI2 pins. The four isolators support multi-channel data exchange and can simultaneously transmit and receive multiple signals. In complex power supply test systems, they can simultaneously monitor multiple power supply parameters and receive multiple feedback signals, enabling comprehensive monitoring and precise control of the entire system. The VDDA pin is connected to the +3.3V power supply and connected to the VSS terminal via a capacitor to filter out high-frequency noise and ripple, stabilize the power supply voltage, and provide reliable support for the proper operation of the isolator.

[0171] In the fan drive circuit, terminal FAN is connected to GND via resistors RF1 and RF2, connected in sequence. The connected end of resistors RF1 and RF2 is connected to the gate of MOS transistor QF1. The source of MOS transistor QF1 is connected to GND. The drain of MOS transistor QF1 is connected to IN+12V via a forward-connected diode DF1. IN+12V is connected to pin 1 of port FAIN and to pin 2 of port FAIN via parallel capacitors FC1 and FC2 to filter high-frequency noise and ripple in the power supply. Pin 2 of port FAIN is connected to the drain of MOS transistor QF1 via inductor FL1, forming an LC filter circuit. This further filters low-frequency noise and ripple in the power supply, making the output power smoother.

[0172] Terminal FAN serves as the input terminal of the fan drive signal. It controls the duty cycle based on the heating instruction of the MOS tube in the auxiliary control module, and controls FAIW and FTR to control the fan speed. The higher the temperature, the higher the speed.

[0173] The resistors RF1 and RF2 are connected to GND in sequence. The two resistors form a voltage divider circuit for adjusting the voltage applied to the gate of the MOS tube QF1, thereby controlling the conduction degree of the MOS tube.

[0174] By changing the input signal at terminal FAN or adjusting the resistance values ​​of resistors RF1 and RF2, the voltage at the gate of MOS transistor QF1 can be changed, thereby controlling the conduction level of the MOS transistor, adjusting the fan supply current, and thus controlling the fan speed. During power supply testing, the fan speed can be flexibly adjusted according to heat dissipation requirements to ensure good heat dissipation under different load conditions. Diode DF1 prevents the reverse electromotive force generated by the motor power failure during fan operation from impacting the circuit, protecting the MOS transistor and power supply from damage, and improving system reliability.

[0175] The filter circuit formed by capacitors FC1 and FC2 and inductor FL1 can effectively filter out noise and ripple in the power supply, providing a stable and pure power supply for the fan, ensuring stable operation of the fan and avoiding problems such as fan speed fluctuations or abnormal noise caused by power quality problems.

[0176] In some embodiments, when the power supply to be tested is connected to the test module, the host computer is further configured to:

[0177] Reading the test requirements of the power supply to be tested through the main control module and the test module;

[0178] According to the test requirements, the main control module is controlled to configure corresponding test parameters in the test module, where the test parameters are used to define the test mode, communication protocol and test current, and are displayed on a test page.

[0179] In actual execution, the host computer can read the basic test requirements of the power supply to be tested through communication between the main control module and the test module. The test requirements include the output voltage, current operating range (such as), frequency, load type and other working conditions of the test power supply, as well as the required test mode.

[0180] After reading the test requirements, the host computer configures the test parameters of each test module based on these requirements. Configuration items include test modes such as voltage and current regulation, communication protocols, and test current ranges. The configured test parameters are displayed on the test page of the graphical user interface (GUI), where users can view and further confirm them.

[0181] The setting of test parameters helps to ensure the accuracy and completeness of the test and avoid unnecessary deviations or errors.

[0182] During the test, the test module continuously collects test data from the output of the power supply under test and transmits the test data to the host computer through the main control module. The host computer processes the received test data, identifies the power characteristic parameters of the power supply, and further performs fault risk assessment.

[0183] In some embodiments, the test results include power supply performance and failure risk. When the host computer receives the test data, the host computer is further configured to:

[0184] Identifying the test data to obtain power characteristic parameters of the power supply to be tested;

[0185] Determining a fractional order according to the power supply characteristic parameters, so as to analyze an attenuation trend of the power supply to be tested according to the fractional order;

[0186] Constructing a membership function for the attenuation trend, performing fuzzy processing on the test data based on the membership function, and determining the variation probability and variation amplitude of the power supply to be tested;

[0187] The power supply performance and the failure risk are determined according to the variation probability and the variation amplitude.

[0188] In actual execution, after the host computer receives the test data, it preprocesses and identifies the test data through Fourier transform to extract the power characteristic parameters of the power supply under test. The power characteristic parameters include the output voltage, current, fluctuation, ripple, etc. of the power supply under test.

[0189] The attenuation trend is manifested as the change in voltage, frequency, etc. of the power supply output signal over time. The attenuation of the power supply output signal is described by fractional calculus.

[0190] The host computer calculates the fractional order according to the power supply characteristic parameters. The fractional order is related to the attenuation characteristics of the power supply under test. By analyzing the fractional order, the attenuation speed and attenuation stability of the power supply under test are evaluated to obtain the attenuation trend.

[0191] A membership function is constructed based on the attenuation trend to describe the degree of power supply attenuation. Through fuzzy processing, the membership function maps the power supply characteristic parameters to different membership values, including normal, moderate attenuation, and severe attenuation. This makes the judgment of power supply characteristics more flexible and can tolerate a certain amount of error.

[0192] After completing the fuzzy processing, the mutation probability and mutation amplitude are obtained, and a risk matrix is ​​constructed to divide the mutation probability and mutation amplitude into different intervals. Each interval corresponds to a specific risk level. The mutation probability indicates the possibility of a change in the power supply output characteristics, and the mutation amplitude indicates the size of the change.

[0193] Based on the risk level, a risk assessment is conducted on the power supply performance, including whether the power supply is stable under specific load and environmental conditions, and whether there is a potential failure risk.

[0194] The host computer determines the comprehensive performance indicators and failure risks of the power supply under test by comprehensively analyzing the variation probability, variation amplitude and fuzzified data. The power supply performance and failure risk can be presented in the form of specific scores or levels, such as good, medium, high failure risk, etc.

[0195] The power supply test circuit provided in this application condenses the functions of N types of instruments and meters currently used to detect power supply products into one device, including AC power meter, power supply power analyzer, oscilloscope, fast charging deception protocol, computer, short-circuit automatic protection meter and other related functions. All functions are fully integrated into one section to detect the power supply to be tested, achieving higher requirements, more accurate and shorter time for power supply product testing, while greatly reducing the investment cost of instruments and meters.

[0196] like Figure 5 As shown, the driving module 140 includes a voltage and current detection module, a signal processing circuit and a power control circuit.

[0197] In the voltage and current detection circuit, for the digital power monitor U102, pin CS is connected to GND1, pin MOSI is connected to terminal MOSI1, pin ALERT is connected to terminal 12C1, and is connected to the power supply +3.3V1 and pin VS through resistor R101, pin MISO is connected to terminal MISO1, pin SCLK is connected to terminal SCLK1, pin VS is connected to pin GND and GND1 through capacitor C101, pin GND is connected to pin VBUS through resistor R107, pin VBUS is connected to terminal CH1-VIN through resistors R106, R105, and R104 connected in sequence, pin IN- is connected to terminal IN-1 through resistor R103, pin IN- is connected to pin IN+ through capacitor C102, and pin IN+ is connected to terminal IN+1 through resistor R102; among them, the digital power monitor U102 is INA229.

[0198] The operation of the voltage and current detection circuit includes voltage monitoring and current monitoring.

[0199] In the voltage monitoring part, the VBUS pin is connected to the CH1-VIN terminal through multiple resistors to measure the bus voltage. The resistor divider configuration can convert the high voltage into a range suitable for monitoring; the VS pin is connected to the capacitor to GND1 to filter out power ripple and ensure measurement accuracy.

[0200] In the current monitoring part, the IN+ and IN- pins are connected to the two ends of the shunt resistor respectively to measure the current size. The combination of resistor R103 and capacitor C102 realizes filtering to ensure the stability of the signal for accurate current measurement.

[0201] The voltage and current detection circuit interacts with the auxiliary control board through SPI communication to send the monitored voltage and current data to the auxiliary control board. The connection between the ALERT pin and terminal 12C1 is used to provide an alarm function.

[0202] In the signal processing circuit, terminal pwmCC1 is connected to the positive input of op amp U103B via resistors R108 and R109, connected in sequence. The end of resistor R109 connected to resistor R108 is connected to GND1 via capacitor C103, which is used to divide the input signal and filter it to remove high-frequency noise. The other end of resistor R109 is connected to GND1 via capacitor C104, and the negative input of U103B is connected to the output of U103B, forming a voltage follower that buffers and isolates the input signal, preventing the signal source from being affected by the load.

[0203] Terminal CVin1 is connected to the positive input of op amp U103A, the positive power supply terminal of op amp U103A is connected to +5V1, the negative power supply terminal of op amp U103A is connected to GND1, terminal pwmCV1 is connected to the reverse input of op amp U103A through resistors R110, R111 and R112 connected in sequence, one end of resistor R111 connected to resistor R110 is connected to GND1 through capacitor C105, and the other end of resistor R111 is connected to GND1 through capacitor C106 for voltage division and filtering. The reverse input of op amp U103A is connected to capacitors C10 connected in sequence. 7 and resistor R114 are connected to pin B0 of the analog switch U104, the inverting input terminal of the operational amplifier U103A is also connected to pin B1 of the analog switch U104 through a parallel resistor R115 and capacitor C108, the inverting input terminal of the operational amplifier U103A is also connected to pin COM of the analog switch U104 and the output terminal of the operational amplifier U103A through capacitor C110, the GND pin of the analog switch U104 is connected to GND1, the VCC pin of the analog switch U104 is connected to the power supply +5V1 and is grounded through capacitor C109, and the SFB pin of the analog switch U104 is connected to port Adata1;

[0204] Pin COM of analog switch U104 is connected to the positive input terminals of op amp U106A, op amp U106B, op amp U106C, and op amp U106D respectively through resistor R116. The output terminal of op amp U103B is connected to the positive input terminal of op amp U106A. The negative input terminal of op amp U106A is connected to terminal 101-3 through resistor R117. The negative input terminal of op amp U106A is also connected to the output terminal of op amp U106A and terminal 101-1 through capacitor C111 and resistor R124 connected in parallel. The positive power supply terminal of op amp U106A is connected to +12V1 and to GND1 through capacitor C112. The negative power supply terminal of op amp U106A is connected to GND1.

[0205] The positive input terminal of the operational amplifier U106B is connected to GND1 via a resistor R119, the negative input terminal of the operational amplifier U106B is connected to the terminal 102-3 via a resistor R118, and the negative input terminal of the operational amplifier U106B is further connected to the output terminal of the operational amplifier U106B and the terminal 102-1 via a capacitor C113 and a resistor R125 connected in parallel;

[0206] The positive input terminal of the operational amplifier U106C is connected to GND1 via a resistor R121, the negative input terminal of the operational amplifier U106C is connected to the terminal 103-3 via a resistor R120, and the negative input terminal of the operational amplifier U106C is further connected to the output terminal of the operational amplifier U106C and the terminal 103-1 via a capacitor C114 and a resistor R126 connected in parallel;

[0207] The positive input terminal of the operational amplifier U106D is connected to GND1 via a resistor R123, the negative input terminal of the operational amplifier U106D is connected to the terminal 104-3 via a resistor R122, and the negative input terminal of the operational amplifier U106D is further connected to the output terminal of the operational amplifier U106D and the terminal 104-1 via a capacitor C115 and a resistor R127 connected in parallel;

[0208] Op amp U103B and op amp U103A are both RS622, analog switch U104 is DIO3157E, op amp U106A is TP2584A, op amp U106B is RS8752XK or TP24594, op amp U106C is TP2584C, and op amp U106D is TP2584D.

[0209] Op amps U106A, U106B, U106C, and U106D are used to further process the signal output by analog switch U104 to achieve signal amplification, comparison, and output drive functions. Op amps U103A and U103B are used to amplify and filter the input signal to remove noise and improve signal quality.

[0210] The analog switch U104 is used to switch between different input signals and select a specific signal path for processing. By controlling the input pin of the analog switch, different signal sources can be selected to connect to the subsequent operational amplifier circuit.

[0211] The signal processing circuit can simultaneously amplify, filter, and compare multiple input signals, such as pwmCC1, CVin1, and pwmCV1. By monitoring and comparing the output signals of different power supply channels, it ensures the stability and consistency of the power supply. The op amp and analog switch configuration isolates the signals, prevents mutual interference between different signal paths, removes high-frequency noise, and protects subsequent circuits from interference. The control pin of analog switch U104, such as SFB, connected to port Adata1 can be connected to a microcontroller or test system for automated signal switching and test control, improving test efficiency and accuracy.

[0212] In the power control circuit, terminal 101-1 is connected to the gate of the switch tube MOS101 through resistor R148, and the gate of the switch tube MOS101 is connected to GND1 through resistor R149; the drain of MOS101 is connected to terminal IN+1 through resistors R132, R131, R130, R129, and R128 connected in sequence. Terminal IN+1 is used for sampling and controlling the switch tube in the power control circuit; terminal 102-1 is connected to the gate of the switch tube MOS102 through resistor R150, and the gate of the switch tube MOS102 is connected to GND1 through resistor R151; the drain of MOS102 is connected to resistors R137, R136, R135, and R137 connected in sequence. 4. Resistor R133 is connected to terminal IN+1; terminal 103-1 is connected to the gate of MOS 103 via resistor R152, and the gate of MOS 103 is connected to GND1 via resistor R153; the drain of MOS 103 is connected to terminal IN+1 via resistors R142, R141, R140, R139, and R138, which are connected in sequence; terminal 104-1 is connected to the gate of MOS 104 via resistor R154, and the gate of MOS 104 is connected to GND1 via resistor R155; the drain of MOS 104 is connected to terminal IN+1 via resistors R147, R146, R145, R144, and R143, which are connected in sequence;

[0213] Terminal IN+1 is connected to terminal IN-1 via resistors R156 and 157 connected in sequence. Terminal IN+1 is also connected to terminal IN-1 via resistors R158 and 159 connected in sequence. Terminal IN-1 is connected to GND1.

[0214] The source of the switching tube MOS101, the source of the switching tube MOS102, the source of the switching tube MOS103, and the source of the switching tube MOS104 are all connected to pin 1 of the relay RY101, pin 2 of the relay RY101 is connected to terminal CH1-VIN, terminal IN-1 is connected to pin 3 of the relay RY101 through resistor R160, pin 4 of the relay RY101 is connected to GND1, pin 5 of the relay RY101 is connected to the drain of the switching tube MOS105, the source of the switching tube MOS105 is connected to +12V, and the gate of the switching tube MOS105 is connected to terminal KO1 through resistor R161;

[0215] In port CH1, pin 1 is connected to GND1 and pin 3 is connected to CH-VIN1;

[0216] Relay RY101 is KRELAY-5, and port CH1 is VH3.96A-3.

[0217] During the operation of the power control circuit, by controlling the gate voltage of the MOSFET, the output of each power supply can be independently controlled, and different loads can be powered and controlled separately; the relay RY101 is used to switch and control high-power loads or different power paths to ensure flexible power distribution; the resistor divider chain and feedback network are used to monitor the power supply output voltage and provide feedback signals to achieve closed-loop control, ensuring the stability and accuracy of the power supply output; by monitoring the drain voltage of the MOSFET, the load current and status can be evaluated to achieve load monitoring and protection; the configuration of MOSFET and resistor can provide overcurrent protection to prevent power supply overload damage; the coordinated operation of the relay and MOSFET can quickly disconnect the fault circuit and protect the system from short-circuit damage. The power loss of the power supply is tested by the heat generation of the loss current MOS101 and MOS102; the short-circuit protection test is performed by short-circuiting MOS103, and the voltage, overcurrent and overvoltage are detected and transmitted through U102. Pin 3 ALRT is connected to the auxiliary control board through terminal 12C1; the auxiliary control board controls the relay RY101 to perform short-circuit protection detection. When the terminal KO1 is at a high level, the switch tube MOS103 is in the on state, and the switch of the relay RY101 will be moved from pin 1 to pin 3. At this time, after the output end of the detection product is in a short-circuit state, KO1 returns to a low level and MOS103 is in the off state. The relay RY101 is moved from pin 3 back to the original pin 1. At this time, all the output parameters of the power supply to be tested are tested again to determine whether the power supply to be tested has a short-circuit protection function.

[0218] In power supply testing, this circuit can be used to test the output characteristics of multiple power supply channels and evaluate the performance of the power supply under different load conditions. By controlling the on and off state of the MOSFET, dynamic load conditions can be simulated to test the transient response and stability of the power supply. The gate control of the MOSFET and the relay switching can be automatically controlled by a microcontroller or test system to achieve an efficient power supply testing process.

[0219] The power supply test method provided in the embodiment of the present application can be executed by a power supply test circuit. In the embodiment of the present application, the power supply test method provided in the embodiment of the present application is described by taking the power supply test circuit executing the power supply test method as an example.

[0220] An embodiment of the present application also provides a power supply testing method.

[0221] like Figure 6 As shown, the power supply test method includes:

[0222] Step 610: Power the test module via the power supply module to the multiple power supply terminals;

[0223] Step 620: Configure test parameters for the test module through the control module to control the drive module to drive the test module to test the power supply to be tested, receive test data returned by the test module, and determine the test result of the power supply to be tested based on the test data.

[0224] In addition, the measured parameters and results of the power supply to be tested are automatically saved or uploaded to the designated storage location of the host computer.

[0225] According to the power supply testing method provided in the embodiment of the present application, a stable and adjustable multi-terminal power supply is provided by a power supply module, and an adaptive power supply is independently provided for different test modules; the control module configures and manages each test module separately, and each test module works independently, reducing mutual interference and mutual influence, and ensuring the accuracy of the test results; isolating each test module can eliminate current disturbances and noise defects.

[0226] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power supply test circuit, characterized in that: include: Power module, multiple test modules, control module and drive module; The power module includes a switching power supply circuit, which includes a power management circuit, a full-bridge drive circuit, and a transformer circuit connected in sequence. The transformer circuit provides multiple power supply terminals, each of which is connected to a corresponding test module. The test module is used to connect to the power supply to be tested; The control module is respectively connected to each of the test modules and the drive module, and the drive module is respectively connected to each of the test modules. The control module is used to configure test parameters for the test modules, so as to control the drive module to drive the test modules to test the power supply to be tested, receive test data returned by the test modules, and determine the test result of the power supply to be tested according to the test data; The control module includes a host computer and a main control module connected to each other; The main control module includes a first isolation circuit, a second isolation circuit and a main control board, the host computer is connected to the main control board via the first isolation circuit, and the main control board is connected to the corresponding test module via the output end of the second isolation circuit; The main control board is used to receive the test data sent by the test module; The host computer is used to configure test parameters for the test module through the main control board, and generate the test results corresponding to the test data; The main control module further includes a filter and voltage stabilizing circuit connected to the main control board, and the filter and voltage stabilizing circuit is used to supply power to the main control module; The test results include power supply performance and failure risk. When the host computer receives the test data, the host computer is further configured to: Identifying the test data to obtain power characteristic parameters of the power supply to be tested; Determining a fractional order according to the power supply characteristic parameters, so as to analyze an attenuation trend of the power supply to be tested according to the fractional order; Constructing a membership function for the attenuation trend, performing fuzzy processing on the test data based on the membership function, and determining the variation probability and variation amplitude of the power supply to be tested; The power supply performance and the failure risk are determined according to the variation probability and the variation amplitude.

2. The power supply test circuit according to claim 1, wherein: The full-bridge drive circuit includes a high-end arm and a low-end arm, the high-end arm includes transistors Q901 and Q902, the low-end arm includes MOS transistors Q903 and Q904, and the high-end arm is connected to the power management circuit; The transformer circuit includes a transformer T901 and a transformer T902, the primary circuit of the transformer T901 is connected to the low-end arm, the transformer T901 and the transformer T902 are connected in series resonance, and the secondary circuit of the transformer T901 and the secondary circuit of the transformer T902 are both used to provide the power supply end.

3. The power supply test circuit according to claim 2, wherein: The first end of the low-end arm is connected to pin 1 of the transformer T901 and pin 1 of the transformer T902, and the second end of the low-end arm is connected to pin 3 of the transformer T901 and pin 3 of the transformer T902. On the primary winding side of the transformer T901, pin 1 is connected to pin 3 via a capacitor C908 and a resistor R913 connected in series, and pin 2 of the transformer T901 is connected to terminal VDD1; On the secondary winding side of the transformer T901, pin 4 is connected to terminal 485b, pin 5 is connected to terminal 485AC, pin 6 is connected to GND2, pin 7 is connected to terminal AC2, pin 8 is connected to GND1, and pin 9 is connected to terminal AC1; On the primary winding side of the transformer T902, pin 1 is connected to pin 3 via a capacitor C909 and a resistor R914 connected in series, and pin 2 of the transformer T902 is connected to terminal VDD2; On the secondary winding side of the transformer T902, pin 4 is connected to GND4, pin 5 is connected to terminal AC4, pin 6 is connected to GND3, pin 7 is connected to terminal AC3, pin 8 is connected to terminal vss, and pin 9 is connected to terminal MCUA; Among them, the terminal AC1, the terminal AC2, the terminal AC3 and the terminal AC4 are the power supply terminals.

4. The power supply test circuit according to claim 3, wherein: The power supply module further includes a grounding circuit, which includes capacitors CY1, CY2, CY3, and CY4; The terminal GND1, the terminal GND2, the terminal GND3 and the terminal GND4 are connected to END via the capacitor CY1, the capacitor CY2, the capacitor CY3 and the capacitor CY4 respectively; The terminal GND1 , the terminal GND2 , the terminal GND3 , and the terminal GND4 are connected to the test circuits corresponding to the terminal AC1 , the terminal AC2 , the terminal AC3 , and the terminal AC4 , respectively.

5. The power supply test circuit according to claim 1, wherein: The main control module also includes a temperature measurement circuit and a fan drive circuit; The main control board is connected to the temperature measurement circuit and the fan drive circuit; The temperature measurement circuit is used to collect temperature data of the test module, the main control board is used to generate a fan control instruction based on the temperature data, and the fan drive circuit is used to control the fan in response to the fan control instruction, and the fan acts on the test module.

6. The power supply test circuit according to claim 1, wherein: When the power supply to be tested is connected to the test module, the host computer is further configured to: Reading the test requirements of the power supply to be tested through the main control module and the test module; According to the test requirements, the main control module is controlled to configure corresponding test parameters in the test module, where the test parameters are used to define the test mode, communication protocol and test current, and are displayed on a test page.

7. A power supply testing method, characterized in that: Applied to the power supply test circuit according to any one of claims 1 to 6, the method comprises: Powering the test module through multiple power supply terminals via the power module; The control module configures test parameters for the test module to control the drive module to drive the test module to test the power supply to be tested, receives test data returned by the test module, and determines the test result of the power supply to be tested according to the test data.

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