Floating-point number processing method and system applied to FPGA
By setting the decimal data output by the loop filter to 4-bit floating point accuracy in the FPGA and converting it into a fixed-point representation, the problem that FPGA cannot represent decimals is solved, and the design accuracy and resource utilization of the satellite navigation receiver tracking ring are improved.
Patent Information
- Application Number
- CN202410104496.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-07-25
Smart Images
Figure CN120371389A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and particularly to a floating-point processing method, system, storage medium, and electronic device applied to FPGA. Background Art
[0002] Different from DSP (Digital Signal Processing) and CPU (Central Processing Unit), FPGA (Field-Programmable Gate Array) does not have a dedicated processing unit or CPU. The process of program running is actually a process of processing a huge circuit. Arithmetic operations such as addition, subtraction, multiplication, and division need to be mapped into logic gates for synthesis. The underlying structure of FPGA determines that the data processing resources suitable for FPGA are oriented to integer or fixed-point data. To implement floating-point operations, relevant operation mechanisms need to be designed, or corresponding floating-point to fixed-point mapping relationships need to be designed.
[0003] In the design of the tracking loop of a satellite navigation receiver, it is necessary to feedback the result of the calculated loop filter to the front end, calculate and update the address of the pseudo-code, and the phase accuracy of the code offset will determine the design accuracy of the tracking loop.
[0004] Specifically, the result of the loop filter fed back is divided into an integer part and a decimal part. In the FPGA design, FPGA cannot directly represent decimals, so the minimum phase accuracy is 1, which greatly restricts the design accuracy of the tracking loop. Summary of the Invention
[0005] The purpose of this application is to provide a floating-point processing method, system, storage medium, and electronic device applied to FPGA, which can improve the calculation accuracy of the tracking loop.
[0006] To solve the above technical problems, this application provides a floating-point processing method applied to FPGA. The specific technical solution is as follows:
[0007] Obtain the output result of the loop filter; the output result includes integer data and decimal data;
[0008] Send the decimal data to a decimal phase accumulator, and set the floating-point precision of the decimal data to 4 bits;
[0009] Input the decimal data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the decimal data; accumulate the fixed-point representation in the decimal phase accumulator, and adjust the phase offset of the integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
[0010] Optionally, after inputting the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data, the method further includes:
[0011] Obtaining a frequency control word; the frequency control word is used to indicate the signal output frequency of the FPGA.
[0012] Optionally, after obtaining the frequency control word, the method further includes:
[0013] Applying the conversion formula to convert the frequency control word into a fixed-point representation.
[0014] Optionally, the conversion formula is:
[0015] I = floor(F * 2^N + 0.5);
[0016] wherein, I represents the converted fixed-point decimal data, F represents the fraction of the floating-point number, 0.5 is the rounding correction value, N represents the data bit width of the converted fixed-point data, and floor represents taking the integer downward.
[0017] Optionally, after inputting the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data, the method further includes:
[0018] Performing a multiplication operation on the fractional data and the frequency control word in the fractional phase accumulator by applying the fixed-point representation of the fractional data.
[0019] Optionally, performing the multiplication operation on the fractional data and the frequency control word in the fractional phase accumulator by applying the fixed-point representation of the fractional data includes:
[0020] Determining the type of digital signal logic processing unit included in the FPGA;
[0021] Inputting a shared multiplier factor in the operation formula into an intermediate port according to the type of digital signal logic processing unit; the intermediate port is used to perform operations with the two side ports respectively.
[0022] Optionally, if the digital signal logic processing unit is a DSP48A and the operation formula is (A + B) × C, inputting the shared multiplier factor in the operation formula into the intermediate port according to the type of digital signal logic processing unit includes:
[0023] Mapping the value of A to the high position of port A of the DSP48A;
[0024] Mapping the value of B to the low position of port D of the DSP48A;
[0025] Map the C value to the lower bits of port B of the multiplier.
[0026] This application also provides a floating-point processing system applied to an FPGA, including:
[0027] An output result acquisition module, configured to acquire the output result of the loop filter; the output result includes integer data and fractional data;
[0028] A floating-point precision setting module, configured to send the fractional data into a fractional phase accumulator and set the floating-point precision of the fractional data to 4 bits;
[0029] A floating-point conversion module, configured to input the fractional data into a conversion formula including the floating-point precision to obtain a fixed-point representation of the fractional data;
[0030] An offset adjustment module, configured to accumulate the fixed-point representation in the fractional phase accumulator and adjust the phase offset of the integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
[0031] Optionally, it further includes:
[0032] A frequency control acquisition module, configured to acquire a frequency control word; the frequency control word is used to indicate the signal output frequency of the FPGA.
[0033] Optionally, it further includes:
[0034] A frequency conversion module, configured to apply the conversion formula to convert the frequency control word into a fixed-point representation.
[0035] Optionally, the conversion formula is:
[0036] I = floor(F * 2^N + 0.5);
[0037] Wherein, I represents the converted fixed-point decimal data, F represents the fraction of the floating-point number, 0.5 is the rounding correction value, N represents the data bit width of the converted fixed-point data, and floor represents taking the integer downward.
[0038] Optionally, it further includes:
[0039] An accumulation module, configured to perform a multiplication operation of the fractional data and the frequency control word by applying the fixed-point representation of the fractional data in the fractional phase accumulator.
[0040] Optionally, the accumulation module includes:
[0041] A type determination unit, configured to determine the type of the digital signal logic processing unit included in the FPGA;
[0042] A data output unit, configured to input a shared multiplier factor in an operation formula to an intermediate port according to the digital signal logic processing unit type; the intermediate port is configured to perform operations with two side ports respectively.
[0043] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described above are implemented.
[0044] The present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory. When the processor calls the computer program in the memory, the steps of the method described above are implemented.
[0045] The present application provides a floating-point number processing method applied to an FPGA, including: obtaining an output result of a loop filter; the output result includes integer data and fractional data; sending the fractional data to a fractional phase accumulator, and setting a floating-point precision of the fractional data to 4 bits; inputting the fractional data into a conversion formula including the floating-point precision to obtain a fixed-point representation of the fractional data; performing accumulation on the fixed-point representation in the fractional phase accumulator, and adjusting a phase offset of an integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse a memory to obtain data corresponding to the output result.
[0046] After the present application receives the output result of the loop filter, for the fractional part thereof, its floating-point precision is set to 4 bits, and the 4-byte floating-point precision is no longer adopted. The corresponding floating-point to fixed-point mapping is 1-byte data, so that the design precision of the tracking loop is also increased to 1 / 2^4, which helps to perform fractional phase accumulation calculation in the fractional phase accumulator and adjust the phase offset of the integer phase counter, thereby greatly improving the design precision of the tracking loop.
[0047] The present application also provides a floating-point number processing system, a storage medium and an electronic device applied to an FPGA, which have the above beneficial effects and will not be elaborated here. Description of the Drawings
[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.
[0049] Figure 1 It is a flowchart of a floating-point number processing method applied to an FPGA provided by an embodiment of the present application;
[0050] Figure 2 A schematic diagram of a DSP48A structure provided by an embodiment of the present application;
[0051] Figure 3 A schematic diagram of a floating-point processing system structure applied to an FPGA provided by an embodiment of the present application. Specific implementation manners
[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0053] The tracking loop of a satellite navigation receiver is used to achieve real-time tracking of satellite signals by the receiver. The design of the tracking loop is a key link in implementing a Beidou satellite navigation receiver. It adopts a real-time high-precision tracking loop of a digital BDS receiver based on DSP+FPGA, and expounds the principle and method of loop tracking.
[0054] The tracking loop uses a second-order frequency-locked loop to assist a third-order phase-locked loop to complete high-precision stable closed-loop tracking of Beidou carrier signals. At the same time, the carrier is used to assist code loop tracking in real time, so as to complete real-time high-precision tracking of Beidou satellite signals. However, since the FPGA cannot directly represent decimals, the design accuracy of the tracking loop is restricted.
[0055] To solve the above problems, please refer to Figure 1 , Figure 1 A flowchart of a floating-point processing method applied to an FPGA provided by an embodiment of the present application. The method includes:
[0056] S101: Obtain the output result of the loop filter; the output result includes integer data and decimal data;
[0057] S102: Send the decimal data into a decimal phase accumulator, and set the floating-point precision of the decimal data to 4 bits;
[0058] S103: Input the decimal data into a conversion formula including the floating-point precision to obtain a fixed-point representation of the decimal data;
[0059] S104: Accumulate the fixed-point representation in the decimal phase accumulator, and adjust the phase offset of the integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
[0060] The loop filter is a linear low-pass filter used to filter out high-frequency components and noise in the output voltage. The design of the loop filter is crucial for the operation of the entire phase-locked loop. It not only filters out high-frequency components, but more importantly, it affects important parameters of the loop, such as phase noise, loop stability, and lock time.
[0061] First, obtain the output result of the loop filter. This output result is floating-point data, including integer data and fractional data. Generally, the floating-point data type occupies 4 bytes. The maximum bit width of the multiplier in FPFA is 18 bits. One floating-point multiplication operation between two floating-point numbers consumes 4 multiplier resources. The precision of 4-byte floating-point numbers is 1 / 2^32. This processing precision is much greater than the design precision of the satellite navigation receiver tracking loop, wasting and occupying too many resources. Therefore, a reasonable design of quantization is crucial. Therefore, in the embodiment of this application, the precision of the floating-point data in the fractional phase accumulator is designed to be 4 bits, and the floating-point to fixed-point mapping is 1-byte data with a precision of 1 / 2^4. The corresponding design precision of the tracking loop is also 1 / 2^4. The integer is mapped to 4 bits, and the data representation method after conversion is Fix8_4. Fix8_4 is a data representation method, where "Fix" represents a fixed-point number, "8" represents the total number of bits, and "4" represents the number of fractional bits. A number can be represented as an 8-bit fixed-point number, where 4 bits are the fractional bits. For example, the number 123.45 can be represented in the form of Fix8_4, that is, 00000123.4500.
[0062] Since there is no decimal point in binary, a special symbol can be used to represent the position of the decimal point. When converting floating-point data to fixed-point data, a conversion formula can be applied. The conversion formula is as follows:
[0063] I = floor(F * 2^N + 0.5);
[0064] Where, I represents the converted fixed-point decimal data, F represents the fraction of the floating-point number, 0.5 is the rounding correction value, N represents the data bit width of the converted fixed-point data, and floor represents taking the integer downward.
[0065] For example, use △ as a special symbol to represent the position of the decimal point. For the floating-point number 9.28, since the data bit width is 4 bits, that is, N = 4, according to the above formula, floor(0.28 * 16 + 0.5) = 4, then the converted binary fixed-point representation is 1001△0100. According to the formula, F = 4 / 16 = 0.25 is deduced.
[0066] Another example is the floating-point number 2.876. According to the above formula, floor(0.876 * 16 + 0.5) = 14, then the converted binary fixed-point representation is 0010△1110. According to the formula, F = 14 / 16 = 0.875 is deduced.
[0067] It can be seen that there is a certain error in converting floating-point data to fixed-point data, that is, there is a precision loss within a reasonable range during the conversion process. However, after converting from floating-point to fixed-point, it is easier to implement the functions of the fractional-phase accumulator and phase control.
[0068] After the embodiment of the present application receives the output result of the loop filter, for the fractional part thereof, its floating-point precision is set to 4 bits, and the 4-byte floating-point precision is no longer used. The corresponding floating-point to fixed-point mapping is 1-byte data, so that the design precision of the tracking loop is also improved to 1 / 2^4, which helps to perform fractional-phase accumulation calculations in the fractional-phase accumulator and adjust the phase offset of the integer-phase counter, thereby greatly improving the design precision of the tracking loop.
[0069] Based on the above embodiments, as a preferred embodiment, after inputting the fractional data into the conversion formula including the floating-point precision and obtaining the fixed-point representation of the fractional data, it further includes:
[0070] Obtain a frequency control word; the frequency control word is used to indicate the signal output frequency of the FPGA.
[0071] At the same time, after obtaining the frequency control word, apply the conversion formula to convert the frequency control word into a fixed-point representation.
[0072] The frequency control word is a parameter for controlling the oscillator frequency and is usually used to implement the frequency adjustment of the loop. It controls the output signal frequency by inputting the frequency control word into the oscillator. In the receiving loop, the frequency control word is used to track the frequency change of the received signal to ensure that the receiver can accurately demodulate the signal. The fractional-phase accumulator is a device for implementing phase tracking. By converting the phase error signal into a digital control signal, it adjusts the phase of the local signal. The fractional-phase accumulator can achieve fine-grained phase adjustment to adapt to the phase change of the received signal. In the receiving loop, the frequency control word and the fractional-phase accumulator work in cooperation. The frequency control word is mainly used to control the frequency tracking of the loop to ensure that the receiver can respond to the frequency change of the signal. The fractional-phase accumulator is used to implement phase tracking to adapt to the phase change of the signal and reduce the phase error. This collaborative working method can improve the performance of the receiving loop and ensure the accurate demodulation of the signal.
[0073] In order to improve the calculation accuracy, after obtaining the frequency control word, the conversion formula described in the above embodiments can also be applied to convert it into a fixed-point representation for participating in the calculation.
[0074] After inputting the fractional data into the conversion formula including the floating-point precision and obtaining the fixed-point representation of the fractional data, the fixed-point representation of the fractional data can be applied in the fractional phase accumulator to perform the multiplication operation of the fractional data and the frequency control word.
[0075] Based on the above embodiments, as a preferred implementation manner, when the frequency control word participates in the operation, there is a shared multiplier factor operation in the satellite navigation receiver tracking loop design, and the FPGA has dedicated multiplier resources, but the bit width is specified as 18 bits. After the above embodiments, 8-bit floating-point data can be obtained. Directly applying the multiplier will result in waste of resources. Therefore, the shared multiplier factor mapping method can be further adopted to complete the multiplier design of 2 groups of data at the same time. The specific implementation manner is as follows:
[0076] The first step: Determine the type of digital signal logic processing unit included in the FPGA;
[0077] The second step: Input the shared multiplier factor in the operation formula into the intermediate port according to the type of digital signal logic processing unit; the intermediate port is used to perform operations with the two side ports respectively.
[0078] For traditional operations to complete A*C and B*C, the FPGA needs to consume two DSP48A resources. The bit width of the multiplier resources is specified as 18 bits. In this way, 10 bits of data bits are in the idle operation state, consuming FPGA resources but not actually used. The traditional method consumes two DSP48A at a time, leaving 2*(36 - 8*2) = 40 bits unused.
[0079] See Figure 2 , Figure 2 FIG. is a schematic diagram of a DSP48A structure provided by an embodiment of the present application. Taking the digital signal logic processing unit as DSP48A as an example, assuming the operation formula is (A + B)×C, inputting the shared multiplier factor in the operation formula into the intermediate port according to the type of digital signal logic processing unit includes:
[0080] Map the A value to the high bit of port A of the DSP48A;
[0081] Map the B value to the low bit of port D of the DSP48A;
[0082] Map the C value to the low bit of port B of the multiplier.
[0083] This is because the C value is the factor for which both the A value and the B value need to perform multiplication calculations. Therefore, it is input to the intermediate port B, by Figure 2From the upper left corner port, it can be seen that port B is located between port A and port D. For other models of digital signal logic processing units, the input of specific data needs to refer to their operation manuals, which are not specifically defined here.
[0084] For the fixed-point data obtained through the above embodiments, a new mapping operation can be adopted for the shared multiplier factor. According to the operation rules of DSP48A, (A + B) * C can be realized. Specifically:
[0085] Map the value of A to the high 8 bits of port A of DSP48E.
[0086] Map the value of B to the low 8 bits of port D of DSP48E.
[0087] Map the value of C to the low 8 bits of port B of the multiplier.
[0088] Then the output result is 36 bits, where the high 16-bit result is A * C and the low 16-bit result is B * C. It can be seen that with the optimized mapping method, one operation consumes one DSP48A and only 4 bits are left unused.
[0089] As can be easily known from the above, the embodiments of the present application greatly improve the utilization rate of on-chip proprietary resources by adopting shared multiplier factor mapping.
[0090] Next, the floating-point processing system provided by the embodiments of the present application will be introduced. The floating-point processing system described below can be correspondingly referred to the floating-point processing method described above.
[0091] See Figure 3 , Figure 3 which is a schematic structural diagram of a floating-point processing system applied to FPGA provided by the embodiments of the present application. The present application also provides a floating-point processing system applied to FPGA, including:
[0092] An output result acquisition module for acquiring the output result of the loop filter; the output result includes integer data and fractional data.
[0093] A floating-point precision setting module for sending the fractional data into the fractional phase accumulator and setting the floating-point precision of the fractional data to 4 bits.
[0094] A floating-point conversion module for inputting the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data; accumulating the fixed-point representation in the fractional phase accumulator and adjusting the phase offset of the corresponding integer phase counter of the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
[0095] Based on the above embodiments, as a preferred embodiment, it further includes:
[0096] A frequency control acquisition module, configured to acquire a frequency control word; the frequency control word is used to indicate the signal output frequency of the FPGA.
[0097] Based on the above embodiments, as a preferred embodiment, it further includes:
[0098] A frequency conversion module, configured to convert the frequency control word into a fixed-point representation by applying the conversion formula.
[0099] Based on the above embodiments, as a preferred embodiment, the conversion formula is:
[0100] I = floor(F * 2^N + 0.5);
[0101] Wherein, I represents the converted fixed-point decimal data, F represents the floating-point fraction, 0.5 is the rounding correction value, N represents the data bit width of the converted fixed-point data, and floor represents taking the integer downward.
[0102] Based on the above embodiments, as a preferred embodiment, it further includes:
[0103] An accumulation module, configured to perform a multiplication operation on the fractional data and the frequency control word by applying the fixed-point representation of the fractional data in the fractional phase accumulator.
[0104] Based on the above embodiments, as a preferred embodiment, the accumulation module includes:
[0105] A type determination unit, configured to determine the type of digital signal logic processing unit included in the FPGA;
[0106] A data output unit, configured to input the shared multiplier factor in the operation formula to an intermediate port according to the type of digital signal logic processing unit; the intermediate port is used to perform operations with the two side ports respectively.
[0107] This application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, the steps provided in the above embodiments can be implemented. The storage medium may include: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.
[0108] This application also provides an electronic device, which may include a memory and a processor. A computer program is stored in the memory. When the processor calls the computer program in the memory, the steps provided in the above embodiments can be implemented. Of course, the electronic device may also include various network interfaces, power supplies and other components.
[0109] The various embodiments in the specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the identical or similar parts among the embodiments, reference can be made to each other. For the system provided in the embodiment, since it corresponds to the method provided in the embodiment, the description is relatively simple. For the relevant parts, reference can be made to the description of the method part.
[0110] In this text, specific examples are used to elaborate on the principle and implementation manner of this application. The descriptions of the above embodiments are only used to help understand the method of this application and its core idea. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
[0111] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.
Claims
1. A floating-point processing method applied to an FPGA, characterized in that Including: Obtain the output result of the loop filter; the output result includes integer data and fractional data; Send the fractional data into a fractional phase accumulator, and set the floating-point precision of the fractional data to 4 bits; Input the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data; Accumulate the fixed-point representation in the fractional phase accumulator, and adjust the phase offset of the integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
2. The floating-point number processing method according to claim 1, wherein After inputting the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data, it further includes: Obtain a frequency control word; the frequency control word is used to indicate the signal output frequency of the FPGA.
3. The floating-point number processing method according to claim 2, wherein After obtaining the frequency control word, it further includes: Apply the conversion formula to convert the frequency control word into a fixed-point representation.
4. The floating-point number processing method according to claim 3, wherein The conversion formula is: I = floor(F * 2^N + 0.5); Where, I represents the converted fixed-point decimal data, F represents the floating-point fraction, 0.5 is the rounding correction value, N represents the data bit width of the converted fixed-point data, and floor represents taking the integer downward.
5. The floating-point number processing method according to claim 2, wherein After inputting the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data, it further includes: Perform the multiplication operation of the fractional data and the frequency control word in the fractional phase accumulator by applying the fixed-point representation of the fractional data.
6. The floating-point number processing method according to claim 5, characterized in that, Performing the multiplication operation of the fractional data and the frequency control word in the fractional phase accumulator by applying the fixed-point representation of the fractional data includes: Determine the type of digital signal logic processing unit included in the FPGA; Input the shared multiplier factor in the operation formula into an intermediate port according to the type of digital signal logic processing unit; the intermediate port is used to perform operations with the two side ports respectively.
7. The floating-point number processing method according to claim 6, wherein If the digital signal logic processing unit is DSP48A and the operation formula is (A + B) × C, inputting the shared multiplier factor in the operation formula into an intermediate port according to the type of digital signal logic processing unit includes: Map the A value to the high bit of port A of the DSP48A; Map the B value to the low bit of port D of the DSP48A; Map the C value to the low bit of port B of the multiplier.
8. A floating-point processing system applied to an FPGA, characterized in that, Including: An output result acquisition module, used to obtain the output result of the loop filter; the output result includes integer data and fractional data; A floating-point precision setting module, used to send the fractional data into a fractional phase accumulator and set the floating-point precision of the fractional data to 4 bits; A floating-point conversion module, used to input the fractional data into a conversion formula including the floating-point precision to obtain the fixed-point representation of the fractional data; An offset adjustment module, used to accumulate the fixed-point representation in the fractional phase accumulator and adjust the phase offset of the integer phase counter corresponding to the integer data when overflow occurs; the phase offset is used to traverse the memory to obtain the data corresponding to the output result.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the floating-point number processing method applied to an FPGA as described in any one of claims 1-7.
10. An electronic device, characterized in that, It includes a memory and a processor. A computer program is stored in the memory, and when the processor calls the computer program in the memory, it implements the steps of the floating-point number processing method applied to an FPGA as described in any one of claims 1-7.