FPGA-ASIC (Field Programmable Gate Array-Application Specific Integrated Circuit) hybrid heterogeneous computing unit design method and device

Abstract

The invention relates to the technical field of computers, and provides an FPGA-ASIC hybrid heterogeneous computing unit design method and device, and the method comprises the steps: obtaining a plurality of target tasks and corresponding standard processing results; wherein the target tasks are tasks of the same type; obtaining the processing logic of each target task; generating a plurality of initial FPGA-ASIC (Field Programmable Gate Array-Application Specific Integrated Circuit) hybrid heterogeneous computing units on the basis of the processing logic; based on the target tasks and the standard processing results corresponding to the target tasks, evaluation indexes corresponding to the initial FPGA-ASIC hybrid heterogeneous computing units are generated; and determining a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units. According to the method, the FPGA-ASIC hybrid heterogeneous computing unit of a complex task can be designed.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a design method and device for an FPGA-ASIC hybrid heterogeneous computing unit. Background Art

[0002] With the continuous increase in the demand for high-performance computing and data processing, heterogeneous computing technology is gradually becoming a key solution in various applications (such as artificial intelligence, machine learning, image processing, and big data analysis, etc.). FPGA (Chinese name: Field Programmable Gate Array) and ASIC (Chinese name: Application Specific Integrated Circuit), as two mainstream hardware accelerators, each have unique advantages. FPGA, with its high flexibility and programmability, can quickly perform hardware customization and optimization for different tasks, while ASIC is a dedicated application hardware accelerator that can provide higher performance and lower power consumption. Combining these two technologies, the FPGA-ASIC hybrid heterogeneous computing unit emerges as the times require, aiming to improve computing efficiency through the optimal configuration of resources.

[0003] The design of existing FPGA-ASIC hybrid heterogeneous computing units usually relies on manual experience. With the increase in task complexity, this design method relying on manual experience is difficult to design FPGA-ASIC hybrid heterogeneous computing units for complex tasks. Summary of the Invention

[0004] This application provides a design method and device for an FPGA-ASIC hybrid heterogeneous computing unit to solve the problems raised in the above background art.

[0005] In a first aspect, this application provides a design method for an FPGA-ASIC hybrid heterogeneous computing unit, including: Obtaining a plurality of target tasks and their corresponding standard processing results; wherein, each of the target tasks is a task of the same type; Obtaining the processing logic of each of the target tasks; Generating a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic; Generating an evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results; Determining a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units.

[0006] In a possible implementation manner, the processing logic includes a plurality of subtask processing algorithms, and the generating a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic includes: Construct a set of hardware accelerators corresponding to each of the sub-task processing algorithms; wherein each of the sets of hardware accelerators includes an FPGA and an ASIC; Perform a Cartesian product operation on each of the sets of hardware accelerators to obtain a plurality of hardware accelerator combinations corresponding to the processing logic; For each of the hardware accelerator combinations, generate an initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the distribution state of the hardware accelerator combination in the processing logic.

[0007] In a possible implementation, the processing logic includes a plurality of task processing nodes, the task processing nodes include parallel task processing nodes and single task processing nodes, the parallel task processing nodes include a plurality of sub-task processing algorithms, the single task processing nodes include one sub-task processing algorithm, and the generating an initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the distribution state of the hardware accelerator combination in the processing logic includes: Determine whether there are multiple parallel task processing nodes that all include an FPGA in the distribution state; If so, generate a first initial FPGA-ASIC hybrid heterogeneous computing unit and a second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method; If not, generate a unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method.

[0008] In a possible implementation, the generating a first initial FPGA-ASIC hybrid heterogeneous computing unit and a second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method includes: Generate an FPGA virtual hardware accelerator corresponding to the processing logic based on the sub-task processing algorithms corresponding to the FPGAs in the distribution state in the processing logic, and for the sub-task processing algorithms corresponding to the ASICs in the distribution state in the processing logic, generate an ASIC virtual hardware accelerator corresponding to the sub-task processing algorithm; the FPGA virtual hardware accelerator corresponding to the processing logic and each of the ASIC virtual hardware accelerators constitute the first initial FPGA-ASIC hybrid heterogeneous computing unit; For each of the parallel task processing nodes, based on the sub-task processing algorithms corresponding to each FPGA in the distributed state, generate the FPGA virtual hardware accelerator corresponding to the parallel task processing node, and for the sub-task processing algorithms corresponding to each ASIC in the distributed state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerators corresponding to each of the parallel task processing nodes and the ASIC virtual hardware accelerators constitute the second initial FPGA-ASIC hybrid heterogeneous computing unit.

[0009] In a possible implementation manner, generating the unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the preset FPGA-ASIC hybrid heterogeneous computing unit generation method includes: Based on the sub-task processing algorithms corresponding to each FPGA in the distributed state in the processing logic, generate the FPGA virtual hardware accelerator corresponding to the processing logic, and for the sub-task processing algorithms corresponding to each ASIC in the distributed state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerator corresponding to the processing logic and the ASIC virtual hardware accelerators constitute the unique initial FPGA-ASIC hybrid heterogeneous computing unit.

[0010] In a possible implementation manner, generating the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results includes: For each of the initial FPGA-ASIC hybrid heterogeneous computing units, construct the virtual computing unit corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit, and based on the virtual computing unit, execute each of the target tasks respectively to obtain the processing result information corresponding to each of the target tasks, and generate the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks.

[0011] In a possible implementation manner, the processing result information includes the processing result, the processing duration, and the energy consumption. Generating the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks includes: For each of the target tasks, determine whether the processing result corresponding to the target task is consistent with the standard processing result; If there is any processing result corresponding to the target task that is inconsistent with the standard processing result, determine that the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit is 0; If the processing results corresponding to all the target tasks are consistent with the standard processing results, generate the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit; where is the evaluation index, represents target tasks, represents the th target task's processing duration, represents the th target task's energy consumption, is the weight coefficient corresponding to the processing duration, is the weight coefficient corresponding to the energy consumption.

[0012] In a second aspect, the present application provides an FPGA-ASIC hybrid heterogeneous computing unit design device, including: A first acquisition module, configured to acquire a plurality of target tasks and their corresponding standard processing results; where each of the target tasks is a task of the same type; A second acquisition module, configured to acquire the processing logic of each of the target tasks; A first generation module, configured to generate a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic; A second generation module, configured to generate the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results; A determination module, configured to determine the target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units.

[0013] The present application provides a method and apparatus for designing an FPGA-ASIC hybrid heterogeneous computing unit. The method includes: obtaining a plurality of target tasks and their corresponding standard processing results; where each of the target tasks is a task of the same type; obtaining the processing logic of each of the target tasks; generating a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic; generating an evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results; and determining a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units. On the one hand, this method generates a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic and standard processing results of each of the target tasks, and optimally selects according to the evaluation index of each of the initial FPGA-ASIC hybrid heterogeneous computing units, realizing the design of the target FPGA-ASIC hybrid heterogeneous computing unit according to the actual requirements of the target task, ensuring the accuracy of the calculation result of the target FPGA-ASIC hybrid heterogeneous computing unit while taking into account the computing efficiency and power consumption. On the other hand, this method helps to design the FPGA-ASIC hybrid heterogeneous computing unit for complex tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 It is a schematic flowchart of the method for designing an FPGA-ASIC hybrid heterogeneous computing unit provided by an embodiment of the present application; Figure 2 It is a schematic block diagram of the structure of the device for designing an FPGA-ASIC hybrid heterogeneous computing unit provided by an embodiment of the present application; Figure 3 It is a schematic block diagram of the structure of the terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0017] The flowcharts shown in the accompanying drawings are only illustrative examples, not necessarily including all content and operations / steps, nor necessarily executed in the order described. For example, some operations / steps can be decomposed, combined, or partially merged, so the actual execution order may change based on the actual situation.

[0018] It should also be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0019] It should be further understood that the term "and / or" used in the specification of this application and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0020] The following will describe in detail some embodiments of this application in conjunction with the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0021] Please refer to Figure 1 , Figure 1 , which is a schematic flowchart of the FPGA-ASIC hybrid heterogeneous computing unit design method provided by the embodiment of this application. As Figure 1 shown, the FPGA-ASIC hybrid heterogeneous computing unit design method provided by the embodiment of this application includes steps S1 to S6.

[0022] Step S1: Obtain multiple target tasks and their corresponding standard processing results; wherein, each of the target tasks is a task of the same type.

[0023] It should be noted that the execution subject of the embodiment of this application is an FPGA-ASIC hybrid heterogeneous computing unit design device.

[0024] Specifically, for tasks of the same type, an engineer designs multiple target tasks, processes each of the target tasks to obtain the standard processing results corresponding to each of the target tasks, and uploads each of the target tasks and their corresponding standard processing results to the FPGA-ASIC hybrid heterogeneous computing unit design device, so that the FPGA-ASIC hybrid heterogeneous computing unit design device can obtain multiple target tasks and their corresponding standard processing results.

[0025] Step S2: Obtain the processing logic of each of the target tasks.

[0026] Specifically, since each of the target tasks belongs to the same type of task, the processing logics corresponding to each of the target tasks are the same. An engineer designs the processing logics corresponding to each of the target tasks and uploads the designed processing logics to the FPGA-ASIC hybrid heterogeneous computing unit design device, so that the FPGA-ASIC hybrid heterogeneous computing unit design device can obtain the processing logics.

[0027] Step S3: Generate a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics.

[0028] Specifically, the processing logic includes a plurality of subtask processing algorithms, and step S3 includes the following steps: Construct a set of hardware accelerators corresponding to each of the subtask processing algorithms; wherein each set of hardware accelerators includes an FPGA and an ASIC; specifically, each of the subtask processing algorithms corresponds to a {FPGA, ASIC} set; Perform a Cartesian product operation on each of the sets of hardware accelerators to obtain a plurality of combinations of hardware accelerators corresponding to the processing logic; wherein the Cartesian product operation refers to all possible combinations of extracting one element from each of multiple sets. For example, performing a Cartesian product operation on {FPGA, ASIC}, {FPGA, ASIC}, and {FPGA, ASIC} results in {FPGA, FPGA, FPGA}, {FPGA, FPGA, ASIC}, {FPGA, ASIC, FPGA}, {FPGA, ASIC, ASIC}, {ASIC, FPGA, FPGA}, {ASIC, FPGA, ASIC}, {ASIC, ASIC, FPGA}, {ASIC, ASIC, ASIC}; For each of the combinations of hardware accelerators, generate an initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on the distribution state of the combination of hardware accelerators in the processing logic.

[0029] It can be understood that the method provided in step S3 can generate various possible combinations of hardware accelerators by performing a Cartesian product operation on multiple sets of hardware accelerators, which helps to achieve precise design of the hardware accelerators corresponding to each subtask processing algorithm.

[0030] Among them, the processing logic includes multiple task processing nodes, the task processing nodes include parallel task processing nodes and single task processing nodes, the parallel task processing nodes include multiple sub-task processing algorithms, and the single task processing nodes include one sub-task processing algorithm. Generating the initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the corresponding distribution state in the processing logic includes the following steps: Determine whether there are multiple parallel task processing nodes including FPGAs in the distribution state; If so, generate the first initial FPGA-ASIC hybrid heterogeneous computing unit and the second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method; If not, generate the unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method.

[0031] Among them, generating the first initial FPGA-ASIC hybrid heterogeneous computing unit and the second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on a preset FPGA-ASIC hybrid heterogeneous computing unit generation method includes the following steps: Generate the FPGA virtual hardware accelerator corresponding to the processing logic based on the sub-task processing algorithms corresponding to the FPGAs in the distribution state in the processing logic, and for the sub-task processing algorithms corresponding to the ASICs in the distribution state in the processing logic, generate the corresponding ASIC virtual hardware accelerators based on the sub-task processing algorithms; the FPGA virtual hardware accelerator corresponding to the processing logic and each of the ASIC virtual hardware accelerators constitute the first initial FPGA-ASIC hybrid heterogeneous computing unit; it can be understood that the first initial FPGA-ASIC hybrid heterogeneous computing unit includes one FPGA and multiple ASICs; For each of the parallel task processing nodes, based on the sub-task processing algorithms corresponding to each FPGA in the distributed state for the parallel task processing node, generate the FPGA virtual hardware accelerator corresponding to the parallel task processing node, and for the sub-task processing algorithms corresponding to each ASIC in the distributed state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerators corresponding to each of the parallel task processing nodes and the ASIC virtual hardware accelerators constitute the second initial FPGA-ASIC hybrid heterogeneous computing unit; it can be understood that the second initial FPGA-ASIC hybrid heterogeneous computing unit includes multiple FPGAs and multiple ASICs.

[0032] Among them, generating the unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the preset FPGA-ASIC hybrid heterogeneous computing unit generation method includes the following steps: Based on the sub-task processing algorithms corresponding to each FPGA in the distributed state in the processing logic, generate the FPGA virtual hardware accelerator corresponding to the processing logic, and for the sub-task processing algorithms corresponding to each ASIC in the distributed state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerator corresponding to the processing logic and the ASIC virtual hardware accelerators constitute the unique initial FPGA-ASIC hybrid heterogeneous computing unit.

[0033] It can be understood that the method of generating the initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the distributed state corresponding to the hardware accelerator combination in the processing logic improves the diversity of the initial FPGA-ASIC hybrid heterogeneous computing unit and helps to achieve the precise design of the target FPGA-ASIC hybrid heterogeneous computing unit.

[0034] Step S4, generate the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results.

[0035] Specifically, step S4 includes the following steps: For each of the initial FPGA-ASIC hybrid heterogeneous computing units, construct the virtual computing unit corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit, and based on the virtual computing unit, execute each of the target tasks respectively to obtain the processing result information corresponding to each of the target tasks, and generate the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks.

[0036] Among them, the processing result information includes a processing result, a processing duration, and energy consumption. Generating an evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks includes: For each of the target tasks, determine whether the processing result corresponding to the target task is consistent with the standard processing result; If there is any target task whose processing result is inconsistent with the standard processing result, determine that the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit is 0; If the processing results corresponding to all the target tasks are consistent with the standard processing results, then Generate the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit; where is the evaluation index, represents target tasks, represents the processing duration corresponding to the th target task, represents the energy consumption corresponding to the th target task, is the weight coefficient corresponding to the processing duration,

[0037] It can be understood that the method provided in step S4 can accurately measure the performance of each initial FPGA-ASIC hybrid heterogeneous computing unit by generating an evaluation index corresponding to each initial FPGA-ASIC hybrid heterogeneous computing unit based on each of the target tasks and their corresponding standard processing results. The evaluation index takes into account the accuracy of the processing result, the processing duration, and the energy consumption, and can comprehensively reflect the performance of the initial FPGA-ASIC hybrid heterogeneous computing unit when executing the target tasks. This comprehensive evaluation method helps to ensure the optimal configuration and resource allocation of the target FPGA-ASIC hybrid heterogeneous computing unit. Step S5, determine the target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units.

[0038] Specifically, determine the initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the largest evaluation index as the target FPGA-ASIC hybrid heterogeneous computing unit.

[0039] The method provided in this embodiment, on the one hand, generates multiple initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics and standard processing results of the target tasks, and optimally selects according to the evaluation indexes of the initial FPGA-ASIC hybrid heterogeneous computing units, realizing the design of the target FPGA-ASIC hybrid heterogeneous computing unit according to the actual requirements of the target task, ensuring the accuracy of the calculation results of the target FPGA-ASIC hybrid heterogeneous computing unit while taking into account the computing efficiency and power consumption. On the other hand, this method helps to design the FPGA-ASIC hybrid heterogeneous computing unit for complex tasks.

[0040] Please refer to Figure 2 , Figure 2 which is a schematic block diagram of the structure of the FPGA-ASIC hybrid heterogeneous computing unit design device 100 provided in the embodiment of the present application. As Figure 2 shown, the FPGA-ASIC hybrid heterogeneous computing unit design device 100 provided in the embodiment of the present application includes: A first acquisition module 110, configured to acquire a plurality of target tasks and their corresponding standard processing results; wherein, each of the target tasks is a task of the same type.

[0041] A second acquisition module 120, configured to acquire the processing logics of the target tasks.

[0042] A first generation module 130, configured to generate a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics.

[0043] A second generation module 140, configured to generate evaluation indexes corresponding to the initial FPGA-ASIC hybrid heterogeneous computing units based on the target tasks and their corresponding standard processing results.

[0044] A determination module 150, configured to determine a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation indexes corresponding to the initial FPGA-ASIC hybrid heterogeneous computing units.

[0045] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described device and each module can refer to the processes in the foregoing embodiment of the FPGA-ASIC hybrid heterogeneous computing unit design method, and will not be elaborated herein.

[0046] The FPGA-ASIC hybrid heterogeneous computing unit design device 100 provided in the above embodiment can be implemented in the form of a computer program, and the computer program can run on a terminal device 200 as Figure 3 shown.

[0047] Please refer toFigure 3 , Figure 3 is a schematic block diagram of the structure of the terminal device 200 provided by an embodiment of the present application. The terminal device 200 includes a processor 201 and a memory 202. The processor 201 and the memory 202 are connected through a device bus 203. Among them, the memory 202 may include a non-volatile storage medium and an internal memory.

[0048] The non-volatile storage medium can store a computer program. The computer program includes program instructions. When the program instructions are executed by the processor 201, the processor 201 can be enabled to execute any of the above FPGA-ASIC hybrid heterogeneous computing unit design methods.

[0049] The processor 201 is used to provide computing and control capabilities to support the operation of the entire terminal device 200.

[0050] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 201, the processor 201 can be enabled to execute any of the above FPGA-ASIC hybrid heterogeneous computing unit design methods.

[0051] Those skilled in the art can understand that Figure 3 the structure shown in is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the terminal device 200 involved in the solution of the present application. The specific terminal device 200 may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0052] It should be understood that the processor 201 may be a central processing unit (CPU), and the processor 201 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0053] Among them, in some embodiments, the processor 201 is used to run the computer program stored in the memory to implement the following steps: Obtain multiple target tasks and their corresponding standard processing results; where each of the target tasks is a task of the same type; Obtain the processing logics of the respective target tasks; Generate a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics; Generate evaluation indices corresponding to the respective initial FPGA-ASIC hybrid heterogeneous computing units based on the respective target tasks and their corresponding standard processing results; Determine a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation indices corresponding to the respective initial FPGA-ASIC hybrid heterogeneous computing units.

[0054] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the terminal device 200 described above can refer to the process of the foregoing FPGA-ASIC hybrid heterogeneous computing unit design method, and will not be elaborated herein.

[0055] An embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by one or more processors, the one or more processors are caused to implement the FPGA-ASIC hybrid heterogeneous computing unit design method provided by the embodiment of the present application.

[0056] Wherein, the computer-readable storage medium may be an internal storage unit of the foregoing embodiment of the terminal device 200, such as a hard disk or memory of the terminal device 200. The computer-readable storage medium may also be an external storage device of the terminal device 200, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped with the terminal device 200.

[0057] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or substitutions within the technical scope disclosed by the present application, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A design method for an FPGA-ASIC hybrid heterogeneous computing unit, characterized in that, Including: Obtain multiple target tasks and their corresponding standard processing results; wherein, each of the target tasks is a task of the same type; Obtain the processing logics of each of the target tasks; Generate multiple initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics; Generate evaluation indices corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results; Determine a target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation indices corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units.

2. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 1, wherein The processing logic includes multiple sub-task processing algorithms, and the generating multiple initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logic includes: Construct a set of hardware accelerators corresponding to each of the sub-task processing algorithms; wherein, each set of hardware accelerators includes an FPGA and an ASIC; Perform a Cartesian product operation on each set of hardware accelerators to obtain multiple combinations of hardware accelerators corresponding to the processing logic; For each combination of hardware accelerators, generate an initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on the distribution state of the combination of hardware accelerators in the processing logic.

3. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 2, wherein The processing logic includes multiple task processing nodes, the task processing nodes include parallel task processing nodes and single task processing nodes, the parallel task processing nodes include multiple sub-task processing algorithms, and the single task processing nodes include one sub-task processing algorithm. The generating an initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on the distribution state of the combination of hardware accelerators in the processing logic includes: Determine whether there are multiple parallel task processing nodes that all include FPGAs in the distribution state; If so, generate a first initial FPGA-ASIC hybrid heterogeneous computing unit and a second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on a preset method for generating an FPGA-ASIC hybrid heterogeneous computing unit; If not, generate a unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on a preset method for generating an FPGA-ASIC hybrid heterogeneous computing unit.

4. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 3, wherein The generating a first initial FPGA-ASIC hybrid heterogeneous computing unit and a second initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the combination of hardware accelerators based on a preset method for generating an FPGA-ASIC hybrid heterogeneous computing unit includes: Generate the FPGA virtual hardware accelerator corresponding to the processing logic based on the sub-task processing algorithms corresponding to each FPGA in the distribution state in the processing logic, and for the sub-task processing algorithms corresponding to each ASIC in the distribution state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerator corresponding to the processing logic and each of the ASIC virtual hardware accelerators constitute the first initial FPGA-ASIC hybrid heterogeneous computing unit; For each of the parallel task processing nodes, generate the FPGA virtual hardware accelerator corresponding to the parallel task processing node based on the sub-task processing algorithms corresponding to each FPGA in the distribution state in the parallel task processing node, and for the sub-task processing algorithms corresponding to each ASIC in the distribution state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerators corresponding to each of the parallel task processing nodes and each of the ASIC virtual hardware accelerators constitute the second initial FPGA-ASIC hybrid heterogeneous computing unit.

5. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 3, wherein The generation of the unique initial FPGA-ASIC hybrid heterogeneous computing unit corresponding to the hardware accelerator combination based on the preset FPGA-ASIC hybrid heterogeneous computing unit generation method includes: Generate the FPGA virtual hardware accelerator corresponding to the processing logic based on the sub-task processing algorithms corresponding to each FPGA in the distribution state in the processing logic, and for the sub-task processing algorithms corresponding to each ASIC in the distribution state in the processing logic, generate the corresponding ASIC virtual hardware accelerator based on the sub-task processing algorithms; the FPGA virtual hardware accelerator corresponding to the processing logic and each of the ASIC virtual hardware accelerators constitute the unique initial FPGA-ASIC hybrid heterogeneous computing unit.

6. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 1, wherein The generation of the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results includes: For each of the initial FPGA-ASIC hybrid heterogeneous computing units, construct the virtual computing unit corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit, and respectively execute each of the target tasks based on the virtual computing unit to obtain the processing result information corresponding to each of the target tasks, and generate the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks.

7. The FPGA-ASIC hybrid heterogeneous computing unit design method according to claim 6, characterized in that The processing result information includes the processing result, the processing duration, and the energy consumption. The generation of the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit based on the processing result information corresponding to each of the target tasks includes: For each of the target tasks, determine whether the processing result corresponding to the target task is consistent with the standard processing result; If there is any processing result corresponding to the target task that is inconsistent with the standard processing result, determine that the evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit is 0; If the processing results corresponding to each of the target tasks are all consistent with the standard processing results, then generate an evaluation index corresponding to the initial FPGA-ASIC hybrid heterogeneous computing unit; where is the evaluation index, represents target tasks, represents the th processing duration corresponding to the target task, represents the th energy consumption corresponding to the target task, is the weight coefficient corresponding to the processing duration, is the weight coefficient corresponding to the energy consumption.

8. A design device for an FPGA-ASIC hybrid heterogeneous computing unit, characterized in that, Including: The first acquisition module is used to acquire a plurality of target tasks and their corresponding standard processing results; wherein, each of the target tasks is a task of the same type; The second acquisition module is used to acquire the processing logics of the target tasks; The first generation module is used to generate a plurality of initial FPGA-ASIC hybrid heterogeneous computing units based on the processing logics; The second generation module is used to generate the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units based on each of the target tasks and their corresponding standard processing results; The determination module is used to determine the target FPGA-ASIC hybrid heterogeneous computing unit based on the evaluation index corresponding to each of the initial FPGA-ASIC hybrid heterogeneous computing units.

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