Data processing method, cache subsystem and multiprocessor system

Abstract

The invention provides a data processing method, a cache subsystem and a multiprocessor system.The data processing method comprises the steps that in response to a first sniffing request in a sniffing request queue, address conflict checking is conducted on the first sniffing request according to at least one write request from a first processor; wherein the first sniffing request is a sniffing request from an interconnection bus, and the second processor is connected with the first processor through the interconnection bus; if a target write request in the at least one write request has an address conflict with the first sniffing request, determining whether the target write request meets a data delivery condition; and if the target write request satisfies a data delivery condition, transmitting request data of the target write request to the first sniffing request of the sniffing request queue. The communication delay of cross-processor communication in the multiprocessor system can be effectively shortened, and the performance of the multiprocessor system is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, a cache subsystem, and a multi-processor system. Background Art

[0002] Multi-processor systems have been widely used due to their high performance, high scalability, etc. A multi-processor system may include multiple processors and a memory, and the multiple processors share the memory space. For a processor, each processor may include at least one core. Each processor has its own cache, and the cache of the processor can cache the data in the memory for the processor to access quickly.

[0003] However, the reading and writing of their respective caches by different processors may cause the same data to be inconsistent in the caches of different processors. How to optimize the performance of the multi-processor system while ensuring the cache consistency of multiple processors is still an important direction for the current technological development. Summary of the Invention

[0004] To overcome the problems existing in the related art, embodiments of the present disclosure propose a data processing method, a cache subsystem, and a multi-processor system. Through the data processing method proposed by the present disclosure, the communication delay of cross-processor communication in the multi-processor system can be effectively shortened, and the performance of the multi-processor system can be improved.

[0005] According to a first aspect of the embodiments of the present disclosure, a data processing method is provided, and the method includes:

[0006] In response to a first snooping request in a snooping request queue, perform an address conflict check on the first snooping request according to at least one write request in a first processor; wherein, the first snooping request is a snooping request from an interconnection bus, a second processor is connected to the first processor through the interconnection bus; the first processor is any processor of the multi-processor system, and the second processor is any processor in the multi-processor system except the first processor;

[0007] If there is a target write request in at least one write request that has an address conflict with the first snooping request, determine whether the target write request meets the data forwarding condition;

[0008] If the target write request meets the data forwarding condition, transfer the request data of the target write request to the first snooping request in the snooping request queue.

[0009] According to a second aspect of the embodiments of the present disclosure, a cache subsystem is provided, which is applied to a multi-processor system, and the cache subsystem includes:

[0010] A snooping request queue for storing first snooping requests from an interconnect bus; the first processor is any processor in a multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; the second processor is connected to the first processor via an interconnect bus;

[0011] A conflict check circuit, connected to the snooping request queue, for performing an address conflict check on the first snooping requests according to at least one write request from the first processor;

[0012] A data forwarding circuit, connected to the conflict check circuit and the snooping request queue, for determining whether a target write request in at least one write request satisfies a data forwarding condition if there is an address conflict between the target write request and the first snooping requests; and if the target write request satisfies the data forwarding condition, transferring the request data of the target write request to the first snooping requests.

[0013] According to a third aspect of the embodiments of the present disclosure, there is provided a multiprocessor system, including:

[0014] A plurality of processors, connected to each other via an interconnect bus, and each processor includes a cache subsystem according to the second aspect of the embodiments of the present disclosure.

[0015] The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

[0016] In the data processing method proposed by the embodiments of the present disclosure, by performing an address conflict check on at least one write request in the first processor and the first snooping requests from the interconnect bus in the snooping request queue, in the case where there is a target write request in at least one write request that has an address conflict with the first snooping requests, by determining whether the target write request satisfies the data forwarding condition, so that when the target write request satisfies the data forwarding condition, the data forwarding circuit is used to transfer the request data of the target write request to the first snooping requests, without waiting for the target write request to be executed before executing the first snooping requests. In this way, while ensuring data consistency between multiple processors, it is also possible to achieve a fast response of the first processor to the first snooping requests, effectively shortening the communication delay of cross-processor communication, realizing efficient interconnection between multiple processors in a multiprocessor system, and improving the performance of the multiprocessor system.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0019] Figure 1 It is a partial structural schematic diagram of a cache subsystem shown according to an exemplary embodiment;

[0020] Figure 2 It is a flowchart of a data processing method shown according to an exemplary embodiment Figure 1 ;

[0021] Figure 3 It is an overall architecture schematic diagram of a cache subsystem shown according to an exemplary embodiment;

[0022] Figure 4 It is an architecture schematic diagram of a snooping buffer shown according to an exemplary embodiment;

[0023] Figure 5 It is a flowchart of a data processing method shown according to an exemplary embodiment Figure 2 ;

[0024] Figure 6 It is a flowchart of a data forwarding process shown according to an exemplary embodiment. Detailed Description of the Embodiments

[0025] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0026] With the rapid development of multi-core processor technology, the number of processor cores in modern computer systems is constantly increasing, making the cache coherence problem particularly important. Cache coherence means that the caches among multiple processor cores (i.e., cores) should maintain consistency, ensuring that the modification of data by one processor core can be promptly known to other processor cores, thus avoiding problems such as inconsistent data seen between processor cores, data loss, and calculation errors. To achieve cache coherence, the industry has proposed and widely adopted various protocols and methods. Among them, common cache coherence protocols include the Modified Exclusive Shared Invalid (MESI) protocol, the Modified Owned Exclusive Shared Invalid (MOESI) protocol, the Modified Shared Invalid (MSI) protocol, etc. The MESI protocol is one of the basic protocols for maintaining cache coherence. It ensures consistency by maintaining four states for each cache block. The MOESI protocol adds an owned state on the basis of MESI, which is used to indicate that the cache block has been modified but is shared among multiple caches.

[0027] In practical applications, the AMBA (Advanced Microcontroller Bus Architecture) protocol also plays an important role in the design of multi-core systems. The AMBA protocol was proposed by ARM Company with the aim of improving the communication efficiency among various components in the system. The AMBA protocol includes multiple sub-protocols, such as the ACE (Advanced Microcontroller Bus Architecture Coherency Extension), etc. It supports high-bandwidth and low-latency data transmission and can work in coordination with cache coherence protocols. The ACE protocol provides support for burst transmission and cache coherence operations, enabling the effective maintenance of data sharing and consistency in a multi-core processor environment. The AR, AW, and AC channels it provides can also well couple the read-write and snooping paths within the cluster. The CHI (Coherent Hub Interface) protocol is the fifth-generation protocol of AMBA and an evolved version of the ACE protocol. It completes all information transmissions in the form of packets and is used to solve the data consistency problem among multiple processors. The CHI protocol aims to achieve scalability and can build small, medium, or large systems. These systems use multiple components, ranging from processor clusters, graphics processors, and memory controllers to I / O bridges, PCI Express (PCIe) subsystems, and the interconnect itself.

[0028] With the continuous increase in computing needs, especially in large-scale parallel computing and distributed systems, cache consistency technology faces new challenges. How to optimize performance while ensuring data consistency is still an important direction for current technology development.

[0029] In the current processor architecture, the ACE protocol is usually used to achieve cache consistency and data sharing within a cluster (i.e., between multiple cores of a processor). The ACE protocol provides efficient cache consistency support for multi-core processors and is particularly suitable for communication within a single cluster. However, the application of the ACE protocol in a multi-cluster environment (i.e., a multi-processor system) faces many challenges. First, the ACE protocol has a large number of signal ports, which makes it incapable of directly supporting efficient interconnection between multiple clusters. Specifically, the complexity and high overhead of the ACE protocol lead to a significant increase in communication delay when data is transmitted across clusters, which in turn affects the overall performance of the system. In this case, relying solely on the ACE protocol is difficult to meet the needs of multi-cluster systems for high-performance and low-latency data communication. The CHI protocol is specifically designed to support efficient communication between multiple clusters, can provide better bandwidth and latency performance between different clusters, and is suitable for complex multi-processor system architectures. Its flexible architectural design enables CHI to effectively manage cross-cluster data sharing and consistency maintenance, ensuring smooth collaboration between clusters. Therefore, in modern processor design, it is particularly important to achieve conversion between ACE and CHI. By implementing this conversion, the processor can switch freely under different workloads and application scenarios, making full use of the advantages of the ACE protocol within the cluster, and seamlessly switch to the CHI protocol when cross-cluster communication is required to ensure data consistency and efficient transmission. However, the current processor cache subsystem design has not yet implemented the conversion from the ACE protocol to the CHI protocol. This gap limits the performance improvement of multi-cluster systems and hinders the realization of efficient multi-cluster interconnection.

[0030] Based on this, the present disclosure provides a cache subsystem, see Figure 1 , Figure 1 FIG. 1 is a partial structural diagram of a cache subsystem according to an exemplary embodiment. The cache subsystem 100 may include:

[0031] The sniff request queue 110 is used to store a first sniff request from an interconnect bus; the first processor is any processor of a multi-processor system, and the second processor is any processor in the multi-processor system except the first processor; the second processor is connected to the first processor via an interconnect bus;

[0032] A conflict check circuit 120, connected to the sniff request queue 110, for performing an address conflict check on the first sniff request according to at least one write request from the first processor;

[0033] The data forwarding circuit 130 is connected to the conflict check circuit 120 and the snooping request queue 110, and is configured to determine whether a target write request satisfies the data forwarding condition if there is an address conflict between the target write request and the first snooping request in at least one write request; if the target write request satisfies the data forwarding condition, the request data of the target write request is transmitted to the first snooping request.

[0034] It should be noted that the cache subsystem shown in the embodiments of the present disclosure can be applied to a multi-processor system, which may include multiple processors, and each processor includes a cache subsystem. Here, the first processor can be any one of the processors in the multi-processor system, and the second processor can be any one of the processors in the multi-processor system other than the first processor, and the second processor is connected to the first processor through an interconnection bus.

[0035] The cache subsystem may include a snooping request queue, a conflict check circuit, and a data forwarding circuit.

[0036] The snooping request queue is configured to receive at least one first snooping request sent by the interconnection bus and store at least one first snooping request.

[0037] Here, the first snooping request is a snooping request from the interconnection bus, and the first snooping request can be used to request to obtain the first data in the cache of the first processor.

[0038] The first snooping request is sent by the interconnection bus to the first processor after receiving a data processing request sent by the second processor. It can be understood that the second processor can send a data processing request to the interconnection bus. When the interconnection bus discovers that the data requested by the data processing request is stored in the cache of the first processor based on the data processing request, the interconnection bus can send a first snooping request to the first processor to request to obtain the first data in the cache of the first processor in the multi-processor system.

[0039] It should be noted that each processor may include a cache, and the cache of the processor is used to store data accessible by the processor. The cache of the processor may include multiple cache lines, which can be used to store the data copied by the processor from the memory and record the status of the data. In a multi-processor system, the caches of the first processor and the second processor may include the same cache line, but the data stored in the same cache line in the first processor and the second processor must be the same. Moreover, in order to maintain the consistency of the data in the caches of multiple processors in the multi-processor system, when any one of the multiple processors needs to perform a write operation on a certain cache line in the cache, it is necessary to ensure that only the cache of this processor contains this cache line during the write operation, and the caches of other processors do not contain this cache line; or, it is necessary to ensure that the status of this cache line in other processors is set to invalid before the write operation.

[0040] When the data requested to be processed by the second processor is stored in the cache of the first processor, the interconnection bus may send a first snooping request to the first processor to request to obtain the first data in the cache of the first processor, so as to send the first data to the second processor for the second processor to perform corresponding processing.

[0041] The conflict check circuit may be connected to the snooping request queue, and is used to read the first snooping request in the snooping request queue and perform an address conflict check on the first snooping request based on at least one write request from the first processor.

[0042] Here, the write request from the first processor may be a write request that the first processor is ready to send through the interconnection bus. In some embodiments, the write request may be a write request from the secondary cache of the first processor.

[0043] It should be noted that the cache of the first processor may include a primary cache and a secondary cache. The write requests from the first processor may include write requests from the primary cache and write requests from the secondary cache. Among them, the write request from the primary cache is used to request to write the requested data back to the secondary cache, and the requested data will not be retained in the primary cache. The write request from the secondary cache is used to request to write the requested data back to the memory through the interconnection bus, and the requested data will not be retained in the secondary cache.

[0044] The snooping request queue of the first processor may store multiple first snooping requests. The conflict check circuit may read the first snooping requests in the snooping request queue in sequence and perform an address conflict check on the first snooping requests according to at least one write request from the first processor to determine whether there is an address conflict between the first snooping requests and the write requests of the first processor.

[0045] It should be noted that if the address of the first data requested by the first sniffing request is the same as the address of the requested data of the write request, it can be determined that there is an address conflict between the first sniffing request and the write request of the first processor. If the address of the first data requested by the first sniffing request is different from the address of the requested data of the write request, it can be determined that there is no address conflict between the first sniffing request and the write request of the first processor.

[0046] In some embodiments, the conflict check circuit can perform address conflict checks on all requests that the first processor needs to process. In one example, the conflict check circuit can perform address conflict checks on read requests from the cores of the first processor, write requests from the cores of the first processor, second sniffing requests from the secondary cache of the first processor, write requests being processed in the bus interface unit of the first processor, and first sniffing requests from the second processor.

[0047] The data forwarding circuit can be connected to the conflict check circuit and the sniffing request queue. When the conflict check circuit determines that there is a target write request in at least one write request that has an address conflict with the first sniffing request, the data forwarding circuit determines whether the target write request meets the data forwarding condition according to the storage location of the target write request. When it is determined that the target write request meets the data forwarding condition, the requested data of the write request is directly passed to the first sniffing request, so that there is no need to wait until the target write request is executed before executing the first sniffing request.

[0048] In the embodiments of the present disclosure, the cache subsystem of the processor may include a sniffing request queue, a conflict check circuit, and a data forwarding circuit. The conflict check circuit is used to perform address conflict checks on at least one write request in the first processor and the first sniffing request from the interconnect bus in the sniffing request queue. Thus, when there is a target write request in at least one write request that has an address conflict with the first sniffing request, the data forwarding circuit is used to determine whether the target write request meets the data forwarding condition, so that when the target write request meets the data forwarding condition, the requested data of the target write request is passed to the first sniffing request, without waiting until the target write request is executed before executing the first sniffing request. In this way, it can not only maintain data consistency between multiple processors, but also achieve a fast response of the first processor to the first sniffing request, effectively shortening the communication delay of cross-processor communication, realizing efficient interconnection between multiple processors in a multi-processor system, and improving the performance of the multi-processor system.

[0049] In some embodiments, as Figure 1 shown, the cache subsystem further includes:

[0050] A write request queue 140 for storing at least one write request and the requested data of the write request; the write requests stored in the write request queue 140 are write requests to be executed or being executed;

[0051] A write request buffer 150 for storing at least one write request and the request data of the write request; the write requests stored in the write request buffer 150 are write requests to be transmitted to the write request queue.

[0052] A snooping buffer 160 is also used for storing at least one write request and the request data of the write request; the write requests stored in the snooping buffer 160 are write requests to be transmitted to the write request buffer.

[0053] The data forwarding circuit 130 is connected to the write request queue 140, the write request buffer 150, and the snooping buffer 160, and is used to transfer the request data of the target write request that meets the data forwarding condition in the write request queue 140, the write request buffer 150, or the snooping buffer 160 to the first snooping request.

[0054] In the embodiments of the present disclosure, the cache subsystem may include a write request queue, a write request buffer, and a snooping buffer.

[0055] The write request queue can be used to store at least one write request and the request data of the write request. The write requests stored in the write request queue can be write requests to be executed or being executed.

[0056] In some embodiments, the write request to be executed can be understood as a write request that will be sent through the interconnect bus soon. In some embodiments, the write request being executed can be understood as a write request that has been sent through the interconnect bus but has not received a response yet.

[0057] The write request buffer can be used to store at least one write request and the request data of the write request. The write requests stored in the write request buffer can be write requests to be transmitted to the write request queue.

[0058] It should be noted that since the write request queue can store a limited number of write requests and the request data of the write requests, when the write request queue is full, the write requests can be temporarily stored in the write request buffer so that when there is free space in the write request queue, the write requests in the write request buffer can be transmitted to the write request queue to wait for sending.

[0059] The snooping buffer can be used to store at least one write request and the request data of the write request. The write requests stored in the snooping buffer are write requests to be transmitted to the write request buffer.

[0060] The target write request that meets the data forwarding condition can be the target write request whose request data is stored in the write request queue, the write request buffer, or the snooping buffer.

[0061] It should be noted that during the process of data forwarding using the data forwarding circuit, the data sources of the forwarded data mainly include three sources, namely, the request data of the write requests in the write request queue, the request data of the write requests in the write request buffer, and the request data of the write requests in the snooping buffer. Therefore, the data forwarding circuit can be connected to the write request queue, the write request buffer, and the snooping buffer, so as to transfer the request data of the target write request that meets the data forwarding conditions in the write request queue, the write request buffer, or the snooping buffer to the first snooping request.

[0062] In some embodiments, when it is determined that the target write request meets the data forwarding conditions and the target write request is stored in the snooping buffer, the data forwarding circuit can obtain the request data of the target write request from the snooping buffer and transfer it to the first snooping request.

[0063] In some embodiments, when it is determined that the target write request meets the data forwarding conditions and the target write request is stored in the write request buffer, the data forwarding circuit can obtain the request data of the target write request from the write request buffer and transfer it to the first snooping request.

[0064] In some embodiments, when it is determined that the target write request meets the data forwarding conditions and the target write request is stored in the write request queue, the data forwarding circuit can obtain the request data of the target write request from the write request queue and transfer it to the first snooping request.

[0065] In the embodiments of the present disclosure, by connecting the data forwarding circuit to the write request queue, the write request buffer, and the snooping buffer, so that when the target write request meets the data forwarding conditions, the request data of the target write request that meets the data forwarding conditions in the write request queue, the write request buffer, or the snooping buffer is transferred to the first snooping request, thereby realizing the data forwarding of the request data of the target write request that meets the data forwarding conditions inside the first processor, and further realizing the fast response of the first processor to the first snooping request initiated by the second processor, effectively shortening the communication delay of cross-processor communication.

[0066] An embodiment of the present disclosure provides a data processing method. Refer to Figure 2 , Figure 2 which is a flowchart of a data processing method shown according to an exemplary embodiment. Figure 1 . Among them, the data processing method may include the following steps:

[0067] Step S201, in response to a first snooping request in the snooping request queue, perform an address conflict check on the first snooping request according to at least one write request within the first processor; wherein, the first snooping request is a snooping request from an interconnect bus, the second processor is connected to the first processor through the interconnect bus; the first processor is any processor in a multi-processor system, and the second processor is any processor in the multi-processor system other than the first processor;

[0068] Step S202, if there is a target write request in at least one write request that has an address conflict with the first snooping request, determine whether the target write request meets the data forwarding condition;

[0069] Step S203, if the target write request meets the data forwarding condition, transfer the request data of the target write request to the first snooping request in the snooping request queue.

[0070] It should be noted that the data processing method shown in the embodiments of the present disclosure can be applied to the cache subsystem of a multi-processor system. The multi-processor system may include multiple processors, and each processor includes a cache subsystem. The first processor in the embodiments of the present disclosure may be any processor in the multi-processor system, and the second processor may be any processor in the multi-processor system other than the first processor. The second processor is connected to the first processor through an interconnect bus.

[0071] In step S201, inside the first processor, in response to the first snooping request in the snooping request queue, the first processor may perform an address conflict check on the first snooping request according to at least one write request within the first processor.

[0072] Here, the first snooping request is a snooping request from an interconnect bus, and the first snooping request may be used to request to obtain the first data in the cache of the first processor. The snooping request queue may store at least one first snooping request issued by the interconnect bus.

[0073] Here, the first snooping request is sent by the interconnect bus to the first processor after receiving a data processing request sent by the second processor. It can be understood that the second processor may send a data processing request to the interconnect bus. When the interconnect bus discovers that the data requested by the data processing request is stored in the cache of the first processor based on this data processing request, the interconnect bus may send a first snooping request to the first processor to request to obtain the first data in the cache of the first processor of the multi-processor system. It should be noted that each processor may include a cache, and the cache of the processor is used to store data for the processor to access. Usually, the first processor may copy the data to be accessed from the memory shared by multiple processors to its own cache to process the data in the cache.

[0074] The cache of a processor may include multiple cache lines, which can be used to store the data copied by the processor from the memory and record the status of the data.

[0075] In a multi-processor system, the caches of the first processor and the second processor may include the same cache line, but the data stored in the same cache line in the first processor and the second processor must be the same. Moreover, in order to maintain the consistency of the data in the caches of multiple processors in the multi-processor system, when any one of the multiple processors needs to perform a write operation on a certain cache line in the cache, it is necessary to ensure that only the cache of this processor contains this cache line during the write operation, and the caches of other processors do not contain this cache line; or, it is necessary to ensure that the status of this cache line in other processors is set to invalid before the write operation.

[0076] At least one write request in the first processor may be a write request that the first processor is ready to send through the interconnection bus, and this write request may be a write request from the secondary cache of the first processor.

[0077] It should be noted that the cache of the first processor may include a primary cache and a secondary cache. The write requests from the first processor may include write requests from the primary cache and write requests from the secondary cache. Among them, the write request from the primary cache is used to request to write the requested data back to the secondary cache, and the requested data will not be retained in the primary cache. The write request from the secondary cache is used to request to write the requested data back to the memory through the interconnection bus, and the requested data will not be retained in the secondary cache.

[0078] In some embodiments, the first processor may perform an address conflict check on all requests that need to be processed by the first processor. Among them, all requests that need to be processed by the first processor may include, but are not limited to, read requests from the core of the first processor, write requests from the core of the first processor, second snooping requests from the secondary cache of the first processor, write requests being processed in the bus interface unit of the first processor, and first snooping requests from the interconnection bus.

[0079] In some embodiments, the address conflict check for the first snooping request may be implemented by the conflict check circuit of the first processor.

[0080] In step S202, if there is a target write request in at least one write request that has an address conflict with the first snooping request, the first processor may determine whether the storage location of the target write request meets the data forwarding condition to determine whether to perform data forwarding processing on the requested data of the target write request.

[0081] It should be noted that if there is an address conflict between the target write request and the first snooping request, according to the rules of the ACE protocol, the target write request will be processed first. After the target write request is processed, the first snooping request will be processed. However, according to the rules of the CHI protocol, the first snooping request will be processed first. Due to the differences in the rules of the ACE protocol and the CHI protocol, system deadlocks are likely to occur when there is an address conflict between the target write request and the first snooping request, which makes the system unable to continue.

[0082] To avoid system deadlocks, the first processor can determine whether the request data of the target write request can be transferred from the temporary storage of the request data to the first snooping request. If the request data of the target write request can be transferred to the first snooping request, it can be determined that the target write request meets the data forwarding condition, and thus the request data of the target write request can be processed for data forwarding when there is an address conflict between the target write request and the first snooping request. If the request data of the target write request cannot be transferred to the first snooping request, it can be determined that the target write request does not meet the data forwarding condition, and there is no need to process the request data of the target write request for data forwarding.

[0083] In some embodiments, if the request data of the target write request is stored in the write request queue, the write request buffer, or the snooping buffer, the request data can be transferred to the first snooping request through the data forwarding circuit, and the target write request meets the data forwarding condition.

[0084] In step S203, if the target write request meets the data forwarding condition, the request data of the target write request can be transferred to the first snooping request in the snooping request queue, so that there is no need to wait until the target write request is executed before executing the first snooping request.

[0085] In some embodiments, the data forwarding circuit can be used to implement the data forwarding process of the request data of the target write request.

[0086] The embodiments of the present disclosure perform address conflict checks on at least one write request in the first processor and the first snooping request from the interconnect bus in the snooping request queue. In the case where there is a target write request with an address conflict with the first snooping request among at least one write request, by determining whether the target write request meets the data forwarding condition, so that when the target write request meets the data forwarding condition, the data forwarding circuit is used to transfer the request data of the target write request to the first snooping request, without waiting until the target write request is executed before executing the first snooping request. In this way, while ensuring data consistency among multiple processors, it can also achieve a fast response of the first processor to the first snooping request, effectively shortening the communication delay of cross-processor communication, realizing efficient interconnection among multiple processors in a multi-processor system, and improving the performance of the multi-processor system.

[0087] In some embodiments, if a target write request meets the data forwarding condition, the request data of the target write request is passed to one of the first sniff requests in the sniff request queue, including one of the following:

[0088] If the target write request is stored in the sniff buffer and the target write request meets the data forwarding condition, obtain the request data of the target write request from the sniff buffer and pass it to the first sniff request;

[0089] If the target write request is stored in the write request buffer and the target write request meets the data forwarding condition, obtain the request data of the target write request from the write request buffer and pass it to the first sniff request;

[0090] If the target write request is stored in the write request queue and the target write request meets the data forwarding condition, obtain the request data of the target write request from the write request queue and pass it to the first sniff request.

[0091] It should be noted that within the first processor, the target write request and the request data of the target write request can be temporarily stored in the sniff buffer, the write request buffer, or the write request queue.

[0092] The write request queue can be used to store write requests to be executed or being executed and the request data of the write request. In some embodiments, a write request to be executed can be understood as a write request to be sent through the interconnection bus. In some embodiments, a write request being executed can be understood as a write request that has been sent through the interconnection bus but has not received a response yet.

[0093] The write request buffer can be used to store write requests to be transmitted to the write request queue and the request data of the write request.

[0094] The sniff buffer can be used to store write requests to be transmitted to the write request buffer.

[0095] If it is determined that a target write request that has an address conflict with the first sniff request meets the data forwarding condition and the target write request is stored in the sniff buffer, the request data of the target write request can be obtained from the sniff buffer and passed to the first sniff request.

[0096] If it is determined that a target write request that has an address conflict with the first sniff request meets the data forwarding condition and the target write request is stored in the write request buffer, the request data of the target write request can be obtained from the write request buffer and passed to the first sniff request.

[0097] If it is determined that the target write request that has an address conflict with the first sniff request meets the data forwarding condition and the target write request is stored in the write request queue, the request data of the target write request can be obtained from the write request queue and passed to the first sniff request.

[0098] In the embodiments of the present disclosure, when it is determined that the target write request meets the data forwarding condition, according to the storage location of the target write request, the request data of the target write request is obtained from this storage location and the request data is passed to the first sniff request, so as to implement data forwarding of the request data of the target write request that meets the data forwarding condition inside the first processor, and further implement a fast response of the first processor to the first sniff request initiated by the second processor, effectively shortening the communication delay of cross-processor communication.

[0099] In some embodiments, the method further includes one of the following:

[0100] After the request data of the target write request in the write request queue is passed, if the target write request has not been issued, cancel sending the target write request to the interconnection bus;

[0101] After the request data of the target write request in the write request queue is passed, if the target write request has been issued, delete the target write request and the request data of the target write request after receiving the response of the target write request.

[0102] In the embodiments of the present disclosure, when the target write request is stored in the write request queue and the request data of the target write request in the write request queue has been passed to the first sniff request, it is necessary to delete the target write request and the request data of the target write request in the cache subsystem of the first processor. It should be noted that when the request data of the target write request in the write request queue has been passed to the first sniff request, the cache subsystem of the first processor will be considered to have no longer stored this request data. In this case, if the target write request in the write request queue is not processed, the target write request may be issued, resulting in a failure of the multi-processor system.

[0103] Based on this, after the request data of the target write request in the write request queue is passed, it can be first determined whether the target write request has been executed. If the target write request has not been executed, the target write request can be deleted from the write request queue to cancel sending the target write request to the interconnection bus. If the target write request has been issued, wait for the interconnection bus to return the response of the target write request, and after receiving the response of the target write request, continue to perform subsequent processing.

[0104] Thus, after the transfer of the request data of the target write request in the write request queue is completed, different processing is performed on the target write request according to whether the target write request in the write request queue is issued, so as to eliminate the adverse effects brought by the continued execution of the target write request.

[0105] In some embodiments, the method further includes:

[0106] In the case where the transfer of the request data of the target write request in the snooping buffer is completed, a cancellation flag is added to the target write request in the snooping buffer; the cancellation flag is used to indicate canceling the sending of the target write request to the interconnect bus;

[0107] The target write request with the cancellation flag added is continuously transmitted to the write request queue;

[0108] Cancel the sending of the target write request in the write request queue with the cancellation flag added.

[0109] In the embodiments of the present disclosure, when the target write request is stored in the snooping buffer and the request data of the target write request in the snooping buffer has been transferred to the first snooping request, it is necessary to delete the target write request and the request data of the target write request in the cache subsystem of the first processor.

[0110] In order to reduce the impact on the inside of the first processor, a cancellation flag can be added to the target write request in the snooping buffer after the transfer of the request data of the target write request in the snooping buffer is completed, and the target write request with the cancellation flag added is continuously transmitted.

[0111] Here, the cancellation flag can be used to indicate canceling the sending of the target write request to the interconnect bus. If the cancellation flag is added to the target write request, it means that the sending of the target write request to the interconnect bus is canceled.

[0112] When the target write request with the cancellation flag added is transmitted to the write request queue, the target write request with the cancellation flag added can be deleted from the write request queue, so as to cancel the sending of the target write request to the interconnect bus.

[0113] Thus, after the transfer of the request data of the target write request in the snooping buffer is completed, a cancellation flag can be added to the target write request in the snooping buffer, and the target write request with the cancellation flag added is continuously transmitted. After the target write request is transmitted to the write request queue, the target write request is deleted from the write request queue, so that the adverse effects brought by the sending of the target write request can be eliminated, and the target write request can be processed inside the first processor, reducing the impact on the inside of the first processor.

[0114] In some embodiments, the method further includes:

[0115] In the case where the request data of the target write request in the write request queue has been transferred, add a cancellation flag to the target write request in the target write request; the cancellation flag is used to indicate canceling the sending of the target write request to the interconnect bus.

[0116] Continue to transfer the target write request with the cancellation flag added to the write request queue.

[0117] Cancel the sending of the target write request with the cancellation flag added in the write request queue.

[0118] In the embodiment of the present disclosure, when the target write request is stored in the write request buffer and the request data of the target write request in the write request buffer has been transferred to the first snooping request, it is necessary to delete the target write request and the request data of the target write request in the cache subsystem of the first processor.

[0119] To reduce the impact on the inside of the first processor, after the transfer of the request data of the target write request in the write request buffer is completed, a cancellation flag can be added to the target write request in the write request buffer, and the target write request with the cancellation flag added is continued to be transferred.

[0120] Here, the cancellation flag can be used to indicate canceling the sending of the target write request to the interconnect bus. If the target write request is added with a cancellation flag, it means that the target write request is canceled from being sent to the interconnect bus.

[0121] When the target write request with the cancellation flag added is transferred to the write request queue, the target write request with the cancellation flag added can be deleted in the write request queue so as to cancel the sending of the target write request to the interconnect bus.

[0122] In this way, after the transfer of the request data of the target write request in the write request buffer is completed, a cancellation flag can be added to the target write request in the write request buffer, and the target write request with the cancellation flag added is continued to be transferred. After the target write request is transferred to the write request queue, the target write request is deleted from the write request queue, so that both the adverse effects caused by the sending of the target write request can be eliminated, and the target write request can be processed within the first processor, reducing the impact on the inside of the first processor.

[0123] In some embodiments, before performing an address conflict check on the first snooping request, the method further includes:

[0124] Obtain the request-related information of at least one write request and the request-related information of the first snooping request; the request-related information is at least used to indicate the request time, request access address, and / or request source of the write request.

[0125] Determine whether at least one write request and the first snooping request satisfy a conflict condition according to the request-related information of at least one write request and the request-related information of the first snooping request;

[0126] When the write request and the first snooping request satisfy the conflict condition, give priority to processing the first snooping request.

[0127] In the embodiments of the present disclosure, in order to realize the interconnection between multi-processor systems, when at least one write request from within the first processor and the first snooping request from the interconnection bus are received, obtain the request-related information of at least one write request and the request-related information of the first snooping request, and determine whether at least one write request and the first snooping request satisfy the conflict condition according to the request-related information of at least one write request and the request-related information of the first snooping request.

[0128] Here, the request-related information can at least be used to indicate the request time, request access address, and / or request source of the write request.

[0129] In some embodiments, it is possible to determine whether at least one write request and the first snooping request satisfy the conflict condition according to the request time and request access address of at least one write request, and the request time and request access address of the first snooping request.

[0130] That the first snooping request and the write request satisfy the conflict condition can be that there is an address access conflict between the first snooping request and the write request. For example, if the first snooping request and the write request are for the same access address at the same moment, there is an address access conflict between the first snooping request and the write request. To maintain cache consistency, the first snooping request and the write request cannot be responded to simultaneously.

[0131] When it is determined that the write request and the first snooping request satisfy the conflict condition, the first snooping request can be given priority for processing. After waiting for the first snooping request to be executed, then process the write request.

[0132] It should be noted that in the case where the write request and the first snooping request satisfy the conflict condition, the ACE protocol stipulates that the write request within the first processor should be processed first, and then the first snooping request from the interconnection bus should be processed. However, in order to support the CHI protocol to realize the interconnection of multi-processor systems based on the CHI protocol, the embodiments of the present disclosure can give priority to processing the first snooping request from the interconnection bus. In this way, the conversion from the ACE protocol to the CHI protocol can be realized in the multi-processor system in the above conflict situation.

[0133] Embodiments of the present disclosure can use the request-related information of at least one write request and the request-related information of the first snooping request to determine whether at least one write request and the first snooping request meet the conflict condition based on the request-related information of at least one write request and the request-related information of the first snooping request. When the write request and the first snooping request meet the conflict condition, the first snooping request is preferentially processed, so that cache consistency can be maintained when the write request and the first snooping request meet the conflict condition, and the conversion from the ACE protocol to the CHI protocol can be realized, thereby realizing the interconnection of a multi-processor system, which is beneficial to the first processor's quick response to the first snooping request from the interconnection bus and effectively shortens the communication delay of communication between different processors in a cross-processor system.

[0134] In some embodiments, if the write request and the first snooping request meet the conflict condition, the request-related information of the write request indicates one of the following:

[0135] The write request is a write request from the core of the first processor, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request;

[0136] The write request is a write request being processed within the first processor, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request;

[0137] The write request is a write request stored in the snooping buffer, and the request time of the write request is the same as the request time of the first snooping request.

[0138] In embodiments of the present disclosure, if the request-related information of the write request indicates that the write request is a write request from the core of the first processor, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request, it can be determined that the write request and the first snooping request meet the conflict condition. In this case, the first snooping request can be preferentially processed, and the write request can be processed after the first snooping request is processed.

[0139] It should be noted that for the address access conflict between the write request from the core of the first processor and the first snooping request from the interconnection bus at the same moment and the same address, according to the ACE protocol regulations, usually the write request from the core of the first processor is processed first, and then the first snooping request from the interconnection bus is processed. Embodiments of the present disclosure can process the first snooping request from the interconnection bus first to support the CHI protocol, and wait until the first snooping request is processed before processing the write request from the core of the first processor.

[0140] If the request-related information of the write request indicates that the write request is a write request being processed within the first processor, and the request time and request access address of the write request are the same as those of the first snooping request, it can be determined that the write request and the first snooping request meet the conflict condition.

[0141] It should be noted that for the address access conflict between the write request being processed within the first processor and the first snooping request from the interconnect bus at the same time and the same address, according to the ACE protocol, usually, it is necessary to wait for the write request being processed within the first processor to be completed before processing the first snooping request from the interconnect bus. In the embodiments of the present disclosure, as long as the write request being processed within the first processor has not been processed to obtain the response returned by the interconnect bus, the first snooping request from the interconnect bus can be preferentially processed. After the first snooping request is processed, the write request can be continued to be processed.

[0142] If the request-related information of the write request indicates that the write request is a write request stored in the snooping buffer, and the request time and request access address of the write request are the same as those of the first snooping request, it can be determined that the write request and the first snooping request meet the conflict condition.

[0143] It should be noted that for the address access conflict between the write request stored in the snooping buffer and the first snooping request from the interconnect bus at the same time and the same address, the first snooping request from the interconnect bus can be preferentially processed. After the first snooping request is processed, the write request stored in the snooping buffer can be processed.

[0144] In the embodiments of the present disclosure, when it is determined that the write request and the first snooping request belong to any of the above three situations according to the request-related information of the write request and the request-related information of the first snooping request, it can be determined that there is an address access conflict between the write request and the first snooping request, that is, the write request and the first snooping request meet the conflict condition. By preferentially processing the first snooping request, it is possible to maintain cache coherence and implement the conversion from the ACE protocol to the CHI protocol, and achieve two-way support for the ACE protocol and the CHI protocol within the first processor and between the first processor and the second processor.

[0145] In some embodiments, the method further includes: if the target write request does not meet the data forwarding condition, creating a buffer table entry corresponding to the first snooping request in the snooping buffer.

[0146] In an embodiment of the present disclosure, when it is determined that a target write request conflicting with the first sniff request address does not meet the data forwarding condition, the request data of the target write request may not be passed to the first sniff request. Instead, a buffer entry corresponding to the first sniff request is created in the sniff buffer, and the first sniff request is stored in the sniff buffer to wait for processing.

[0147] It should be noted that in the buffer of the processor, the buffer entry is the basic unit for storing specific data or instruction information. The design and storage method of the buffer entry directly affect the efficiency and performance of the cache. An efficient buffer entry design can reduce the cache miss rate and improve the data access speed.

[0148] It is worth noting that after creating a buffer entry corresponding to the first sniff request in the sniff buffer, the buffer entry can record the entire life cycle of the first sniff request within the buffer subsystem.

[0149] In an embodiment of the present disclosure, when it is determined that a target write request conflicting with the first sniff request address does not meet the data forwarding condition, that is, the request data of the target write request cannot be forwarded to the first sniff request, a buffer entry corresponding to the first sniff request is created in the sniff buffer, and the first sniff request is stored in the sniff buffer to wait for the target write request to be processed and then process the first sniff request.

[0150] An embodiment of the present disclosure further provides a multi-processor system, which may include:

[0151] Multiple processors, which are connected by an interconnection bus;

[0152] Each of the multiple processors includes a cache subsystem as shown in one or more of the above technical solutions.

[0153] In an embodiment of the present disclosure, the multi-processor system may include multiple processors, which are connected by an interconnection bus.

[0154] Each processor may include a cache subsystem, which includes a sniff request queue, a conflict check circuit, and a data forwarding circuit. The cache subsystem of each processor can be used to execute the data processing method shown in one or more of the above technical solutions. In this way, it can not only maintain data consistency between multiple processors, but also enable the first processor to quickly respond to the first sniff request, effectively shortening the communication delay of cross-processor communication, realizing efficient interconnection between multiple processors in the multi-processor system, and improving the performance of the multi-processor system.

[0155] In some embodiments, as Figure 3 shown, Figure 3It is a schematic diagram of the overall architecture of a cache subsystem shown according to an exemplary embodiment. The data forwarding circuit can be located between the snooping buffer and the external cluster snooping request queue. When a snooping request from an external cluster enters the snooping buffer, it will first check for address conflicts. If there are certain conflicts, the data forwarding circuit will be used to implement the data forwarding from the conflicting request to the external cluster snooping request, and this data will be sent by the conflicting request into the external cluster snooping request queue.

[0156] As Figure 4 shown, Figure 4 It is a schematic diagram of the architecture of a snooping buffer shown according to an exemplary embodiment. The address conflict check when a snooping request from an external cluster enters the snooping buffer can be performed by the snooping buffer circuit unit. This snooping buffer circuit unit can receive read / write requests from the core, snooping requests from other clusters, and snooping requests from the secondary cache to perform address conflict checks. If there are address conflicts but no data forwarding is required, it can create an entry in the snooping buffer for the snooping request from other clusters. If there are address conflicts and data forwarding is required, it does not create an entry in the snooping buffer for the snooping request from other clusters and directly waits for data forwarding in the external cluster snooping request queue.

[0157] It should be noted that each request will be maintained by an entry, and the entire life cycle of this request in the coherence maintenance unit after the entry is created is within the entry.

[0158] In some embodiments, to implement the conversion from the ACE protocol to the CHI protocol, there are the following types of address conflicts that need to be checked for address conflicts in the snooping buffer:

[0159] A. A write request B from the core and a snooping request from another cluster with the same address at the same time;

[0160] B. A snooping request from the secondary cache and a snooping request from another cluster with the same address at the same time;

[0161] C. A snooping request from another cluster and a write request being processed in the external interaction unit with the same address at the same time;

[0162] D. A snooping request from another cluster and a write request in the snooping buffer entry with the same address at the same time;

[0163] It should be noted that for the above two types of address conflicts between A and C, the ACE protocol stipulates that write requests should be processed first and then snooping requests from other clusters. However, to support the CHI protocol for multi-cluster interconnection based on the CHI protocol, in the embodiments of the present disclosure, for these two address conflict situations, it is possible to choose to process the snooping requests from other clusters first, and after waiting for them to be processed, perform certain processing on the two types of requests that conflict with them.

[0164] In some embodiments, to maintain cache coherence and support two protocol specifications, the specific solutions for these types of address conflicts are as follows:

[0165] (a) For a write request B from a core and a snooping request from another cluster with the same address at the same time, the snooping request from the other cluster is processed first.

[0166] (b) For a snooping request from a secondary cache and a snooping request from another cluster with the same address at the same time, the snooping request from the secondary cache is processed first, but the data write-back caused by this snooping request will not be processed and needs to wait for the snooping request from the other cluster to be processed before being processed.

[0167] (c) For a snooping request from another cluster and a write request being processed in the external interaction unit at the same time, as long as the write request has not been processed to obtain the request response returned by the interconnection bus, the snooping request from the other cluster is given priority, and subsequent processing will be performed on this write request.

[0168] (d) For a snooping request from an external cluster and a write request in the snooping buffer table entry with the same address at the same time, the snooping request from the external cluster needs to be processed first, and this write request waits for the snooping request to be processed before performing certain processing.

[0169] To ensure that the snooping request from another cluster can obtain the first data, it is necessary to add a data forwarding path within the cluster, that is, send the data required by the snooping request from the write request temporary storage to the snooping request, as Figure 5 shown, Figure 5 is a flowchart showing a data processing method according to an exemplary embodiment. Figure 2 This method includes:

[0170] Step S501, receiving a snooping request sent by the interconnection bus.

[0171] Step S502, the snooping buffer circuit unit checks for address conflict requests between the snooping request and the write request.

[0172] Step S503, the data forwarding circuit determines whether data needs to be forwarded according to the type of the write request.

[0173] Step S504: The data forwarding circuit forwards the first data to the snooping requests initiated by other clusters and updates the cache status.

[0174] As Figure 6 shown, Figure 6 FIG. is a schematic flowchart of a data forwarding process according to an exemplary embodiment. Among them, the write buffer stores write requests and write data to be sent to the write request queue and initiated to the external cluster's interconnect network. The write request queue stores write requests and write data that are about to be initiated to the external cluster's interconnect network, as well as write requests and write data being processed and those that have started being processed but not yet completed.

[0175] There are three sources of the data to be forwarded: the write data in the write request buffer, the write data in the write request queue, and the write data in the snooping buffer entry. Before creating an entry in the snooping buffer for a snooping request from an external cluster, an address conflict check will be performed. If it is found that there is an address conflict with the write request entry in the write request buffer, the write request queue, or the snooping buffer, then the conflicting write requests, under the condition of meeting the data forwarding conditions, will forward the data to the snooping request entry of the external cluster. At this time, the external cluster snooping request that has obtained the forwarded data will not create an entry in the snooping buffer anymore.

[0176] After forwarding the data, the request for forwarding the data needs to be processed in a certain way. If the data is forwarded from the entry in the snooping buffer, then after the snooping request of the external cluster is completed, the request in the entry will be marked with a cancellation mark and continue to be sent to the write request buffer and the write request queue, and will be cancelled in the write request queue, and the request ends. If the data is forwarded from the write request buffer, then after the snooping request of the external cluster is completed, the request in the write request buffer will be marked with a cancellation mark and continue to be sent to the write request queue, and will be cancelled in the write request queue, and the request ends. If the data is forwarded from the write request queue, it is necessary to wait until the snooping request of the external cluster is completed, and then the request in the write request queue is processed. If the request has not been sent to the external cluster interconnect bus, it is cancelled. If it has been sent, it waits for the response of the request from the external cluster interconnect bus.

[0177] In this solution, within the cluster, through the handling of address conflicts in specific scenarios and data forwarding, two-way support for the ACE protocol and the CHI protocol inside and outside the cluster is achieved, providing a certain degree of help for realizing multi-cluster interconnect based on the CHI protocol.

[0178] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here in detail.

[0179] Embodiments of the present disclosure also provide a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor of a multi-processor system, the processor is enabled to execute any one of the above-described data processing methods according to embodiments of the present disclosure.

[0180] Embodiments of the present disclosure provide a computer program product, which includes: a computer program or executable instructions, and the computer program or executable instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or executable instructions from the computer-readable storage medium, and the processor executes the computer program or executable instructions, so that the computer device executes any one of the above-described data processing methods according to embodiments of the present disclosure.

[0181] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0182] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A data processing method, characterized in that, The method includes: In response to a first snooping request in a snooping request queue, perform an address conflict check on the first snooping request according to at least one write request within a first processor; wherein, the first snooping request is a snooping request from an interconnect bus, a second processor is connected to the first processor through the interconnect bus; the first processor is any processor of a multiprocessor system, and the second processor is any processor in the multiprocessor system other than the first processor; If there is a target write request among the at least one write request that has an address conflict with the first snooping request, determine whether the target write request meets the data forwarding condition; If the target write request meets the data forwarding condition, transfer the request data of the target write request to the first snooping request in the snooping request queue.

2. The method according to claim 1, wherein The step of if the target write request meets the data forwarding condition, transfer the request data of the target write request to the first snooping request in the snooping request queue includes one of the following: If the target write request is stored in a snooping buffer and the target write request meets the data forwarding condition, obtain the request data of the target write request from the snooping buffer and transfer it to the first snooping request; If the target write request is stored in a write request buffer and the target write request meets the data forwarding condition, obtain the request data of the target write request from the write request buffer and transfer it to the first snooping request; If the target write request is stored in a write request queue and the target write request meets the data forwarding condition, obtain the request data of the target write request from the write request queue and transfer it to the first snooping request.

3. The method according to claim 2, wherein The method further includes one of the following: After completing the transfer of the request data of the target write request in the write request queue, if the target write request has not been issued, cancel sending the target write request to the interconnect bus; After completing the transfer of the request data of the target write request in the write request buffer, if the target write request has been issued, delete the target write request and the request data of the target write request after receiving the response to the target write request.

4. The method according to claim 2, wherein, The method further includes: In the case of completing the transfer of the request data of the target write request in the snooping buffer, add a cancellation flag to the target write request in the snooping buffer; the cancellation flag is used to indicate canceling sending the target write request to the interconnect bus; Continue to transfer the target write request with the cancellation flag added to the write request queue; Cancel sending the target write request with the cancellation flag added in the write request queue.

5. The method according to claim 2, wherein, The method further includes: In the case of completing the transfer of the request data of the target write request in the write request queue, add a cancellation flag to the target write request in the target write request; the cancellation flag is used to indicate canceling sending the target write request to the interconnect bus; Continue to transfer the target write request with the cancellation flag added to the write request queue; Cancel sending the target write request with the cancellation flag added in the write request queue.

6. The method according to claim 1, wherein Before performing an address conflict check on the first snooping request, the method further includes: Obtaining request-related information of the at least one write request and request-related information of the first snooping request; the request-related information is at least used to indicate the request time, request access address, and / or request source of the write request. Determining whether the at least one write request and the first snooping request satisfy a conflict condition according to the request-related information of the at least one write request and the request-related information of the first snooping request. When the write request and the first snooping request satisfy the conflict condition, give priority to processing the first snooping request.

7. The method according to claim 6, wherein, If the write request and the first snooping request satisfy the conflict condition, the request-related information of the write request indicates one of the following: The write request is a write request from the core of the first processor, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request. The write request is a write request being processed within the first processor, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request. The write request is a write request stored in the snooping buffer, and the request time and request access address of the write request are the same as the request time and request access address of the first snooping request.

8. The method according to claim 1, characterized in that, The method further includes: If the target write request does not satisfy the data forwarding condition, creating a buffer entry corresponding to the first snooping request in the snooping buffer.

9. A cache subsystem, characterized in that, Applied to a first processor, the cache subsystem includes: A snooping request queue for storing a first snooping request from an interconnect bus; the first processor is any processor of a multi-processor system, and the second processor is any processor in the multi-processor system other than the first processor; the second processor is connected to the first processor through an interconnect bus. A conflict check circuit connected to the snooping request queue for performing an address conflict check on the first snooping request according to at least one write request from the first processor. A data forwarding circuit connected to the conflict check circuit and the snooping request queue for determining whether a target write request satisfies a data forwarding condition if there is an address conflict between the target write request and the first snooping request in at least one write request; if the target write request satisfies the data forwarding condition, transferring the request data of the target write request to the first snooping request.

10. The cache subsystem according to claim 9, wherein The cache subsystem includes: A write request queue for storing at least one write request and the request data of the write request; the write requests stored in the write request queue are write requests to be executed or being executed. A write request buffer for storing at least one write request and the request data of the write request; the write requests stored in the write request buffer are write requests to be transmitted to the write request queue. A sniffing buffer, which is further configured to store at least one write request and request data of the write request; the write request stored in the sniffing buffer is a write request to be transmitted to the write request buffer. The data forwarding circuit is connected to the write request queue, the write request buffer, and the sniffing buffer, and is configured to transfer the request data of a target write request that meets the data forwarding condition in the write request queue, the write request buffer, or the sniffing buffer to the first sniffing request.

11. A multi-processor system, characterized in that, Comprising: A plurality of processors, which are connected by an interconnection bus, and each processor includes a cache subsystem as described in claim 9 or 10.

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