Data scheduling method, device and equipment of domain control computing power model and storage medium

Abstract

The invention provides a data scheduling method and device for a domain control computing power model, equipment and a storage medium. The data scheduling method comprises the following steps: operating an upper unit according to an upper time sequence; wherein the upper unit is an operation unit used for processing through upper business and generating business data, and the business data generated by the upper unit is output data; the output data is input data required by the lower unit for performing lower business processing; the lower unit is an operation unit used for generating service data through lower service processing; if it is monitored that the upper unit reaches the Nth trigger point of the upper time sequence, transmitting the Nth stage data in the upper unit to the lower unit; wherein the Nth trigger point is the Nth time node on the pulse signal; and according to the lower time sequence, controlling the lower unit to carry out lower business processing according to the Nth-stage data to obtain the business data of the Nth stage. According to the invention, the overall delay of the domain control computing power model is greatly reduced, and the computing speed of the domain control computing power model is improved.

Description

Technical Field

[0001] This application relates to the field of intelligent driving technology, and particularly to a data scheduling method, device, equipment, and storage medium for a domain control computing power model. Background Art

[0002] Intelligent driving is usually achieved by using a domain control computing power model with high computing power. The domain control computing power model consists of multiple independent computing units, each computing unit runs an independent operating system, and the computing units are communicatively connected to each other; compared with a single computing unit, the communication overhead between the computing units in the domain control computing power model is often much larger. Especially when deploying a large model, due to the computing power and memory limitations of a single computing unit, it is necessary to split and deploy the large model onto multiple computing units.

[0003] Currently, for the data scheduling method of a domain control computing power model with high computing power, usually after the previous computing unit completes its service processing and generates service data, the service data is sent to the next computing unit for service processing.

[0004] However, the inventor found that since it takes a long time for the previous computing unit to send the service data to the next computing unit, a large delay is generated in the overall domain control computing power model. Summary of the Invention

[0005] This application provides a data scheduling method, device, equipment, and storage medium for a domain control computing power model to solve the problem that it takes a long time for the previous computing unit to send service data to the next computing unit currently, resulting in a large delay in the overall domain control computing power model.

[0006] In a first aspect, this application provides a data scheduling method for a domain control computing power model, where there is at least one computing unit in the domain control computing power model;

[0007] The method includes:

[0008] Running a superior unit according to a superior timing; where the superior timing is a pulse signal for controlling the timing of the superior unit; the superior unit is a computing unit for generating service data through superior service processing, and the service data generated by the superior unit is output data; the output data is the input data required for the inferior unit to perform inferior service processing; the inferior unit is a computing unit for generating service data through inferior service processing;

[0009] If it is monitored that the upper unit reaches the Nth trigger point of the upper timing sequence, the Nth stage data in the upper unit is transmitted to the lower unit; where the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated when the upper service processing of the upper unit runs to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is a natural number greater than or equal to 1 and less than or equal to M;

[0010] Control the lower unit to perform lower service processing according to the Nth stage data according to the lower timing sequence, and obtain the service data of the Nth stage; where the lower timing sequence is a pulse signal used to control the timing of the lower unit.

[0011] In the above solution, running the upper unit according to the upper timing sequence includes:

[0012] Obtain two computing units belonging to the upper and lower relationship in the domain control computing power model through a preset index tree, and determine the upper unit and the lower unit in the two computing units according to the upper and lower relationship; where the index tree represents the association relationship between each computing unit in the domain control computing power model; the upper and lower relationship represents the dependency relationship between two computing units;

[0013] If it is monitored that the upper unit receives service data, send the upper timing sequence to the upper unit; where the service data received by the upper unit is the input data used by the upper unit to implement the upper service processing;

[0014] Control the upper unit to perform upper service processing according to the service data received by the upper unit through the upper timing sequence, so that the upper unit generates service data.

[0015] In the above solution, if it is monitored that the upper unit reaches the Nth trigger point of the upper timing sequence, and the Nth stage data in the upper unit is transmitted to the lower unit, it includes:

[0016] Monitor the running time of the upper node. If it is determined that the running time reaches the Nth trigger point of the upper timing sequence, obtain the Nth stage data generated by the upper node;

[0017] Transmit the Nth stage data to the lower unit through a preset network communication bus.

[0018] In the above solution, controlling the lower unit to perform lower service processing according to the Nth stage data according to the lower timing sequence includes:

[0019] Obtain the lower-level units in the domain control computing power model that have a hierarchical relationship with the upper-level unit through a pre-set index tree; wherein, the index tree represents the association relationship between each computing unit in the domain control computing power model; the hierarchical relationship represents the dependency relationship between two computing units;

[0020] Output a lower-level timing to the lower-level unit, and control the lower-level unit to perform lower-level service processing according to the data in the Nth stage through the lower-level timing, so that the lower-level unit generates service data in the Nth stage.

[0021] In the above solution, before running the upper-level unit according to the upper-level timing, it further includes:

[0022] Obtain the service processing information of each computing unit; wherein, the service processing information records the unit input data and unit output data of the computing unit; the unit input data is the service data required by the computing unit during service processing; the unit output data is the service data generated by the computing unit after completing service processing;

[0023] Determine the hierarchical relationship between each computing unit in the domain control computing power model according to the service processing information of each computing unit; wherein, the hierarchical relationship is used to determine the upper-level unit and the lower-level unit in two computing units.

[0024] In the above solution, determining the hierarchical relationship between each computing unit in the domain control computing power model according to the service processing information of each computing unit includes:

[0025] If it is determined that the target unit output data matches the target unit input data, set the computing unit corresponding to the target unit output data as the upper-level unit, and set the computing unit corresponding to the target unit input data as the lower-level unit; wherein, the target unit output data is one of the unit output data of at least one computing unit; the target unit input data is one of the unit input data of at least one computing unit.

[0026] In the above solution, before running the upper-level unit according to the upper-level timing, it further includes:

[0027] Obtain the service process information of each computing unit; wherein, the service process information records the service processing process of the computing unit, as well as the stage input data and stage output data generated during the service processing process; the service processing process includes at least one service stage; the stage input data is the service data required by the computing unit when running a service stage; the stage output data is the service data generated by the computing unit when running a service stage.

[0028] Determine the time nodes of the upper timing according to the service process information of each of the operation units; wherein, the time nodes represent the nodes when the upper nodes complete the service phases in the upper timing.

[0029] In the above solution, determining the time nodes of the upper timing according to the service process information of each of the operation units includes:

[0030] Obtain two operation units with an upper-lower relationship in the domain control computing power model, and identify the upper unit and the lower unit in the two operation units;

[0031] Identify the stage output data in the upper unit that matches the stage input data of the lower unit, and determine the service phase corresponding to the identified stage output data;

[0032] Set the position corresponding to the determined service phase in the upper timing corresponding to the upper unit as the time node.

[0033] In a second aspect, the present application provides a data scheduling device for a domain control computing power model, where there is at least one operation unit in the domain control computing power model;

[0034] The device includes:

[0035] An upper control module, configured to operate the upper unit according to the upper timing; wherein, the upper timing is a pulse signal for timing control of the upper unit; the upper unit is an operation unit for generating service data through upper service processing, and the service data generated by the upper unit is output data; the output data is the input data required for the lower unit to perform lower service processing; the lower unit is an operation unit for generating service data through lower service processing;

[0036] A data transmission module, configured to, if it is monitored that the upper unit reaches the Nth trigger point of the upper timing, transmit the Nth stage data in the upper unit to the lower unit; wherein, the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated when the upper service processing of the upper unit runs to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is any natural number in the interval [1, M];

[0037] A lower control module, configured to control the lower unit to perform lower service processing according to the Nth stage data according to the lower timing to obtain the service data of the Nth stage; wherein, the lower timing is a pulse signal for timing control of the lower unit.

[0038] In a third aspect, the present application provides a computer device, including: a processor and a memory communicatively connected to the processor;

[0039] The memory stores computer-executable instructions;

[0040] The processor executes the computer-executable instructions stored in the memory to implement the data scheduling method of the domain control computing power model as described in the above claims.

[0041] In a fourth aspect, the present application provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the data scheduling method of the above domain control computing power model when executed by a processor.

[0042] In a fifth aspect, the present application provides a computer program product including a computer program, which implements the data scheduling method of the above domain control computing power model when executed by a processor.

[0043] A data scheduling method, device, equipment and storage medium for a domain control computing power model provided by the present application, if it is monitored that the upper unit reaches the Nth trigger point of the upper timing, then transmits the Nth stage data in the upper unit to the lower unit; realizes the technical effect of transmitting the service output generated in a certain stage to the lower unit.

[0044] By controlling the lower unit through the lower timing to perform lower-level service processing according to the Nth stage data to obtain the service data of the Nth stage; enabling the upper unit to transmit service data to the lower unit, and during the process of the lower unit performing the lower-level service processing corresponding to the Nth stage data, the upper unit will continue to run to the (N + 1)th trigger point, and at the same time, the upper unit transmits the Nth stage data during the process of running to the (N + 1)th trigger point for the lower-level service processing of the lower unit. Therefore, the transmission time of the Nth stage data coincides with the running process of the upper unit from the Nth trigger point to the (N + 1)th trigger point, and the transmission time of the Nth stage data coincides with the running process of the lower unit to the Nth trigger point, thereby greatly reducing the overall delay to achieve the transmission of service data and the parallel operation of the upper unit and the lower unit, greatly reducing the overall delay of communication between multiple computing units in the domain control computing power model, and because all computing units in the domain control computing power model are called, the overall computing speed of the domain control computing power model and the utilization rate of the computing units are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0046] Figure 1 It is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0047] Figure 2 Flowchart of Embodiment 1 of a data scheduling method for a domain control computing power model provided by an embodiment of the present application;

[0048] Figure 3 Flowchart of Embodiment 2 of a data scheduling method for a domain control computing power model provided by an embodiment of the present application;

[0049] Figure 4 Schematic diagram of program modules of a data scheduling device for a domain control computing power model provided by the present invention;

[0050] Figure 5 Schematic diagram of the hardware structure of a computer device in a computer device of the present invention.

[0051] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Specific Embodiments

[0052] Here, exemplary embodiments will be described in detail, and their examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0053] Please refer to Figure 1 , the specific application scenario of the present application is:

[0054] The domain control computing power model 11 has at least one operation unit 12, and a control module 13 of the data scheduling method of the domain control computing power model is connected to each operation unit 12; the operation unit is a computer module or computer control module that realizes a specified function by performing business processing.

[0055] The control module 13 operates the upper unit according to the upper timing; wherein, the upper timing is a pulse signal for timing control of the upper unit; the upper unit is an operation unit for performing upper business processing and generating service data, and the service data generated by the upper unit is output data; the output data is the input data required by the lower unit for performing lower business processing; the lower unit is an operation unit for generating service data by performing lower business processing;

[0056] If the control module 13 monitors that the upper unit reaches the Nth trigger point of the upper timing, the Nth stage data in the upper unit is transmitted to the lower unit; wherein the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the business data generated by the upper business processing of the upper unit when it runs to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is a natural number greater than or equal to 1 and less than or equal to M;

[0057] The control module 13 controls the lower unit to perform lower service processing according to the Nth stage data according to the lower timing, and obtains the service data of the Nth stage; wherein the lower timing is a pulse signal for timing control of the lower unit.

[0058] The technical solution of the present application and how the technical solution of the present application solves the problems of the prior art are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0059] Embodiment 1:

[0060] See also Figure 2 , the present application provides a data scheduling method for a domain control computing power model, wherein the domain control computing power model has at least one computing unit;

[0061] Methods include:

[0062] S201: Run the upper unit according to the upper timing; wherein the upper timing is a pulse signal for performing timing control on the upper unit; the upper unit is an operation unit for generating business data through upper business processing, and the business data generated by the upper unit is output data; the output data is the input data required for the lower unit to perform lower business processing; the lower unit is an operation unit for generating business data through lower business processing.

[0063] In this step, the upper unit is controlled to process the upper business by running the upper unit according to the upper timing, and the output data is obtained, and the output data is used as the input data of the lower unit, so as to achieve the technical effect of controlling the operation of the upper unit based on the timing control.

[0064] It should be noted that in order for the computer to work in an orderly manner, there are strict requirements for the generation time, stabilization time, cancellation time and the relationship between various operation signals. The time control of the operation signal is called timing control. Only strict timing control can ensure the organic combination of various functional components of the computer system.

[0065] In a preferred embodiment, operating the upper unit according to the upper timing sequence includes:

[0066] Obtain two operation units in the domain control computing power model that belong to the upper-lower relationship through a pre-set index tree, and determine the upper unit and the lower unit in the two operation units according to the upper-lower relationship; wherein, the index tree represents the association relationship between the operation units in the domain control computing power model; the upper-lower relationship represents the dependency relationship between the two operation units.

[0067] If it is monitored that the upper unit receives service data, send an upper timing to the upper unit; wherein, the service data received by the upper unit is the input data used by the upper unit to implement upper service processing.

[0068] Control the upper unit to perform upper service processing according to the service data received by the upper unit through the upper timing, so that the upper unit generates service data.

[0069] Exemplarily, obtain two operation units with an upper-lower relationship from the index tree through data indexing and querying.

[0070] Among them, data indexing and querying: The data indexing technology used for tasks that require efficient querying and retrieving of data to accelerate the data access and retrieval process. The index tree can be any one of the following data structures: hash table, B-tree, inverted index.

[0071] A hash table is also called a hash table (Hash table), which is a data structure that directly accesses the data storage location in memory according to the key (Key).

[0072] A B-tree, generally speaking, is a generalized binary search tree (binary search tree) that can have more than 2 child nodes.

[0073] An inverted index (Inverted index), an inverted index first knows which documents each keyword appears in, and searches for documents from keywords (keyword → document). Exactly the purpose is reversed, and it has nothing to do with "reverse search".

[0074] Use the watch function or the listen function to monitor whether the upper unit receives service data, and control the upper unit to perform upper service processing according to the service data received by the upper unit through the upper timing, so that the upper unit generates service data.

[0075] When the upper unit performs upper-level service processing, one or several of the parallel computing algorithm, data partitioning and distributed computing algorithm, data stream processing algorithm, and GPU acceleration algorithm can be used to implement the upper-level service processing. This is to select suitable data access and computing methods according to specific application scenarios and requirements. At the same time, considering the data size, computing complexity, and performance requirements, reasonable algorithm design and optimization are carried out to improve the efficiency and performance of data access and computing.

[0076] The parallel computing algorithm is: by using parallel computing technologies such as multi-threading, vectorized instructions, or parallel processors, multiple data elements are processed simultaneously. This can improve computing performance and efficiency, especially for large-scale data sets or tasks that require complex calculations.

[0077] The data partitioning and distributed computing algorithm is: for large-scale data sets or distributed systems, the data can be partitioned and stored on different nodes, and distributed computing is performed. This can be achieved using technologies such as distributed file systems, MapReduce models, and Spark.

[0078] The data stream processing algorithm is: real-time processing of continuous data streams to meet the requirements of low latency and high throughput. This can be achieved using technologies such as stream processing platforms, complex event processing, or pipeline architectures.

[0079] The GPU acceleration algorithm is: for tasks that require high-performance computing, the graphics processing unit (GPU) can be utilized for acceleration. By using GPU programming models such as CUDA or OpenCL, the computing tasks are assigned to the GPU for parallel computing.

[0080] Optionally, a dynamic adjustment and optimization algorithm can be used to adjust the upper-level timing. The dynamic adjustment and optimization is to dynamically adjust the running timing according to the status of real-time data transmission and computing tasks to adapt to different workloads and environmental changes. This can be achieved using feedback control, adaptive algorithms, or machine learning methods.

[0081] S202: If it is monitored that the upper unit reaches the Nth trigger point of the upper-level timing, the Nth-stage data in the upper unit is transmitted to the lower unit; where the Nth trigger point is the Nth time node on the pulse signal; the Nth-stage data is the service data generated when the upper-level service processing of the upper unit runs to the Nth trigger point; there are M time nodes in the pulse signal;; M is a natural number, and N is a natural number greater than or equal to 1 and less than or equal to M;..

[0082] In this step, by monitoring that the upper unit reaches the Nth trigger point of the upper-level timing and transmitting the Nth-stage data in the upper unit to the lower unit; the technical effect of transmitting the service output generated at a certain stage to the lower unit is achieved.

[0083] In a preferred embodiment, if it is monitored that the upper unit reaches the Nth trigger point of the upper timing sequence, the Nth stage data in the upper unit is transmitted to the lower unit, including:

[0084] Monitor the running time of the upper node. If it is determined that the running time reaches the Nth trigger point of the upper timing sequence, obtain the Nth stage data generated by the upper node;

[0085] Transmit the Nth stage data to the lower unit through a pre-set network communication bus.

[0086] Exemplarily, monitor the running time of the upper node through the watch function or the listen function. If it is determined that the running time reaches the Nth trigger point, perform a memory access to the upper node to obtain the Nth stage data from the memory of the upper node, and perform data compression and encoding processing on the Nth stage data for the sake of pure transmission.

[0087] Memory access is: by using appropriate memory access modes, such as direct memory access (DMA), cache mechanisms, etc., to read data from memory or external storage devices. This can be achieved by using pointers, array indices, or file system interfaces.

[0088] Data compression and encoding processing is: for large-scale data sets, data compression and encoding techniques can be used to reduce the storage and transmission overhead of data. This can include methods such as using compression algorithms, dictionary encoding, bit-level encoding, etc.

[0089] Transmit the Nth stage data to the lower unit through the network communication bus.

[0090] The network communication bus is: used to implement high-speed network connections between computing units, such as Ethernet, InfiniBand, etc., for data transmission between computing units. Data flow scheduling and priority scheduling algorithms can be used to optimize the bandwidth utilization and latency of data transmission.

[0091] Therefore, this example realizes prefetching the Nth stage data from the upper unit in advance and transmitting it to the lower unit for caching to reduce data transmission latency. Cache algorithms and prefetching strategies can be used to determine which data should be transmitted and when to transmit.

[0092] Optionally, according to one or more of the priority scheduling rules, error recovery and retransmission rules, and bandwidth management rules, transmit the Nth stage data to the lower unit through the network communication bus.

[0093] The priority scheduling rule is: according to the importance and urgency of the data, use a priority scheduling algorithm to determine the priority of data transmission. This can ensure that important data is transmitted first to meet the requirements of the computing unit.

[0094] The error recovery and retransmission rules are as follows: During data transmission, errors or packet losses may occur. To ensure data integrity and reliability, an error recovery and retransmission mechanism can be implemented to retransmit lost data when transmission errors occur.

[0095] The bandwidth management rules are as follows: Considering the limitations of network bandwidth, use bandwidth management algorithms to optimize the bandwidth utilization of data transmission. This can include techniques such as dynamically adjusting the transmission rate, data compression, and flow control.

[0096] S203: According to the lower-level timing, control the lower-level unit to perform lower-level service processing based on the data in the Nth stage, and obtain the service data in the Nth stage; where the lower-level timing is a pulse signal used to control the timing of the lower-level unit.

[0097] In this step,

[0098] By controlling the lower-level unit to perform lower-level service processing based on the data in the Nth stage according to the lower-level timing, the service data in the Nth stage is obtained; enabling the upper-level unit to transmit service data to the lower-level unit, and during the process of the lower-level unit performing the lower-level service processing corresponding to the data in the Nth stage, the upper-level unit will continue to run towards the (N + 1)th trigger point. At the same time, during the process of the upper-level unit running towards the (N + 1)th trigger point, it transmits the data in the Nth stage for the lower-level service processing of the lower-level unit. Therefore, the transmission time of the data in the Nth stage coincides with the running process of the upper-level unit from the Nth trigger point to the (N + 1)th trigger point, and the transmission time of the data in the Nth stage also coincides with the running process of the lower-level unit towards the Nth trigger point. Furthermore, the overall delay is greatly reduced to achieve the transmission of service data, as well as the parallel operation of the upper-level unit and the lower-level unit, greatly reducing the overall delay in communication between multiple arithmetic units in the domain control computing power model. And because all arithmetic units in the domain control computing power model are called, the overall computing speed of the domain control computing power model and the utilization rate of the arithmetic units are improved.

[0099] Therefore, the technical solution disclosed in this application enables the lower-level unit to obtain in advance the service data used for lower-level service processing before performing lower-level service processing, thereby realizing the data transmission or data prefetch process (this process is called JIT (Just-in-Time)), thereby overall reducing the delay of the domain control computing power model, improving the computing speed, and realizing the transmission of these data to the corresponding arithmetic units in advance, so that the data is exactly transmitted when the arithmetic unit needs to access it.

[0100] In a preferred embodiment, controlling the lower-level unit to perform lower-level service processing based on the data in the Nth stage according to the lower-level timing includes:

[0101] Obtain the lower-level unit corresponding to the upper-level unit in the domain control computing power model through the pre-set index tree;

[0102] Output the lower-level timing to the lower-level unit, and control the lower-level unit to perform lower-level service processing according to the data in the Nth stage through the lower-level timing, so that the lower-level unit generates the service data in the Nth stage.

[0103] Exemplarily, by outputting the lower-level timing to the lower-level unit, the lower-level timing controls, in a task scheduling or instruction scheduling manner, to implement controlling the lower-level unit to perform lower-level service processing.

[0104] When the lower-level unit performs lower-level service processing, it can adopt one or several algorithms among parallel computing algorithms, data partitioning and distributed computing algorithms, data stream processing algorithms, and GPU acceleration algorithms to implement lower-level service processing. This is to achieve selecting suitable data access and computing methods according to specific application scenarios and requirements. At the same time, considering data size, computing complexity, and performance requirements, reasonable algorithm design and optimization are carried out to improve the efficiency and performance of data access and computing.

[0105] Task scheduling is: through a reasonable task scheduling algorithm, adjust the execution order of computing units so that the corresponding computing tasks are executed after the data transmission is completed. This can be achieved through algorithms such as priority scheduling and load balancing.

[0106] Instruction scheduling is: schedule the instructions in the computing task so that the instructions that need to access and transmit data are executed after the data transmission is completed. This can be achieved through techniques such as instruction-level parallelism and out-of-order execution.

[0107] It should be noted that the specific implementation method will depend on factors such as system architecture, hardware devices, and software environment. In actual applications, it may be necessary to perform debugging, optimization, and customization according to specific situations. At the same time, comprehensively considering factors such as performance, latency, and resource consumption, making appropriate trade-offs is the key to realizing JIT data transmission and running timing adjustment.

[0108] The parallel computing algorithm is: by using parallel computing technologies such as multi-threading, vectorized instructions, or parallel processors, process multiple data elements simultaneously. This can improve computing performance and efficiency, especially for large-scale data sets or tasks that require complex calculations.

[0109] Data partitioning and distributed computing algorithms are: for large-scale data sets or distributed systems, the data can be partitioned and stored on different nodes, and distributed computing can be performed. This can be achieved using technologies such as distributed file systems, MapReduce models, and Spark.

[0110] The data stream processing algorithm is: real-time processing of continuous data streams to meet the requirements of low latency and high throughput. This can be achieved using technologies such as stream processing platforms, complex event processing, or pipeline architectures.

[0111] The GPU acceleration algorithm is: for tasks that require high-performance computing, the graphics processing unit (GPU) can be utilized for acceleration. By using GPU programming models such as CUDA or OpenCL, the computing tasks are assigned to the GPU for parallel computing.

[0112] Optionally, a dynamic adjustment and optimization algorithm can be adopted to adjust the lower-level timing. The dynamic adjustment and optimization is to dynamically adjust the running timing according to the real-time data transmission and the status of computing tasks, so as to adapt to different workloads and environmental changes. This can be achieved using feedback control, adaptive algorithms, or machine learning methods.

[0113] Embodiment 2:

[0114] Please refer to Figure 3 , this application provides a data scheduling method for a domain control computing power model, and there is at least one operation unit in the domain control computing power model;

[0115] The method includes:

[0116] S301: Obtain the service processing information of each operation unit; wherein, the service processing information records the unit input data and unit output data of the operation unit; the unit input data is the service data required by the operation unit when performing service processing; the unit output data is the service data generated by the operation unit when completing service processing;

[0117] According to the service processing information of each operation unit, determine the upper and lower level relationships between the operation units in the domain control computing power model; wherein, the upper and lower level relationships are used to determine the upper unit and the lower unit among two operation units.

[0118] In a preferred embodiment, determining the upper and lower level relationships between the operation units in the domain control computing power model according to the service processing information of each operation unit includes:

[0119] If it is determined that the target unit output data matches the target unit input data, then set the operation unit corresponding to the target unit output data as the upper unit, and set the operation unit corresponding to the target unit input data as the lower unit; wherein, the target unit output data is one of the unit output data of at least one operation unit; the target unit input data is one of the unit input data of at least one operation unit.

[0120] Exemplarily, the execution order of the operation units in the domain control computing power model is adjusted through a static scheduling algorithm or a dynamic scheduling algorithm, and the service processing information of the adjusted operation units is determined through a data dependency analysis algorithm, and the upper and lower relationships between the operation units are determined according to the service processing information.

[0121] Static scheduling algorithm: At the compilation or startup stage, according to the dependency relationship and performance requirements of the tasks, the execution order of the operation units is statically determined. This can be achieved using a static compiler, scheduler, or compilation optimization techniques.

[0122] Dynamic scheduling algorithm: At runtime, according to the real-time data requirements and the status of the computing tasks, the execution order of the operation units is dynamically adjusted. This can be achieved using a dynamic scheduler, load balancing algorithm, or feedback control mechanism.

[0123] Data dependency analysis algorithm: Analyze the data dependency relationships in the computing tasks to determine which instructions or operations must be executed after the data transfer is completed. According to the data dependency relationships, adjust the execution order of the instructions to ensure that the correct data is used.

[0124] S302: Obtain the service process information of each operation unit; wherein, the service process information records the service processing process of the operation unit, as well as the stage input data and stage output data generated during the service processing process; the service processing process includes at least one service stage; the stage input data is the service data required by the operation unit when running a service stage; the stage output data is the service data generated by the operation unit when running a service stage;

[0125] According to the service process information of each operation unit, determine the time node of the upper timing; wherein, the time node represents the node when the upper node completes the service stage in the upper timing.

[0126] In a preferred embodiment, determining the time node of the upper timing according to the service process information of each operation unit includes:

[0127] Obtain two operation units with an upper and lower relationship in the domain control computing power model, and identify the upper unit and the lower unit in the two operation units;

[0128] Identify the stage output data in the upper unit that matches the stage input data of the lower unit, and determine the service stage corresponding to the identified stage output data;

[0129] Set the position corresponding to the determined service stage in the upper timing corresponding to the upper unit as the time node.

[0130] Exemplarily, through one or several of the historical data analysis algorithm, real-time monitoring and analysis algorithm, and machine learning algorithm, based on the service data received by the operation unit in the domain control computing power model historically and the service processing process of the service data, service process information is obtained.

[0131] Historical data analysis algorithm: Infer future data requirements by analyzing historical data. This can be analyzed based on past data access patterns, computing tasks, and operating states. Statistical methods, time series analysis, or data mining techniques can be used to identify patterns and trends, so as to predict future data requirements.

[0132] Real-time monitoring and analysis algorithm: Real-time monitor the operation unit during operation, and collect real-time data on data access, computing tasks, and operating states. Based on these real-time data, real-time data analysis techniques, such as real-time statistics, machine learning models, etc., can be used to predict the data requirements at the next moment.

[0133] Machine learning algorithm: Use machine learning algorithms to learn the data access patterns and behavior rules of the operation unit, so as to predict data requirements. Methods such as supervised learning, unsupervised learning, or reinforcement learning can be used to predict data requirements according to the input features (such as historical data, real-time data, task information, etc.).

[0134] Data flow analysis algorithm: Perform real-time analysis on the data flow to understand the usage and characteristics of the data. Data flow processing techniques, such as stream computing, complex event processing, etc., can be used to extract useful information and predict data requirements.

[0135] It is necessary to select a suitable method according to the specific situation, and perform training, verification, and optimization according to the actual data. The statistics and prediction of data requirements are complex issues that need to consider multiple factors, such as data access patterns, characteristics of computing tasks, characteristics of operation units, etc. Therefore, it is very important to flexibly use different methods and technologies, combine domain knowledge and practical experience, and perform statistics and prediction of data requirements.

[0136] S303: Operate the upper unit according to the upper timing; wherein, the upper timing is a pulse signal used for timing control of the upper unit; the upper unit is an operation unit used for performing upper-level service processing and generating service data, and the service data generated by the upper unit is output data; the output data is the input data required by the lower unit for performing lower-level service processing; the lower unit is an operation unit used for generating service data through lower-level service processing.

[0137] This step is the same as S201 in Embodiment 1, so it will not be elaborated here.

[0138] S304: If it is monitored that the upper unit reaches the Nth trigger point of the upper timing sequence, then transmit the Nth stage data in the upper unit to the lower unit; where the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated when the upper service processing of the upper unit runs to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is any natural number in the interval [1, M].

[0139] This step is the same as S202 in Embodiment 1, so it will not be elaborated here.

[0140] S305: According to the lower timing sequence, control the lower unit to perform lower service processing based on the Nth stage data to obtain the service data of the Nth stage; where the lower timing sequence is a pulse signal used to control the timing of the lower unit.

[0141] This step is the same as S203 in Embodiment 1, so it will not be elaborated here.

[0142] Embodiment 3:

[0143] Please refer to Figure 4 , this application provides a data scheduling device 1 for a domain control computing power model. There is at least one computing unit in the domain control computing power model;

[0144] The device includes:

[0145] An upper control module 43, configured to operate the upper unit according to the upper timing sequence; where the upper timing sequence is a pulse signal used to control the timing of the upper unit; the upper unit is a computing unit used to perform upper service processing and generate service data, and the service data generated by the upper unit is output data; the output data is the input data required for the lower unit to perform lower service processing; the lower unit is a computing unit used to generate service data through lower service processing;

[0146] A data transmission module 44, configured to, if it is monitored that the upper unit reaches the Nth trigger point of the upper timing sequence, then transmit the Nth stage data in the upper unit to the lower unit; where the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated when the upper service processing of the upper unit runs to the Nth trigger point; there are M time nodes in the pulse signal;; M is a natural number, and N is a natural number greater than or equal to 1 and less than or equal to M;

[0147] A lower control module 45, configured to control the lower unit to perform lower service processing based on the Nth stage data according to the lower timing sequence to obtain the service data of the Nth stage; where the lower timing sequence is a pulse signal used to control the timing of the lower unit.

[0148] Optionally, the data scheduling device 1 further includes:

[0149] The upper and lower position recognition module 41 is used to obtain the service processing information of each operation unit; wherein, the service processing information records the unit input data and unit output data of the operation unit; the unit input data is the service data required by the operation unit when performing service processing; the unit output data is the service data generated by the operation unit when completing service processing.

[0150] According to the service processing information of each operation unit, determine the upper and lower position relationships between the operation units in the domain control computing power model; wherein, the upper and lower position relationships are used to determine the upper unit and lower unit in two operation units.

[0151] The node recognition module 42 is used to obtain the service process information of each operation unit; wherein, the service process information records the service processing process of the operation unit, as well as the stage input data and stage output data generated during the service processing process; the service processing process includes at least one service stage; the stage input data is the service data required by the operation unit when running a service stage; the stage output data is the service data generated by the operation unit when running a service stage.

[0152] According to the service process information of each operation unit, determine the time node of the upper timing; wherein, the time node represents the node when the upper node completes the service stage in the upper timing.

[0153] Embodiment 4:

[0154] To achieve the above object, the present application further provides a computer device 5, including: a processor 52 and a memory 51 communicatively connected to the processor 52; the memory stores computer execution instructions.

[0155] The processor executes the computer execution instructions stored in the memory 51 to implement the data scheduling method of the above domain control computing power model. Among them, the components of the data scheduling device of the domain control computing power model can be dispersed in different computer devices. The computer device 5 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, a rack server, a blade server, a tower server or a cabinet server (including an independent server, or a server cluster composed of multiple application servers) that executes the program, etc. The computer device of this embodiment at least includes but is not limited to: a memory 51 and a processor 52 that can communicate with each other through a system bus, as Figure 5 shown. It should be noted that Figure 5Only a computer device with components - is shown, but it should be understood that it is not required to implement all the shown components, and more or fewer components can be alternatively implemented. In this embodiment, the memory 51 (i.e., the readable storage medium) includes flash memory, hard disk, multimedia card, card - type memory (e.g., SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read - only memory (ROM), electrically erasable programmable read - only memory (EEPROM), programmable read - only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 51 can be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 51 can also be an external storage device of the computer device, such as a plug - in hard disk equipped on the computer device, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Of course, the memory 51 can also include both the internal storage unit and the external storage device of the computer device. In this embodiment, the memory 51 is generally used to store the operating system installed on the computer device and various application software, such as the program code of the data scheduling device of the domain control computing power model in Embodiment 3. In addition, the memory 51 can also be used to temporarily store various data that have been output or are to be output. The processor 52 can be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data - processing chips in some embodiments. The processor 52 is generally used to control the overall operation of the computer device. In this embodiment, the processor 52 is used to run the program code stored in the memory 51 or process data, such as running the data scheduling device of the domain control computing power model to implement the data scheduling method of the domain control computing power model in the above - mentioned embodiment.

[0156] The integrated modules implemented in the form of software functional modules can be stored in a computer-readable storage medium. The above software functional modules are stored in a storage medium and include several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute some steps of the methods of various embodiments of the present application. It should be understood that the above processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being executed and completed by a hardware processor, or can be executed and completed by a combination of hardware and software modules in the processor. The memory may include high-speed RAM memory, and may also include non-volatile storage NVM, such as at least one disk memory, and can also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disc, etc.

[0157] To achieve the above object, the present application also provides a computer-readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (such as an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disc, a server, an App application mall, etc., on which computer-executable instructions are stored, and when the program is executed by the processor 52, the corresponding functions are realized. The computer-readable storage medium of this embodiment is used to store computer-executable instructions for implementing the data scheduling method of the domain control computing power model, and when executed by the processor 52, the data scheduling method of the domain control computing power model in the above embodiment is realized.

[0158] The above storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disc. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0159] An exemplary storage medium is coupled to a processor, enabling the processor to read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an Application Specific Integrated Circuit (ASIC). Of course, the processor and the storage medium can also exist as discrete components in an electronic device or a master device.

[0160] This application provides a computer program product, including a computer program, which implements the data scheduling method of the above domain control computing power model when executed by a processor.

[0161] It should be noted that in this document, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0162] Those skilled in the art will readily conceive of other embodiments of this application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of this application, which follow the general principles of this application and include common general knowledge or conventional technical means in the technical field not disclosed in this application. The specification and examples are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the following claims.

[0163] It should be understood that this application is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is only limited by the appended claims.

Claims

1. A data scheduling method for a domain control computing power model, characterized in that, The domain control computing power model has at least one arithmetic unit; The method includes: Running the upper unit according to the upper timing; wherein, the upper timing is a pulse signal for timing control of the upper unit; the upper unit is an arithmetic unit for processing upper services and generating service data, and the service data generated by the upper unit is output data; the output data is input data required for the lower unit to perform lower services; the lower unit is an arithmetic unit for generating service data through lower service processing; If it is monitored that the upper unit reaches the Nth trigger point of the upper timing, then transmit the Nth stage data in the upper unit to the lower unit; wherein, the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated by the upper service processing of the upper unit when running to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is a natural number greater than or equal to 1 and less than or equal to M; Control the lower unit according to the lower timing to perform lower service processing based on the Nth stage data to obtain the service data of the Nth stage; wherein, the lower timing is a pulse signal for timing control of the lower unit.

2. The data scheduling method according to claim 1, wherein Running the upper unit according to the upper timing includes: Obtain two arithmetic units in the domain control computing power model that belong to the upper-lower relationship through a preset index tree, and determine the upper unit and the lower unit in the two arithmetic units according to the upper-lower relationship; wherein, the index tree represents the association relationship between the arithmetic units in the domain control computing power model; the upper-lower relationship represents the dependency relationship between two arithmetic units; If it is monitored that the upper unit receives service data, then send the upper timing to the upper unit; wherein, the service data received by the upper unit is the input data for the upper unit to implement upper service processing; Control the upper unit according to the upper timing to perform upper service processing based on the service data received by the upper unit, so that the upper unit generates service data.

3. The data scheduling method according to claim 1, characterized in that If it is monitored that the upper unit reaches the Nth trigger point of the upper timing, then transmitting the Nth stage data in the upper unit to the lower unit includes: Monitor the running time of the upper node. If it is determined that the running time reaches the Nth trigger point of the upper timing, then obtain the Nth stage data generated by the upper node; Transmit the Nth stage data to the lower unit through a preset network communication bus.

4. The data scheduling method according to claim 1, characterized in that, Controlling the lower unit according to the lower timing to perform lower service processing based on the Nth stage data includes: Obtain the lower unit in the domain control computing power model that has an upper-lower relationship with the upper unit through a preset index tree; wherein, the index tree represents the association relationship between the arithmetic units in the domain control computing power model; the upper-lower relationship represents the dependency relationship between two arithmetic units; Output the lower-level timing to the lower-level unit, and control the lower-level unit to perform lower-level service processing according to the data in the Nth stage through the lower-level timing, so that the lower-level unit generates service data in the Nth stage.

5. The data scheduling method according to claim 1, wherein Before running the upper-level unit according to the upper-level timing, it further includes: Obtain the service processing information of each arithmetic unit; wherein, the service processing information records the unit input data and unit output data of the arithmetic unit; the unit input data is the service data required by the arithmetic unit during service processing; the unit output data is the service data generated by the arithmetic unit after completing service processing. According to the service processing information of each arithmetic unit, determine the upper and lower position relationships between the arithmetic units in the domain control computing power model; wherein, the upper and lower position relationships are used to determine the upper-level unit and the lower-level unit in two arithmetic units.

6. The data scheduling method according to claim 5, wherein Determining the upper and lower position relationships between the arithmetic units in the domain control computing power model according to the service processing information of each arithmetic unit includes: If it is determined that the target unit output data matches the target unit input data, set the arithmetic unit corresponding to the target unit output data as the upper-level unit, and set the arithmetic unit corresponding to the target unit input data as the lower-level unit; wherein, the target unit output data is one of the unit output data of at least one arithmetic unit; the target unit input data is one of the unit input data of at least one arithmetic unit.

7. The data scheduling method according to claim 1, wherein Before running the upper-level unit according to the upper-level timing, it further includes: Obtain the service process information of each arithmetic unit; wherein, the service process information records the service processing process of the arithmetic unit, as well as the stage input data and stage output data generated during the service processing process; the service processing process includes at least one service stage; the stage input data is the service data required by the arithmetic unit when running a service stage; the stage output data is the service data generated by the arithmetic unit when running a service stage. According to the service process information of each arithmetic unit, determine the time node of the upper-level timing; wherein, the time node represents the node when the upper-level node completes the service stage in the upper-level timing.

8. The data scheduling method according to claim 7, wherein Determining the time node of the upper-level timing according to the service process information of each arithmetic unit includes: Obtain two arithmetic units with an upper and lower position relationship in the domain control computing power model, and identify the upper-level unit and the lower-level unit in the two arithmetic units. Identify the stage output data in the upper-level unit that matches the stage input data of the lower-level unit, and determine the service stage corresponding to the identified stage output data. Set the position corresponding to the determined service stage in the upper-level timing corresponding to the upper-level unit as the time node.

9. A data scheduling device for a domain control computing power model, characterized in that, There is at least one arithmetic unit in the domain control computing power model; The device includes: The upper control module is used to operate the upper unit according to the upper timing; wherein, the upper timing is a pulse signal for timing control of the upper unit; the upper unit is an arithmetic unit for processing upper services and generating service data, and the service data generated by the upper unit is output data; the output data is the input data required by the lower unit for lower service processing; the lower unit is an arithmetic unit for generating service data through lower service processing; The data transmission module is used to transmit the Nth stage data in the upper unit to the lower unit if it is monitored that the upper unit reaches the Nth trigger point of the upper timing; wherein, the Nth trigger point is the Nth time node on the pulse signal; the Nth stage data is the service data generated by the upper service processing of the upper unit when it runs to the Nth trigger point; there are M time nodes in the pulse signal; M is a natural number, and N is any natural number in the interval [1, M]; The lower control module is used to control the lower unit to perform lower service processing according to the Nth stage data according to the lower timing, and obtain the service data of the Nth stage; wherein, the lower timing is a pulse signal for timing control of the lower unit.

10. A computer device, characterized in that, Comprising: A processor and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the data scheduling method of the domain control computing power model according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by the processor, they are used to implement the data scheduling method of the domain control computing power model according to any one of claims 1 to 8.

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