FPGA synchronous serial bus duty ratio processing method based on communication sequence pre-training

Abstract

The invention belongs to the technical field of information communication, and relates to an FPGA (Field Programmable Gate Array) synchronous serial bus duty ratio processing method based on communication sequence pre-training, which considers the influence of different factors such as temperature, layout and wiring, use of peripheral devices and the like on channel associated clock skew and distortion in a synchronous serial bus interface, and utilizes a '0' and '1' test sequence to process the duty ratio of the synchronous serial bus. The FPGA is divided into a master FPGA and a slave FPGA in a current application environment, the duty ratio of master transmitting and slave receiving is adjusted or the duty ratio of slave transmitting and master receiving is adjusted, and a duty ratio mode which is most suitable for the current application scene is adjusted in a self-adaptive mode. According to the invention, the accuracy and reliability of the FPGA serial synchronous communication bus are improved, and the bit error rate is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of information and communication technologies, and particularly relates to a method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training. Background Art

[0002] With the rapid development of synchronous serial technology, improving the communication rate between an FPGA and an external serial bus has become a common pursuit in the field of FPGA serial communication. High-speed synchronous serial buses can well meet the requirements of different fields in terms of cost, anti-interference, communication efficiency, etc. Correspondingly, they also pose higher requirements for the reliability and accuracy of communication.

[0003] Ideally, during the communication process between an FPGA and an external synchronous serial bus, the serial data corresponds to the clock on the same path. Taking the example that the transmitting end sends data at the falling edge of the clock on the same path and the receiving end receives data at the rising edge of the clock on the same path, the falling edge of the clock on the same path is aligned with the edge of each bit of serial data, and the rising edge of the clock on the same path is exactly in the middle position of each bit of serial data. The level at the middle position of the data is the most stable and the reception is the most accurate, as Figure 1 shown. However, in actual application scenarios, the communication accuracy of synchronous serial buses is affected by many factors such as temperature, layout and wiring, and peripheral devices. When the FPGA and its peripheral devices are at different operating temperatures, it may cause distortion of the duty cycle of the clock on the same path, or cause a certain offset between the serial data and the clock on the same path, resulting in a certain offset between the rising edge of the clock on the same path and the middle position of the serial data. Especially in the case of a relatively high communication rate, when the receiving end collects data at the rising edge of the clock on the same path, it may collect the edge position of the data, resulting in communication errors.

[0004] Currently, there are various methods to improve the communication accuracy of high-speed synchronous serial buses. For example, in terms of hardware, the equal-length processing method is often used to try to ensure that the time delays of the serial data and the clock on the same path are consistent. However, this method cannot avoid the influence of devices such as external optocouplers on the distortion of the clock signal on the same path, and this method does not have portability, and corresponding processing needs to be carried out again for different hardware.

[0005] In terms of software, a duty cycle configuration function can be added to the FPGA. When communication errors occur in the external synchronous serial bus in a certain application environment, the duty cycle of the transmitting clock can be reconfigured according to the relative relationship between the current clock on the same path and the serial data. By changing the duty cycle of the clock, ensure that the rising edge of the clock on the same path is aligned with the relatively stable part in the middle position of the data, thereby ensuring the accuracy of reception. However, this method is not self-adaptive and requires manual selection of an appropriate duty cycle adjustment method according to the current reception situation to improve the reception accuracy.

[0006] In summary, the existing methods cannot adaptively solve the problem that when the FPGA communicates with an external synchronous serial bus in different environments, the serial data is unstable when received at the rising edge of the clock on the same path, and cannot adaptively improve the accuracy of reception. Summary of the Invention

[0007] (1) Technical Problem to be Solved

[0008] The technical problem to be solved by the present invention is how to provide a method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training to solve the problem that when the FPGA communicates with an external synchronous serial bus in different environments, the serial data is unstable when received at the rising edge of the clock on the same path.

[0009] (2) Technical Solution

[0010] To solve the above technical problem, the present invention proposes a method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training. The FPGA is divided into a master FPGA and a slave FPGA. The method includes the following steps:

[0011] Step 1: Taking the sampling clock CLK of the synchronous serial interface module in the master FPGA M as a reference, calculate the number of sampling points N of the high-level duration of the clock on the same path sent by the master FPGA in the initialization state Mp and the number of sampling points N of the low-level duration of the clock on the same path Mn ;

[0012] Step 2: The master FPGA configures the clock on the same path with the number of sampling points N of the high-level duration of the clock on the same path Mp and the number of sampling points N of the low-level duration of the clock on the same path Mn as the clock on the same path, and continuously sends a communication sequence for pre-training to the slave FPGA at the falling edge of the clock, and the sequence data content is alternating "0" and "1";

[0013] Step 3: The slave FPGA receives the serial data sent by the master FPGA. Then, analyze and calculate the duty cycle of the clock on the same path of the serial data, and calculate the number of effective time sampling points N Sq before the rising edge of the clock on the same path of the serial data received by the slave FPGA and the number of effective time sampling points N Sh after the rising edge of the clock on the same path of the serial data received by the slave FPGA;

[0014] Step 4: According to N Sq and N Sh , judge the relative position between the clock on the same path received by the slave FPGA and the serial data;

[0015] Step 5. Determine the specific offset of the rising edge of the received clock data from the middle position of the received data in the FPGA:

[0016] If N Sq > N Sh , the FPGA continuously sends the data "0" to the main FPGA at the falling edge of the clock;

[0017] Otherwise, the FPGA continuously sends the data "1" to the main FPGA at the falling edge of the clock;

[0018] Step 6. The synchronous serial receiving module of the main FPGA samples the received data according to the rising edge of the received clock data and continuously detects the status of the received data.

[0019] 2. A method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training according to claim 1, wherein in step 1, N Mp and N Mn The specific calculation method of the initial value is:

[0020]

[0021] Wherein, CLK M is the sampling clock of the synchronous serial interface module in the main FPGA, f is the baud rate of the synchronous serial bus, and

[0022]

[0023] Furthermore, step 3 includes:

[0024] When the FPGA detects the change edge of the received data, it starts timing in units of the sampling clock CLK S of the synchronous serial interface module of the FPGA until the rising edge of the clock data is received, and the FPGA receiving module stops timing. The timing result at this time is recorded as N Sq ;

[0025] When the FPGA detects the rising edge of the clock data, it starts timing in units of the sampling clock CLK S of the synchronous serial interface module of the FPGA until the change edge of the received data is received, and the FPGA receiving module stops timing. The timing result at this time is recorded as N Sh .

[0026] Furthermore, step 4 includes:

[0027] If |N Sq - N Sh | < 0.2 × (N Sq + N Sh) No duty cycle adjustment is required. The FPGA continuously sends a communication sequence to the master FPGA at the falling edge of the clock. The sequence content alternates between a continuous series of a "0"s and a continuous series of a "1"s, where a is a positive integer. Then, go to step 6;

[0028] Otherwise, duty cycle adjustment is required. Go to step 5.

[0029] Furthermore, in step 6,

[0030] If the master FPGA detects that all 2a sampling points are "1", the master FPGA adjusts the duty cycle of its transmitted clock with data. Decrease the number of sampling points N for the high-level duration of the clock with data by 1, and increase the number of sampling points N for the low-level duration of the clock with data by 1. The adjustment formula is: Mp Subtract 1 from the number of sampling points N for the high-level duration of the clock with data, Mn Add 1 to the number of sampling points N for the low-level duration of the clock with data. The adjustment formula is:

[0031] N Mp ′ = N Mp - 1,

[0032] N Mn ′ = N Mn + 1,

[0033] With the adjusted number of sampling points N Mp ′ for the high-level duration of the clock with data and the adjusted number of sampling points N Mn ′ for the low-level duration of the clock with data, continuously send the "0""1" communication sequence to the slave FPGA in alternation, and go back to step 3;

[0034] If the master FPGA detects that all 2a sampling points are "0", the master FPGA adjusts the duty cycle of its transmitted clock. Increase the number of sampling points N for the high-level duration of the clock with data by 1, and decrease the number of sampling points N for the low-level duration of the clock with data by 1. The adjustment formula is: Mp Add 1 to the number of sampling points N for the high-level duration of the clock with data, Mn Subtract 1 from the number of sampling points N for the low-level duration of the clock with data. The adjustment formula is:

[0035] N Mp ′ = N Mp + 1,

[0036] N Mn ′ = N Mn - 1,

[0037] With the adjusted number of sampling points N Mp ′ for the high-level duration of the clock with data and the adjusted number of sampling points N Mn ′ for the low-level duration of the clock with data, continuously send the "0""1" communication sequence to the slave FPGA in alternation, and go back to step 3;

[0038] If the master FPGA detects that among the 2a sampling points, there are both "0"s and "1"s, then no duty cycle adjustment is performed.

[0039] The present invention also proposes a method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training. The FPGA is divided into a master FPGA and a slave FPGA, and the method includes the following steps:

[0040] Step 1: Taking the sampling clock CLK of the synchronous serial interface module in the slave FPGA S as a reference, calculate the number of sampling points N of the high-level duration of the clock along with the data sent by the slave FPGA in the initial state Sp and the number of sampling points N of the low-level duration of the clock along with the data Sn ;

[0041] Step 2: The slave FPGA configures the clock along with the data with the number of sampling points N of the high-level duration of the clock along with the data Sp and the number of sampling points N of the low-level duration of the clock along with the data Sn as the clock along with the data, and continuously sends a communication sequence for pre-training to the master FPGA at the falling edge of the clock. The sequence content alternates between "0" and "1";

[0042] Step 3: After the master FPGA receives the serial data sent by the slave FPGA, analyze and calculate the duty cycle of the clock along with the data of the serial data, and calculate the number of effective time sampling points N of the serial data received by the master FPGA before the rising edge of the clock along with the data Mq and the number of effective time sampling points N of the serial data received by the master FPGA after the rising edge of the clock along with the data Mh ;

[0043] Step 4: According to N Mq and N Mh , judge the relative position between the clock along with the data received by the master FPGA and the serial data;

[0044] Step 5: The master FPGA judges the specific offset of the rising edge of the received clock along with the data from the middle position of the received data:

[0045] If N Mq > N Mh , then the master FPGA continuously sends the data "0" to the slave FPGA at the falling edge of the clock;

[0046] Otherwise, the master FPGA will continuously send the data "1" to the slave FPGA at the falling edge of the clock;

[0047] Step 6: The synchronous serial receiving module of the slave FPGA samples the received data according to the rising edge of the received clock along with the data, and continuously detects the state of the received data.

[0048] Further, in step 1, N Sp and N SnThe specific calculation method of the initial value is as follows:

[0049]

[0050] Among them, CLK S is the sampling clock of the synchronous serial interface module in the FPGA, and f is the baud rate of the synchronous serial bus.

[0051] Furthermore, in step 3,

[0052] When the master FPGA detects the change edge of the received data, it starts timing with the sampling clock CLK M of the synchronous serial interface module of the master FPGA until the rising edge of the accompanying clock appears, and the master FPGA receiving module stops timing. The timing result at this time is recorded as N Mq ;

[0053] When the master FPGA detects the rising edge of the accompanying clock, it starts timing with the sampling clock CLK M of the synchronous serial interface module of the master FPGA until the change edge of the received data appears, and the FPGA receiving module stops timing. The timing result at this time is recorded as N Mh .

[0054] Furthermore, in step 4,

[0055] If |N Mq - N Mh | < 0.2 × (N Mq + N Mh ), then there is no need to adjust the duty cycle. The master FPGA sends a communication sequence to the slave FPGA at the falling edge of the clock. The sequence content is alternating between continuous b "0"s and continuous b "1"s. Among them, b is a positive integer, and it goes to step 6;

[0056] Otherwise, it is necessary to adjust the duty cycle, and it goes to step 5.

[0057] Furthermore, in step 6,

[0058] If the slave FPGA detects that 2b sampling points are all "1", then the slave FPGA adjusts the duty cycle of its own transmission clock, subtracts 1 from the number of sampling points N Sp for the high-level duration of the accompanying clock, and adds 1 to the sampling time N Sn for the low-level duration of the accompanying clock. The adjustment formula is:

[0059] N Sp ' = N Sp - 1,

[0060] N Sn ' = N Sn + 1,

[0061] Sample point number N of the adjusted in-channel clock high-level duration Sp ′ and sample time N of the adjusted in-channel clock low-level duration Sn ′ continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3;

[0062] If the slave FPGA detects that all 2b sample points are "0", the slave FPGA adjusts the duty cycle of its own transmitted clock, and increases the sample point number N of the adjusted in-channel clock high-level duration Sp by 1, and decreases the sample point number N of the adjusted in-channel clock low-level duration Sn by 1. The adjustment formula is:

[0063] N Sp ′ = N Sp + 1,

[0064] N Sn ′ = N Sn - 1,

[0065] With the adjusted sample point number N of the in-channel clock high-level duration Sp ′ and the adjusted sample time N of the in-channel clock low-level duration Sn ′ continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3;

[0066] If the slave FPGA detects both "0" and "1" among the 2b sample points, no duty cycle adjustment is performed.

[0067] (III) Beneficial effects

[0068] The present invention proposes a method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training. The present invention considers the influence of different factors such as temperature, layout and wiring, and the use of peripheral devices on the in-channel clock offset and distortion in the synchronous serial bus interface. Using the "0" and "1" test sequences, the FPGA is divided into a master FPGA and a slave FPGA in the current application environment, and the master-transmit slave-receive duty cycle and / or the slave-transmit master-receive duty cycle are adjusted to adaptively adjust the duty cycle mode most suitable for the current application scenario, improving the accuracy and reliability of the FPGA serial synchronous communication bus and reducing the bit error rate. Description of the drawings

[0069] Figure 1 Schematic diagram of the relative relationship between the rising edge of the synchronous serial bus clock and the received serial data;

[0070] Figure 2 Flowchart of the FPGA synchronous serial bus interaction mechanism based on the master-transmit slave-receive line duty cycle preprocessing of the master FPGA;

[0071] Figure 3 It is a flowchart of the FPGA synchronous serial bus interaction mechanism based on the duty cycle preprocessing of the master - transmit - slave - receive line of the FPGA;

[0072] Figure 4 It is a flowchart of the FPGA synchronous serial bus interaction mechanism based on the duty cycle preprocessing of the slave - transmit - master - receive line of the master FPGA;

[0073] Figure 5 It is a flowchart of the FPGA synchronous serial bus interaction mechanism based on the duty cycle preprocessing of the slave - transmit - master - receive line of the slave FPGA;

[0074] Figure 6 It is a schematic diagram of the communication structure in the FPGA duty cycle adjustment mode;

[0075] Figure 7 It is a schematic diagram of the relative relationship between the rising edge of the clock and the received serial data after the clock distortion of the clock on the same path;

[0076] Figure 8 It is a schematic diagram of the relative relationship between the rising edge of the clock after adjusting the duty cycle and the received serial data. Specific implementation manners

[0077] To make the purpose, content and advantages of the present invention clearer, the following combines the drawings and embodiments to further describe the specific implementation manners of the present invention in detail.

[0078] The present invention proposes a method for processing the duty cycle of the FPGA synchronous serial bus based on communication sequence pre - training, and elaborates on the FPGA synchronous serial bus interaction mechanism based on duty cycle preprocessing.

[0079] Two FPGAs that communicate using a synchronous serial bus are divided into a master FPGA and a slave FPGA. The master FPGA is the FPGA that gives priority to data transmission during the communication process and is responsible for the main process control in the duty cycle preprocessing interaction mechanism. The slave FPGA is the FPGA that first receives data during the communication process and is mainly in a subordinate position in the duty cycle preprocessing interaction mechanism, as Figure 6 shown.

[0080] After the communication device is powered on, before the master FPGA and the slave FPGA perform formal synchronous serial bus communication, they are both in the duty cycle adjustment mode to adjust the duty cycle.

[0081] The adjustment of the duty cycle is divided into two parts: the duty cycle adjustment on the master - transmit - slave - receive line and the duty cycle adjustment on the slave - transmit - master - receive line. The clock duty cycle on the master - transmit - slave - receive line is adjusted, as Figure 2 , Figure 3 shown.

[0082] Step 1: Using the sampling clock CLK of the synchronous serial interface module in the main FPGA M (unit: MHz) as a reference, calculate the number of sampling points N for the high-level duration of the clock accompanying the main FPGA in the initialization state Mp and the number of sampling points N for the low-level duration of the clock accompanying the main FPGA Mn . N Mp and N Mn are initialized to be the same by default, that is, the duty cycle of the clock accompanying the main FPGA is 1:2.

[0083] N Mp and N Mn The specific calculation method of the initial values is as follows:

[0084]

[0085] Among them, CLK M (unit: MHz) is the sampling clock of the synchronous serial interface module in the main FPGA, and f (unit: Mbps) is the baud rate of the synchronous serial bus. And to ensure the adjustment accuracy of the duty cycle of the clock accompanying the main FPGA, it is necessary to ensure:

[0086]

[0087] That is, for the transmission or reception of 1 bit of serial valid data, the synchronous serial interface module in the main FPGA can sample it at least 8 times.

[0088] Calculate the initial number of sampling points N for the high-level duration of the clock accompanying the main FPGA Mp and the number of sampling points N for the low-level duration of the clock accompanying the main FPGA Mn Then go to Step 2.

[0089] Step 2: The main FPGA configures the clock accompanying the main FPGA with the number of sampling points N for the high-level duration of the clock accompanying the main FPGA Mp and the number of sampling points N for the low-level duration of the clock accompanying the main FPGA Mn As the clock accompanying the main FPGA, continuously send a communication sequence for pre-training to the slave FPGA at the falling edge of the clock. The sequence data content alternates between "0" and "1", and then go to Step 3.

[0090] Step 3: The slave FPGA receives the serial data sent by the main FPGA. After that, analyze the duty cycle of the clock accompanying the serial data, that is, judge the relative relationship between the rising edge of the clock accompanying the serial data and the received serial data.

[0091] When the slave FPGA detects the change edge (rising edge / falling edge) of the received data, it starts to use the sampling clock CLK of the synchronous serial interface module of the slave FPGA SWhen timing is in units of MHz until the rising edge of the clock on the same path appears, the timing stops at the FPGA receiving module. The timing result at this time is the number of valid time sampling points of the serial data received from the FPGA before the rising edge of the clock on the same path, denoted as N Sq ;

[0092] After detecting the rising edge of the clock on the same path from the FPGA, start timing with the sampling clock CLK of the synchronous serial interface module of the FPGA S When timing is in units of MHz until the change edge (rising edge / falling edge) of the received data appears, the timing stops at the FPGA receiving module. The timing result at this time is the number of valid time sampling points of the received serial data after the rising edge of the clock on the same path, denoted as N Sh , as Figure 7 shown;

[0093] To ensure the adjustment accuracy of the duty cycle of the clock on the same path by the FPGA, it is necessary to ensure that:

[0094]

[0095] That is, for the reception or transmission of 1-bit serial valid data, the synchronous serial interface module in the FPGA can sample it at least 8 times.

[0096] Calculate N in the current application environment Sq and N Sh After that, go to step 4.

[0097] Step 4: According to N Sq and N Sh , judge the relative position between the clock on the same path received from the FPGA and the serial data.

[0098] If |N Sq -N Sh | < 0.2×(N Sq +N Sh ), it means that the valid time of the serial data received from the FPGA before the rising edge of the received clock on the same path and the valid time after the rising edge of the received clock on the same path are close, that is, the rising edge of the clock on the same path is in the middle position of the received data, and no duty cycle adjustment is required, as Figure 8 shown. The FPGA will continuously send a communication sequence to the main FPGA at the falling edge of the clock. The sequence content is alternating between a continuous series of a "0"s and a continuous series of a "1"s. That is, after continuously sending a "0"s on the data line, then continuously send a "1"s, and repeat in a cycle, where a is a positive integer, and the recommended value range is 500 ≤ a ≤ 5000, such as a = 1000. The default initial duty cycle of the clock on the same path sent is 1:2. Go to step 6.

[0099] Otherwise, it means there is a certain gap between the valid time of the serial data received from the FPGA before the rising edge of the received clock on the fly and the valid time after the rising edge of the received clock on the fly. The rising edge of the received clock on the fly has a certain offset relative to the middle position of the received serial data, and duty cycle adjustment is required. Go to step 5.

[0100] Step 5. Determine the specific offset of the rising edge of the received clock on the fly from the middle position of the received data from the FPGA:

[0101] If N Sq > N Sh , it means that the valid time of the data received from the FPGA before the rising edge of the received clock is longer than the valid time after the rising edge of the received clock, that is, the rising edge of the received clock is at the position behind the received data. In this case, the FPGA will continuously send data "0" to the main FPGA at the falling edge of the clock, that is, the data line is continuously pulled low, and the default initial duty cycle of the clock on the fly sent is 1:2;

[0102] Otherwise, it means that the valid time of the data received from the FPGA before the rising edge of the received clock is shorter than the valid time after the rising edge of the received clock, that is, the rising edge of the received clock is at the position in front of the received data. In this case, the FPGA will continuously send data "1" to the main FPGA at the falling edge of the clock, that is, the data line is continuously pulled high, and the default initial duty cycle of the clock on the fly sent is 1:2. Go to step 6.

[0103] Step 6. The synchronous serial receiving module of the main FPGA samples the received data according to the rising edge of the received clock on the fly and continuously detects the status of the received data.

[0104] If the main FPGA detects that all 2a sampling points are "1", it means that on the main sending and slave receiving line, the FPGA detects that the valid time of the received data before the rising edge of the received clock on the fly is shorter than the valid time after the rising edge of the received clock, that is, the rising edge of the received clock is at the position in front of the received data. At this time, the main FPGA needs to adjust the duty cycle of its own sent clock on the fly, subtract one from the sampling point number N of the high-level duration of the clock on the fly, and add one to the sampling point number N of the low-level duration of the clock on the fly. The specific adjustment formula is as follows. Go back to step 2 and continuously send the "0" "1" communication sequence to the FPGA with the adjusted N Mp ' and N Mn '. Mp ' and N Mn ' to the FPGA alternately.

[0105] N Mp ' = N Mp - 1

[0106] N Mn ' = N Mn + 1

[0107] If the master FPGA detects that all 2a sampling points are "0", it means that on the master transmit - slave receive line, the slave FPGA detects that the valid time of the received data before the rising edge of the receive clock - associated is longer than the valid time after the rising edge of the receive clock, that is, the rising edge of the receive clock is at a position behind the received data. At this time, the master FPGA needs to adjust the duty cycle of its own transmit clock, increasing the sampling points N of the high - level duration of the clock - associated by 1 and decreasing the sampling points N of the low - level duration of the clock - associated by 1. The specific adjustment formula is as follows. Return to step 2 and alternately send the "0""1" communication sequence to the slave FPGA with the adjusted N' and N'. Mp Add 1 to the sampling points N of the high - level duration of the clock - associated Mn Subtract 1 from the sampling points N of the low - level duration of the clock - associated. Specifically, the adjustment formula is as follows. Return to step 2 and alternately send the "0""1" communication sequence to the slave FPGA with the adjusted N' and N'. Mp ′ and N Mn ′ continuously to the slave FPGA.

[0108] N Mp = N Mp + 1

[0109] N Mn ′ = N Mn - 1

[0110] If the master FPGA detects that there are both "0" and "1" among the 2a sampling points, it means that on the master transmit - slave receive line, the slave FPGA detects that the valid time of the received serial data before the rising edge of the receive clock - associated is close to the valid time after the rising edge of the receive clock - associated, that is, the rising edge of the clock - associated is at a position in the middle of the received data, and no duty - cycle adjustment is required. The currently used high - low level configuration of the clock - associated is the more appropriate configuration method on the master transmit - slave receive line. At this time, the duty cycle is N':(N' + N'), and the duty - cycle adjustment of the master transmit - slave receive line ends. Mp ′:(N Mp ’ + N Mn ’), and the duty - cycle adjustment of the master transmit - slave receive line ends.

[0111] The following are the detailed steps for the duty - cycle adjustment of the slave transmit - master receive line, as shown in Figure 4 、 Figure 5 :

[0112] Step 1. The duty cycle of the master transmit - slave receive line has been adjusted. Start to adjust the duty cycle of the slave transmit - master receive line. Based on the sampling clock CLK S (unit: MHz) in the slave FPGA, calculate the sampling points N of the high - level duration of the clock - associated sent by the slave FPGA and the sampling points N of the low - level duration of the clock - associated in the initialization state. N and N are initialized to be the same by default, that is, the duty cycle of the clock - associated is 1:2. Sq and the sampling points N of the low - level duration of the clock - associated Sn . N Sp and N Sn are initialized to be the same by default, that is, the duty cycle of the clock - associated is 1:2.

[0113] NSp and N Sn The specific calculation method of the initial value is as follows:

[0114]

[0115] Among them, CLK S (unit: MHz) is the sampling clock of the synchronous serial interface module in the FPGA, and f (unit: Mbps) is the baud rate of the synchronous serial bus.

[0116] Calculate the initial high-level duration N of the clock on the same path Sp and the low-level duration N of the clock on the same path Sn Then go to step 2.

[0117] Step 2: Sample the number of points N of the high-level duration of the clock on the same path from the FPGA Sp and the number of points N of the low-level duration of the clock on the same path Sn Configure for the clock on the same path, and continuously send the communication sequence for pre-training to the main FPGA at the falling edge of the clock. The sequence content alternates between "0" and "1", and then go to step 3.

[0118] Step 3: The main FPGA receives the serial data sent by the slave FPGA. After that, analyze the duty cycle of the clock on the same path of the serial data, that is, judge the relative relationship between the rising edge of the clock on the same path and the received serial data.

[0119] When the main FPGA detects the change edge (rising edge / falling edge) of the received data, start timing with the sampling clock CLK M (unit: MHz) of the synchronous serial interface module of the main FPGA as the unit until the rising edge of the clock on the same path appears. The main FPGA receiving module stops timing. At this time, the timing result is the number of effective time sampling points of the serial data received by the main FPGA before the rising edge of the clock on the same path, denoted as N Mq ;

[0120] When the main FPGA detects the rising edge of the clock on the same path, start timing with the sampling clock CLK M (unit: MHz) of the synchronous serial interface module of the main FPGA as the unit until the change edge (rising edge / falling edge) of the received data appears. The main FPGA receiving module stops timing. At this time, the timing result is the number of effective time sampling points of the received serial data after the rising edge of the clock on the same path, denoted as N Mh , as Figure 7 shown;

[0121] Calculate N Mq and N Mh in the current application environment, and then go to step 4.

[0122] Step 4: Based on N Mq and N Mh , determine the relative position between the clock on the same path received by the main FPGA and the serial data.

[0123] If |N Mq -N Mh | < 0.2×(N Mq +N Mh ), it means that the valid time of the serial data received by the main FPGA before the rising edge of the clock on the same path and the valid time after the rising edge of the clock on the same path are close, that is, the rising edge of the clock on the same path is at the middle position of the received data, and no duty cycle adjustment is required. As shown in Figure 8 . The main FPGA will continuously send a communication sequence to the slave FPGA at the falling edge of the clock. The sequence content is alternating between continuous b "0"s and continuous b "1"s. That is, after continuously sending b "0"s on the data line, then continuously send b "1"s, and repeat in a cycle, where b is a positive integer, and the recommended value range is 500 ≤ b ≤ 5000, such as b = 1000. The default duty cycle of the clock on the same path sent is 1:2. Go to Step 6.

[0124] Otherwise, it means that there is a certain gap between the valid time of the serial data received by the main FPGA before the rising edge of the clock on the same path and the valid time after the rising edge of the clock on the same path. There is a certain offset of the rising edge of the received clock on the same path relative to the middle position of the received serial data, and duty cycle adjustment is required. Go to Step 5.

[0125] Step 5: The main FPGA determines the specific offset of the rising edge of the received clock on the same path from the middle position of the received data:

[0126] If N Mq > N Mh , it means that the valid time of the data received by the main FPGA before the rising edge of the received clock is longer than the valid time after the rising edge of the received clock, that is, the rising edge of the received clock is at a position behind the received data. In this case, the main FPGA will continuously send the data "0" to the slave FPGA at the falling edge of the clock, that is, the data line is continuously pulled low, and the duty cycle of the clock on the same path is the duty cycle of the main sending and slave receiving line finally determined in Step 6 of the duty cycle adjustment of the main sending and slave receiving line (the high-level duration N Mp ′, the low-level duration N Mn ′).

[0127] Otherwise, it means that the valid time of the received data before the rising edge of the receive clock is shorter than the valid time after the rising edge of the receive clock, that is, the rising edge of the receive clock is at a position ahead of the received data. In this case, the master FPGA will continuously send the data "1" to the slave FPGA at the falling edge of the clock, that is, the data line is continuously pulled high, and the duty cycle of the accompanying clock is the master-transmit slave-receive duty cycle finally determined in step 6 of the duty cycle adjustment of the master-transmit slave-receive line (high-level duration N Mp ′, low-level duration N Mn ′), and go to step 6.

[0128] Step 6: The synchronous serial receiving module of the slave FPGA samples the received data according to the rising edge of the received accompanying clock and continuously detects the status of the received data.

[0129] If the slave FPGA detects that all 2b sampling points are "1", it means that on the slave-transmit master-receive line, the master FPGA detects that the valid time of the received data before the rising edge of the received accompanying clock is shorter than the valid time after the rising edge of the received accompanying clock, that is, the rising edge of the receive clock is at a position ahead of the received data. At this time, the slave FPGA needs to adjust the duty cycle of its own transmission clock, subtract one from the sampling points N Sp of the high-level duration of the accompanying clock, and add one to the sampling time N Sn of the low-level duration of the accompanying clock. The specific adjustment formula is as follows. Return to step 2 and continuously send the "0""1" communication sequence to the slave FPGA with the adjusted N Sp ′ and N Sn ′.

[0130] N Sp ′ = N Sp - 1

[0131] N Sn ′ = N Sn + 1

[0132] If the slave FPGA detects that all 2b sampling points are "0", it means that on the slave-transmit master line, the master FPGA detects that the valid time of the received data before the rising edge of the received accompanying clock is longer than the valid time after the rising edge of the receive clock, that is, the rising edge of the received accompanying clock is at a position behind the received data. At this time, the slave FPGA needs to adjust the duty cycle of its own transmission clock, add one to the sampling points N Sp of the high-level duration of the accompanying clock, and subtract one from the sampling points N Sn of the low-level duration of the accompanying clock. The specific adjustment formula is as follows. Return to step 2 and continuously send the "0""1" communication sequence to the slave FPGA with the adjusted N Sp ′ and N Sn ′.

[0133] NSp ' = N Sp + 1

[0134] N Sn ' = N Sn - 1

[0135] If there are both "0"s and "1"s among the 2b sampling points detected by the FPGA, it means that on the master-transmit slave-receive line, the master FPGA detects that the hold time of the received serial data before the rising edge of the received slave clock and the hold time after the rising edge of the received slave clock are close, that is, the rising edge of the slave clock is at the middle position of the received data, and no duty cycle adjustment is required. The currently used high and low level configuration of the slave clock is the more appropriate configuration method on the master-transmit slave-receive line, and the duty cycle at this time is N Sp ': (N Sp '+ N' Sn ), the duty cycle adjustment of the master-transmit slave-receive line is completed, and both the master and slave FPGAs are ready and can start normal operation and use.

[0136] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can still be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training, where the FPGA is divided into a master FPGA and a slave FPGA, and is characterized in that, It includes the following steps: Step 1: Using the sampling clock CLK of the synchronous serial interface module in the main FPGA M as a reference, calculate the number of sampling points N for the high-level duration of the clock accompanying the main FPGA transmitted in the initialization state Mp and the number of sampling points N for the low-level duration of the clock accompanying the main FPGA Mn ; Step 2: The main FPGA samples the number of points N for the duration of the high level of the clock on the same path Mp and the number of points N for the duration of the low level of the clock on the same path Mn For the clock configuration on the same path, continuously send the communication sequence for pre-training to the slave FPGA at the falling edge of the clock, and the sequence data content alternates between "0" and "1". Step 3: Receive the serial data sent by the master FPGA from the slave FPGA. Then, analyze and calculate the duty cycle of the clock accompanying the serial data, and calculate the number of effective time sampling points N of the serial data received from the slave FPGA before the rising edge of the clock accompanying the serial data Sq and the number of effective time sampling points N of the serial data received from the slave FPGA after the rising edge of the clock accompanying the serial data sh ; Step 4. According to N Sq and N Sh , determine the relative position between the clock and data received from the FPGA Step 5: Determine the specific offset of the rising edge of the received clock data recovery (CDR) clock from the middle position of the received data in the FPGA; If N Sq > N Sh , the FPGA continuously sends data "0" to the main FPGA at the falling edge of the clock; Otherwise, the FPGA continuously sends data "1" to the master FPGA at the falling edge of the clock; Step 6: The synchronous serial receiving module of the master FPGA samples the received data according to the rising edge of the received CDR clock, and continuously detects the status of the received data.

2. The duty cycle processing method for the FPGA synchronous serial bus based on communication sequence pre-training according to claim 1, characterized in that In Step 1, N Mp and N Mn The specific calculation method for the initial values is as follows: Among them, CLK M is the sampling clock of the synchronous serial interface module in the main FPGA, f is the baud rate of the synchronous serial bus, and 3. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 2, characterized in that Step 3 includes: After detecting the received data change edge from the FPGA, start timing in units of the sampling clock CLK of the synchronous serial interface module of the FPGA S until the rising edge of the accompanying clock appears, and the receiving module of the FPGA stops timing. The timing result at this time is recorded as N Sq ; After detecting the rising edge of the clock on the fly from the FPGA, start timing in units of the sampling clock CLK of the synchronous serial interface module from the FPGA S until the change edge of the received data appears, and the receiving module of the FPGA stops timing. The timing result at this time is recorded as N Sh .

4. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 3, characterized in that Step 4 includes: If |N Sq -N Sh | < 0.2×(N Sq +N Sh ), no duty cycle adjustment is required. Continuously send a communication sequence from the FPGA to the main FPGA at the falling edge of the clock. The sequence content is alternating between a consecutive "0"s and a consecutive "1"s, where a is a positive integer. Go to step 6; Otherwise, the duty cycle needs to be adjusted, and go to Step 5.

5. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 4, characterized in that In Step 6, If the main FPGA detects that all 2a sampling points are "1", the main FPGA adjusts the duty cycle of the clock sent along with the data, decreasing the number of sampling points N for the high-level duration of the clock sent along with the data by 1 and increasing the number of sampling points N for the low-level duration of the clock sent along with the data by 1. The adjustment formula is as follows: Mp Subtract 1 from the number of sampling points N for the high-level duration of the clock sent along with the data Mn and add 1 to the number of sampling points N for the low-level duration of the clock sent along with the data. The adjustment formula is: N Mp ′ = N Mp - 1, N Mn ′ = N Mn + 1, Sample point number N for the adjusted high-level duration of the associated clock Mp ' and sample point number N for the adjusted low-level duration of the associated clock Mn ' continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3; If the main FPGA detects that all 2a sampling points are "0", the main FPGA adjusts the duty cycle of its own transmission clock, increasing the number of sampling points N for the high-level duration of the clock on the same path by 1 and decreasing the number of sampling points N for the low-level duration of the clock on the same path by 1. The adjustment formula is as follows: Mp Increase the number of sampling points N for the high-level duration of the clock on the same path by 1 Mn Decrease the number of sampling points N for the low-level duration of the clock on the same path by 1. The adjustment formula is: N Mp ′ = N Mp + 1, N Mn ′ = N Mn -1, Sampling points N for the high-level duration of the adjusted clock on the same channel Mp ' and sampling points N for the low-level duration of the adjusted clock on the same channel Mn ' Continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3; If the master FPGA detects both "0" and "1" in 2a sampling points, the duty cycle is not adjusted.

6. A method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training. The FPGA is divided into a master FPGA and a slave FPGA, and is characterized in that, It includes the following steps: Step 1: Using the sampling clock CLK from the synchronous serial interface module in the FPGA as a reference, calculate the number of sampling points N of the high-level duration of the clock accompanying the data sent from the FPGA in the initialization state S and the number of sampling points N of the low-level duration of the clock accompanying the data Sp ; Sn ; Step 2: Sample the number of points N for the high-level duration of the clock accompanying the data from the FPGA Sp and the number of points N for the low-level duration of the clock accompanying the data Sn Configure the clock accompanying the data. Continuously send a communication sequence for pre-training to the main FPGA at the falling edge of the clock. The sequence content alternates between "0" and "1". Step 3: After the master FPGA receives the serial data sent by the slave FPGA, analyze and calculate the duty cycle of the clock accompanying the serial data, and calculate the number of effective time sampling points N of the serial data received by the master FPGA before the rising edge of the clock accompanying the serial data Mq and the number of effective time sampling points N of the serial data received by the master FPGA after the rising edge of the clock accompanying the serial data Mh ; Step 4. According to N Mq and N Mh , determine the relative position between the clock on the same path received by the main FPGA and the serial data; Step 5: The master FPGA determines the specific offset of the rising edge of the received CDR clock from the middle position of the received data; If N Mq > N Mh , the master FPGA continuously sends the data "0" to the slave FPGA at the falling edge of the clock; Otherwise, the master FPGA continuously sends data "1" to the slave FPGA at the falling edge of the clock; Step 6: The synchronous serial receiving module of the slave FPGA samples the received data according to the rising edge of the received CDR clock, and continuously detects the status of the received data.

7. A method for processing the duty cycle of an FPGA synchronous serial bus based on communication sequence pre-training according to claim 6, characterized in that In Step 1, N Sp and N Sn The specific calculation method for the initial values is as follows: Among them, CLK S is the sampling clock of the synchronous serial interface module in the FPGA, and f is the baud rate of the synchronous serial bus.

8. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 7, characterized in that In Step 3, After the main FPGA detects the received data change edge, it starts timing with the sampling clock CLK of the main FPGA synchronous serial interface module M until the rising edge of the clock on the same path appears, and the main FPGA receiving module stops timing. The timing result at this time is recorded as N Mq ; After the master FPGA detects the rising edge of the slave clock, it starts timing with the sampling clock CLK of the master FPGA synchronous serial interface module M as the unit until the change edge of the received data appears. The FPGA receiving module stops timing, and the timing result at this time is recorded as N Mh .

9. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 8, characterized in that In Step 4, If |N Mq -N Mh | < 0.2×(N Mq +N Mh ), then no duty cycle adjustment is required. The master FPGA sends a communication sequence to the slave FPGA at the falling edge of the clock. The sequence content is alternating between continuous b "0"s and continuous b "1"s, where b is a positive integer. Go to step 6; Otherwise, the duty cycle needs to be adjusted, and go to Step 5.

10. A duty cycle processing method for an FPGA synchronous serial bus based on communication sequence pre-training according to claim 9, characterized in that, In Step 6, If all 2b sampling points detected from the FPGA are "1", then adjust the duty cycle of the self-transmitted clock from the FPGA, and sample the number of points N for the high-level duration of the channel clock Sp Subtract 1, and sample the time N for the low-level duration of the channel clock Sn Add 1, and the adjustment formula is: N Sp ′ = N Sp -1, N Sn ′ = N Sn + 1, Sampling points N for the high-level duration of the adjusted clock on the same channel Sp ′ and sampling time N for the low-level duration of the adjusted clock on the same channel Sn ′ Continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3; If all 2b sampling points detected from the FPGA are "0", the duty cycle of the self-transmitted clock is adjusted from the FPGA, and the number of sampling points N for the high-level duration of the channel clock is Sp incremented by 1, and the number of sampling points N for the low-level duration of the channel clock is Sn decremented by 1, and the adjustment formula is: N Sp ′ = N Sp + 1, N Sn ′ = N Sn -1, Sample point number N for the adjusted high-level duration of the associated clock Sp ′ and sample time N for the adjusted low-level duration of the associated clock Sn ′ Continuously send the communication sequence of "0" and "1" to the slave FPGA alternately, and return to step 3; If the slave FPGA detects both "0" and "1" in 2b sampling points, the duty cycle is not adjusted.

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