On-chip adjustable delay chip, device and delay adjustment method

Abstract

The invention provides an on-chip adjustable delay chip, an on-chip adjustable delay device and a delay adjustment method, and relates to the technical field of delayers. According to the invention, by arranging the delay fine tuning unit, delay adjustment can be carried out on the chip according to the difference of the actually measured delay amount after the chip is manufactured. The delay fine tuning unit comprises a plurality of transmission lines with different lengths and has a plurality of different delay amounts; based on the length difference between the transmission lines before and after adjustment, the delay can be finely adjusted and reduced by selecting a shorter transmission line, and the delay can be finely adjusted and increased by selecting a longer transmission line. Compared with the length of each transmission line, the length difference between different transmission lines is small, and the delay amount of the delay branch can be finely adjusted by taking the small difference as the adjustment amount on the existing processing technology level. And after fine adjustment, the error range of the delay amount is reduced, so that the delay precision is improved on the basis of the existing processing technology level.

Description

Technical Field

[0001] The present invention relates to the technical field of delay devices, and in particular, to an on-chip adjustable delay chip, device and delay adjustment method. Background Art

[0002] A delay device (also known as a delay line) is an important component in a radio frequency transceiver delay module. In an antenna system, the delay device is used to introduce a delay of an echo signal, so as to realize distance measurement. By adjusting the delay time of the signal, the time difference of signal transmission can be compensated to ensure signal synchronization, thereby improving the performance and reliability of the system. An on-chip delay device is a delay device fabricated on a chip and has the characteristic of high integration. For example, on-chip capacitors, on-chip inductors, and transmission lines are fabricated on a chip substrate to form a delay device.

[0003] The delay amount accuracy of an on-chip delay device is mainly affected by the accuracy of the chip processing technology. For example, the length of the transmission line directly affects the propagation time of the signal, thereby affecting the delay amount. The processing accuracy of the transmission line length determines the accuracy of the delay amount. For another example, the sizes of capacitor and inductor elements directly affect the phase and amplitude of the signal, thereby affecting the delay amount. When a high-precision and large-bit delay device is required for a system, such as a nanosecond-level delay device, higher requirements will be put forward for the accuracy of the technology. For example, by improving the accuracy of processing equipment and the level of process control and reducing processing errors; for another example, optimizing the processing technology to improve the stability and consistency of the technology. However, limited by cost and technical difficulty, it is difficult to implement the method of improving the process level. As a result, the existing on-chip delay line is limited by the processing technology accuracy, with a large delay amount error and a problem of low delay accuracy. Summary of the Invention

[0004] Embodiments of the present invention provide an on-chip adjustable delay chip, device and delay adjustment method to solve the problem that the existing on-chip delay line is limited by the processing technology accuracy and has low delay accuracy.

[0005] In a first aspect, an embodiment of the present invention provides an on-chip adjustable delay chip, including: a delay branch, and a delay fine-tuning unit connected in series with the delay branch;

[0006] The delay fine-tuning unit includes a plurality of transmission lines with different lengths; any one and only one of the transmission lines is used to be connected in series with the delay branch; wherein, before on-chip delay adjustment, the intermediate transmission line with the length closest to the average value among the transmission lines is connected in series with the delay branch;

[0007] The delay fine-tuning unit is configured to, when the measured delay amount of the delay branch is greater than the target delay range, disconnect the intermediate transmission line, and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch;

[0008] The delay fine-tuning unit is further configured to disconnect the intermediate transmission line and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch when the measured delay of the delay branch is less than the target delay range.

[0009] In a possible implementation, the intermediate transmission line is connected in series with the delay branch through an air bridge; correspondingly, the intermediate transmission line is disconnected by disconnecting the air bridge;

[0010] The transmission lines other than the intermediate transmission line are connected in series with the delay branch through wire bonding.

[0011] In a possible implementation, the delay of the delay branch is in the nanosecond level;

[0012] The delay of the delay fine-tuning unit is in the picosecond level.

[0013] In a possible implementation, a delay coarse-tuning unit is further included; the delay coarse-tuning unit is connected in series with the delay branch;

[0014] The delay coarse-tuning unit includes a plurality of different delays;

[0015] The delay of any one of the delay coarse-tuning units is less than the delay of the delay branch, and the delay of any one of the delay coarse-tuning units is greater than the delay of the delay fine-tuning unit.

[0016] In a possible implementation, the delay fine-tuning unit is further configured to keep the intermediate transmission line connected in series with the delay branch when the measured delay of the delay branch does not exceed the target delay range.

[0017] In a possible implementation, the delay coarse-tuning unit is configured to adjust the delay of the delay coarse-tuning unit based on the magnitude relationship between the measured delay of the delay branch and the target delay range, so that the delay chip outputs the target delay.

[0018] In a possible implementation, the delay coarse-tuning unit includes a plurality of delay units connected in series;

[0019] Any one of the delay units includes a delay line, a reference line, and two switching switches;

[0020] The switching switch is used to switch the delay unit between the delay state and the reference state.

[0021] In a possible implementation, the delay branch is a constant-resistance delay network.

[0022] In a second aspect, an embodiment of the present invention provides a delay device, including an on-chip adjustable delay chip in any one of the possible implementations of the first aspect.

[0023] Thirdly, an embodiment of the present invention provides a method for adjusting the delay of an on-chip adjustable delay chip, which is applied to the on-chip adjustable delay chip in any possible implementation manner of the first aspect; the method includes:

[0024] Obtain the target delay range and the measured delay amount of the delay branch;

[0025] If the measured delay amount of the delay branch is greater than the target delay range, control to disconnect the intermediate transmission line, and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch;

[0026] If the measured delay amount of the delay branch is less than the target delay range, disconnect the intermediate transmission line, and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch.

[0027] An embodiment of the present invention provides an on-chip adjustable delay chip, a device and a delay adjustment method. By setting a delay fine-tuning unit, the present invention can perform on-chip delay adjustment according to the difference in the measured delay amount after the chip is manufactured. The delay fine-tuning unit includes multiple transmission lines with different lengths and has multiple different delay amounts; based on the length difference of the transmission lines before and after adjustment, the delay can be finely adjusted and reduced by selecting a shorter transmission line, and the delay can be finely adjusted and increased by selecting a longer transmission line. Compared with the lengths of the respective transmission lines, the length differences between different transmission lines are relatively small, and these small differences can be used as adjustment amounts on the existing processing technology level to finely adjust the delay amount of the delay branch. The error range of the delay amount after fine adjustment is reduced, thereby improving the delay accuracy on the existing processing technology level. Description of the Drawings

[0028] Figure 1 It is a functional block diagram of a delay device provided by an embodiment of the present invention;

[0029] Figure 2 It is an equivalent circuit diagram of a basic unit of a delay constant resistance network provided by an embodiment of the present invention;

[0030] Figure 3 It is a schematic diagram of a MIM capacitor structure provided by an embodiment of the present invention;

[0031] Figure 4 It is a schematic diagram of the non-adjustable single-wafer delay accuracy provided by an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of the structure of a delay coarse adjustment unit provided by an embodiment of the present invention;

[0033] Figure 6 It is a layout schematic diagram of an adjustable delay chip provided by an embodiment of the present invention;

[0034] Figure 7Schematic diagram of the delay fine-tuning unit structure provided by the embodiment of the present invention;

[0035] Figure 8 Schematic diagram of the insertion loss curve of the delay chip provided by the embodiment of the present invention;

[0036] Figure 9 Schematic diagram of the amplitude fluctuation curve of each state of the delay chip provided by the embodiment of the present invention;

[0037] Figure 10 Schematic diagram of the delay amount curve of the delay chip provided by the embodiment of the present invention;

[0038] Figure 11 Schematic diagram of the delay accuracy curve of the delay chip provided by the embodiment of the present invention;

[0039] Figure 12 Schematic diagram of the input voltage standing wave ratio of the zero state and the delay state of the delay chip provided by the embodiment of the present invention;

[0040] Figure 13 Schematic diagram of the output voltage standing wave ratio of the zero state and the delay state of the delay chip provided by the embodiment of the present invention. Detailed implementation manners

[0041] In order to enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are part of the embodiments of this solution, rather than all of the embodiments. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this solution.

[0042] The term "including" in the specification and claims of this solution and any other deformation thereof means "including but not limited to", and is intended to cover non-exclusive inclusion, and is not limited to the examples listed in the text. In addition, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order.

[0043] The implementation of the present invention will be described in detail below in conjunction with specific drawings:

[0044] Whether the antenna system can accurately locate and whether the main lobe of the beam can effectively suppress the side lobe depend on the accuracy index of the phase shifter. The phase shifter is a frequency-independent control device that will affect the instantaneous bandwidth of the antenna. Therefore, a delay device is considered to be used to replace it to obtain better performance.

[0045] High-performance antenna systems also pose different requirements for delay line circuits, such as bandwidth, miniaturization, stability, high precision, etc. in all aspects, making delay line chips a hot research topic at home and abroad. The volume of the delay line limits its application scope. The relatively small on-chip delay line (also known as the delay line chip) is widely used in miniaturized antenna systems and has the advantages of stable delay amount and strong anti-crosstalk ability.

[0046] In broadband phased array antennas, the pointing of the antenna scanning beam will drift with the change of the operating frequency due to the aperture effect, which will deteriorate the frequency response of the antenna to broadband signals and further restrict the instantaneous bandwidth of the phased array antenna. Therefore, the core technology that needs to be solved in antenna broadband imaging is how to eliminate the beam spatial pointing dispersion problem caused by broadband large aperture and large scanning angle during large-angle two-dimensional scanning of the antenna array surface and improve the beam pointing accuracy. To solve this problem, it is necessary to perform delay compensation on the received / transmitted signals of the phased array antenna. At the same time, higher requirements are also put forward for the delay accuracy.

[0047] A delay line is usually a commonly used microwave passive two-port device. Its main function is to delay an electromagnetic wave for a constant time during transmission between two ports to compensate for the phase difference caused by different frequencies. It has a wide range of applications in many fields, such as various antenna arrays. The delay line is mainly used to compensate for the beam spatial pointing dispersion caused by broadband large-angle scanning. When processing broadband and ultra-wideband array signals, the time delay difference between the received and transmitted signals of each antenna element must be compensated to a reasonable range. When the time delay difference between the received and transmitted signals of the large antenna array surface elements is large, a large-bit delay chip is required. Traditional large delay lines are implemented in the form of components. In actual project applications, with the increase in the requirement for the total delay, the volume, cost, and electrical loss of the delay line cannot be ignored.

[0048] Figure 1 It is the functional block diagram of the delay line provided by the embodiment of the present invention; referring to Figure 1 , the delay line can be composed of two groups of single-pole double-throw switches, a reference branch, and a delay network branch. The reference branch usually uses a T-type or π-type attenuation unit. The delay branch unit uses a constant-resistance network unit, as shown in Figure 1 . This delay topology requires the reference branch and the delay branch to use two groups of single-pole double-throw switches to work complementarily in the reference state and the delay state to achieve delay. The connected switching devices mainly improve the isolation degree of this topology. Among them, VN is the control level of the delay line, VP is the common-mode voltage, and VN is the differential-mode voltage; Rg is the isolation resistor externally connected to the gate of the HEMT switch (usually greater than 1.5 kΩ), which plays the role of isolating radio frequency signals.

[0049] Figure 2 It is the equivalent circuit diagram of the basic unit of the delay constant-resistance network provided by the embodiment of the present invention. The delay line can include multiple Figure 2The unit shown. When the delay amount of the delay chip is large, a large number of inductors and capacitors need to be cascaded to form an equivalent delay unit. When the delay amount is large (in the ns order of magnitude), the insertion loss of the delay network branch will increase with the increase of the delay unit, and the dispersion of the delay will be difficult to control with the increase of the unit. The greater the phase dispersion of the delay, the worse the delay accuracy.

[0050] The delay accuracy is also affected by the accuracy of the MIM capacitor located in the constant-resistance network. According to C = ε×ε0×S / d, it can be obtained that the parameters affecting the capacitance size are the capacitance area size and the dielectric capacitance thickness. Figure 3 Schematic diagram of the MIM capacitor structure provided by the embodiment of the present invention. Refer to Figure 3 , the MIM capacitor includes an upper electrode plate, a dielectric, and a lower electrode plate. Therefore, in the actual process wafer, the parameters affecting the capacitance accuracy are the metal sizes of the upper and lower electrode plates, the dielectric thickness, and the change of the dielectric constant. Therefore, the process parameters and processing accuracy must be strictly controlled to achieve high-precision capacitance indicators. For example, high-precision lithography technology is used to control the deviation of the metal sizes of the upper and lower electrode plates of the capacitor; the dielectric deposition silicon nitride technology is used to control the deviation of the silicon nitride dielectric thickness.

[0051] Figure 4 Schematic diagram of the non-adjustable single-wafer delay accuracy provided by the embodiment of the present invention. Even if the process is strictly controlled, refer to Figure 4 , when the delay amount reaches the ns level, the delay accuracy of the 450 chips of the actual processed single wafer is about ±16 ps, and the delay accuracy error is ±1.23%. If an ns-level, small-size, high-precision large-bit delay chip is required, higher requirements will be put forward for the process accuracy. Therefore, in practical applications, there is an urgent need for a high-precision ns-level delay chip structure.

[0052] Regarding the delay amount and the delay accuracy, it should be noted that with the increase of the delay amount, the length of the transmission line in the delay line increases, or the size of the capacitor / inductor increases, or the number of capacitors / inductors increases. In short, with the increase of the delay amount, the manufacturing error range also increases and the delay accuracy decreases.

[0053] The embodiment of the present invention can perform on-chip delay adjustment according to the difference in the measured delay amount after the chip is manufactured by setting a delay fine-tuning unit on the chip, so as to solve the problem that the existing on-chip delay line is limited by the processing technology accuracy and the delay accuracy is low.

[0054] Schematic diagram of the structure of an adjustable delay chip provided by an embodiment of the present invention. The chip includes: a delay branch, and a delay fine-tuning unit connected in series with the delay branch; the delay fine-tuning unit includes a plurality of transmission lines with different lengths; any one and only one of the transmission lines is used to be connected in series with the delay branch; wherein, before on-chip delay adjustment, the intermediate transmission line with the length closest to the average value among the transmission lines is connected in series with the delay branch; the delay fine-tuning unit is used to disconnect the intermediate transmission line and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch when the measured delay amount of the delay branch is greater than the target delay range; the delay fine-tuning unit is further used to disconnect the intermediate transmission line and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch when the measured delay amount of the delay branch is less than the target delay range.

[0055] In some embodiments, the delay branch is a branch circuit specifically used in the delay chip to increase the delay time of a signal.

[0056] Exemplarily, the working principle of the delay branch is often based on the charge and discharge characteristics of capacitors and inductors, or utilizes the transmission delay of logic gates.

[0057] When a signal passes through the delay branch, a time delay will be generated, making the output signal lag behind the input signal in time. Exemplarily, the chip further includes a reference branch. The reference branch is connected in parallel with the delay branch and can be switched by a switch to allow the signal to pass through the reference branch or through the delay branch. Correspondingly, when the signal passes through the delay branch, it generates a time delay relative to passing through the reference branch.

[0058] In some embodiments, the delay branch is a constant-resistance delay network.

[0059] In some embodiments, the delay fine-tuning unit is connected in series with the delay branch and is used to adjust and compensate for the delay error of the delay branch. It should be noted that the delay error here is caused by manufacturing errors and is the difference between the target delay amount and the measured delay amount. The target delay amount here is the design value, which is the delay amount that the delay chip needs to achieve in the delay state. Generally, due to manufacturing errors, there will also be errors in the delay amount of the actually prepared delay chip. Moreover, for delay chips with a large delay amount, the delay amount error is larger, so that the delay amount error exceeds the required range. The structure of the delay fine-tuning unit is described in detail below.

[0060] In some embodiments, the delay fine-tuning unit includes a plurality of transmission lines with different lengths; any one and only one of the transmission lines is used to be connected in series with the delay branch; wherein, before on-chip delay adjustment, the intermediate transmission line with the length closest to the average value among the transmission lines is connected in series with the delay branch;

[0061] The length differences of the transmission lines result in different signal transmission times therein, which is the basis for realizing the delay fine-tuning function. The delay fine-tuning unit includes multiple transmission lines with different lengths, whereby different delays can be achieved. Among these multiple transmission lines with different lengths, only one transmission line is selected each time to be connected in series with the delay branch.

[0062] Before performing the on-chip delay adjustment operation, there is a default transmission line selection rule, that is, from these multiple transmission lines with different lengths, select the transmission line whose length is closest to the average length of all transmission lines and is in the middle position (if all transmission lines are sorted by length, it is in the middle position), and connect it in series with the delay branch. This is to provide a relatively moderate delay effect for the circuit in the initial state as the starting point for subsequent fine adjustment.

[0063] Regarding the state before the on-chip delay adjustment operation, it should be noted that the delay branch and the delay fine-tuning unit are simultaneously fabricated on the chip based on the chip process, and during the fabrication process, the middle transmission line is connected in series with the delay branch based on the chip process. That is, the fabricated chip already has a complete delay function. If precise adjustment of the delay error is required, then further fine-tuning is performed. The following describes the adjustment method of the delay fine-tuning unit.

[0064] In some embodiments, the delay fine-tuning unit is configured to, when the measured delay of the delay branch is greater than the target delay range, disconnect the middle transmission line and select a transmission line shorter than the middle transmission line to be connected in series with the delay branch;

[0065] Exemplarily, the delay is fine-tuned and reduced based on the length difference of the transmission lines before and after adjustment.

[0066] The trigger condition for adjustment is: after actually measuring the delay amount, when the delay amount generated by the current delay branch (including the middle transmission line) exceeds the upper limit of the target delay range required by the system, the adjustment mechanism is triggered.

[0067] The specific adjustment strategy is: first disconnect the middle-length transmission line connected in series with the delay branch in the default state. Select a shorter transmission line and select a transmission line with a length less than the middle transmission line from the remaining transmission lines to be re-connected in series with the delay branch.

[0068] The adjustment principle is: the time for a signal to propagate in a transmission line is proportional to its physical length, and a shorter transmission line generates less delay. By shortening the transmission line length, the total delay amount is reduced, so that the measured delay amount returns to the target range.

[0069] In some embodiments, the delay fine-tuning unit is further configured to, when the measured delay of the delay branch is less than the target delay range, disconnect the middle transmission line and select a transmission line longer than the middle transmission line to be connected in series with the delay branch.

[0070] Exemplarily, the delay is finely adjusted by increasing the delay based on the length difference between the transmission lines before and after adjustment.

[0071] The embodiments of the present invention illustrate the dynamic adjustment logic of the delay fine-tuning unit under another working condition. The core is to compensate for the problem of insufficient delay by switching to a longer transmission line. Specifically, when the total delay of the delay branch measured actually (including the intermediate transmission line) is lower than the lower limit of the target range required by the system, the adjustment mechanism is triggered. First, the initially default intermediate-length transmission line is cut off, and a transmission line with a length greater than that of the intermediate transmission line is selected from the remaining transmission lines and re-connected in series with the delay branch. The longer transmission line will introduce a greater delay. By increasing the length of the transmission line, the total delay amount is increased, so that the measured value returns to the target range.

[0072] In some embodiments, the delay fine-tuning unit is further configured to keep the intermediate transmission line connected in series with the delay branch when the actually measured delay amount of the delay branch does not exceed the target delay range.

[0073] In the embodiments of the present invention, when the actually measured delay amount of the delay branch does not exceed the target delay range, the delay amount of the delay branch already meets the design requirements at this time, and no adjustment is required. Keeping the series connection state can ensure the normal transmission of signals and avoid errors caused by unnecessary adjustments.

[0074] It should be noted that the delay amount of any transmission line is less than that of the delay branch. For example, the delay amount of the delay branch can be in the order of nanoseconds, and the delay amount of any transmission line is in the order of picoseconds. Due to the small delay amount, only comparing from the length aspect, the length of any transmission line is relatively small, and the error range of the delay amount after manufacturing is also small. Since the manufacturing process level remains unchanged, setting a shorter transmission line will also be limited by manufacturing errors. Compared with the lengths of the transmission lines, the length differences between different transmission lines are relatively small, which can be achieved with the existing processing technology level. Further, based on the length differences between different transmission lines, the embodiments of the present invention use these small differences as the adjustment amount to finely adjust the delay amount of the delay branch, thereby realizing the fine adjustment of the delay amount. Even though a single transmission line is affected by manufacturing errors, the relatively stable length difference between different transmission lines can ensure that when different transmission lines are combined and connected in series with the delay branch, the resulting change in the delay amount is predictable and controllable. This design ingeniously utilizes the linear relationship between the transmission line length and the delay amount, and under the limited manufacturing process conditions, meets the requirement of high-precision adjustment of the delay amount, greatly improving the adaptability and reliability of the delay fine-tuning unit in a complex circuit environment.

[0075] In the embodiment of the present invention, by providing a delay fine-tuning unit, after the chip manufacturing is completed, the delay can be adjusted on the chip according to the difference in the measured delay amount. The delay fine-tuning unit includes a plurality of transmission lines with different lengths, having a plurality of different delay amounts; based on the length difference of the transmission lines before and after adjustment, the delay can be fine-tuned and reduced by selecting a shorter transmission line, and the delay can be fine-tuned and increased by selecting a longer transmission line. Relative to the lengths of the respective transmission lines, the length differences between different transmission lines are small, and these small differences can be used as adjustment amounts at the existing processing technology level to fine-tune the delay amount of the delay branch. The error range of the fine-tuned delay amount is reduced, thereby improving the delay accuracy at the existing processing technology level.

[0076] The following describes the connection and disconnection methods of the transmission line and the delay branch.

[0077] In a possible implementation manner, the intermediate transmission line is connected in series with the delay branch through an air bridge; correspondingly, the intermediate transmission line is disconnected by disconnecting the air bridge; the transmission lines other than the intermediate transmission line are connected in series with the delay branch through wire bonding.

[0078] An air bridge is a structure used to achieve electrical connection between different metal layers in a circuit or to cross an isolation area. It is usually made of metal or other conductive materials, shaped like a "bridge", spanning above the area that needs to be connected or crossed, and the area below the "bridge" is air, hence the name air bridge.

[0079] An air bridge is a commonly used chip structure, and the intermediate transmission line can be connected in series with the delay branch through the air bridge during the chip manufacturing stage. Wire bonding is a process widely used during the chip packaging and testing process. When the chip manufacturing is completed and enters the packaging and testing stage, wire bonding can be used to more flexibly and conveniently adjust the connection between the intermediate transmission line and the delay branch.

[0080] In the embodiment of the present invention, on-chip adjustment of the delay can be achieved by means of air bridge cutting and wire bonding. Traditional delay adjustment may require complex circuit adjustments outside the chip, while the embodiment of this invention can directly perform delay adjustment inside the chip (on-chip), with higher integration and flexibility.

[0081] In a possible implementation manner, the delay amount of the delay branch is at the nanosecond level; the delay amount of the delay fine-tuning unit is at the picosecond level.

[0082] The nanosecond-level delay branch provides a large delay amount to meet the system's demand for large-bit delay. It is finely adjusted by the picosecond-level delay fine-tuning unit to further improve the delay accuracy and meet the requirements of high-precision applications. In the embodiment of the present invention, through the combination of nanosecond level and picosecond level, high-precision delay control can be achieved on the basis of large-range delay, ensuring the stability and reliability of the system under different working conditions. The embodiment of the present invention can provide an ns-level delay chip structure.

[0083] In a possible implementation manner, it further includes a delay coarse-tuning unit; the delay coarse-tuning unit is connected in series with the delay branch; the delay coarse-tuning unit includes a plurality of different delay amounts; the delay amount of any one of the delay coarse-tuning units is less than the delay amount of the delay branch, and the delay amount of any one of the delay coarse-tuning units is greater than the delay amount of the delay fine-tuning unit.

[0084] The delay branch provides the main delay amount, which can be in the nanosecond level. The delay coarse-tuning unit is used to adjust the delay amount within a large range to quickly approach the target delay amount, and its adjustment amount can be in the picosecond level. The delay fine-tuning unit is used to finely adjust the delay amount within a small range, and its adjustment amount can be in the picosecond level.

[0085] The delay coarse-tuning unit is connected in series with the delay branch, and the signal passes through the delay coarse-tuning unit and the delay branch in sequence. The delay amount of the delay coarse-tuning unit is superimposed on the delay amount of the delay branch to form the total delay amount.

[0086] In the embodiment of the present invention, by setting the delay coarse-tuning unit and connecting it in series with the delay branch, the delay amount can be quickly adjusted within a large range, and at the same time, fine adjustment is performed through the delay fine-tuning unit to improve the delay accuracy and adjustment efficiency. This design not only improves the performance of the delay device but also enhances the flexibility and adaptability of the system.

[0087] In a possible implementation manner, the delay coarse-tuning unit is used to adjust the delay amount of the delay coarse-tuning unit based on the size relationship between the measured delay amount of the delay branch and the target delay range, so that the delay chip outputs the target delay.

[0088] In a possible implementation manner, the delay coarse-tuning unit includes a plurality of delay units connected in series; any one of the delay units includes a delay line, a reference line, and two switching switches; the switching switches are used to switch the delay unit between the delay state and the reference state.

[0089] The following uses a comprehensive embodiment to illustrate the working mode of the delay coarse-tuning unit.

[0090] Figure 5 For the structural schematic diagram of the delay coarse-tuning unit provided by the embodiment of the present invention. Refer to Figure 5, which is a topological structure diagram of an adjustable 1.4 ns (1400 ps) delay chip. In some embodiments, the delay branch uses large-bit delay, for example, the delay amount is 1400 ps; the coarse delay adjustment unit uses two-bit delay, for example, two smaller delays, 8 ps bit and 16 ps. The 1400 ps bit, 8 ps bit, and 16 ps bit are cascaded to adjust the accuracy, as Figure 5 shown. Each bit of delay is controlled by two pairs of single-pole double-throw switches respectively. When the TTL level of the control switch is low, both switches are connected to the attenuation branch to achieve the reference zero state; when the TTL level of the control switch is high, both switches are connected to the delay branch to achieve the delay state.

[0091] The working truth table is shown in the following table. Among them, the two small bits of 8 ps bit and 16 ps bit are adjustable bits for the large delay measurement data being too large or too small. For a 3-bit digital control delay device, there are a total of 7 states, corresponding to 16 ports for input and output. Set the working states of the cascaded delay device according to the truth table to obtain the full-state delay curve. Then adjust the circuit according to the simulation results to improve the circuit indicators that do not meet the requirements, and perform the full-state circuit simulation again. Repeat the adjustment and simulation until the overall indicators of the circuit are met.

[0092] Table 1 Three-bit delay truth table

[0093]

[0094] The following uses a comprehensive embodiment to illustrate the delay fine-tuning unit. Figure 6 is a layout schematic diagram of the adjustable delay chip provided by the embodiment of the present invention; the green dashed box in the figure represents the delay branch, and the red dashed box represents the delay fine-tuning unit. Figure 7 is a structural schematic diagram of the delay fine-tuning unit provided by the embodiment of the present invention; Figure 7 corresponding to Figure 6 the part in the red dashed box in

[0095] In some embodiments, the target delay amount of the adjustable delay chip is 1.4 ns (1400 ps).

[0096] The delay error is finely adjusted by using the on-chip wire bonding method on the chip. For example, when the measured delay deviates from the 1400 ps ± 4 ps interval, neither bonding nor cutting the internal air bridge of the chip is required; when the measured delay is too large, bond the pressure point Pa to the pressure point Pc, and at the same time disconnect the air bridge directly between the pressure point Pa and the pressure point Pb; when the measured delay is too small, bond the pressure point Pa to the pressure point Pd, and at the same time disconnect the air bridge directly between the pressure point Pa and the pressure point Pb.

[0097] The delay accuracy adjustment method of the embodiment of the present invention is realized by bonding or cutting methods. For the specific bonding and cutting positions, reference can be made to Figure 7 .

[0098] If the delay device designed without adjustable results in the traditional way has a delay range of 1390 ps to 1410 ps for 450 chips on a single wafer. And the actual project requirement for the delay error needs to be as close as possible to 1400 ps. Based on the processing error of the delay itself, through the fine-tuning and coarse-tuning methods described above, the delay accuracy of the traditional delay device can be adjusted from ±4 ps to ±16 ps to within ±4 ps. As shown in the following table.

[0099]

[0100] The on-chip adjustable delay is mainly realized by bonding or cutting. When bonding on the chip, two gold wires are used for bonding, and the length should be as short as possible to avoid affecting the internal unit matching of the delay device circuit. When designing the chip Figure 7 The circled part is preferably manufactured by air bridge processing. Air bridge is an important circuit connection technology. A chip usually consists of multiple functional layers, including insulation layers, conductive layers, transistors, etc. These functions are directly realized through wires or metal bridges. The principle of the air bridge is to use air as the insulating medium to suspend the metal wire on the chip surface to achieve circuit connection. At the same time, since it is suspended on the chip surface, cutting is relatively easy, which is convenient for on-chip adjustment.

[0101] In some embodiments, based on the GaAs Phemt process, the present invention designs a 1.4 ns (1400 ps) numerically controlled delay device chip, and the schematic diagram is as Figure 6 shown. In an ideal state, when the external input control signal switches the delay state, the delay line should generate a very precise delay time. However, in reality, since the time delay in the delay line is realized by the path difference between the delay state and the ground state, during production and processing, due to the error of the board itself and the board processing, the greater the delay time, the more this error will be amplified, making it difficult to control the delay accuracy within a small range. Therefore, we designed a compact adjustment circuit. In this way, an adjustment circuit is loaded on each delay state, which is equivalent to having an adjustment range of ±12 ps for each delay state, further improving the delay accuracy. The present invention adopts a combination of coarse-tuning and fine-tuning methods to realize a high-precision ns-level delay device chip.

[0102] The present invention manufactures a delay chip by adopting an innovative large-bit numerically controlled delay structure. Figure 8 Schematic diagram of the insertion loss curve of the delay chip provided by the embodiment of the present invention; Figure 9 Schematic diagram of the amplitude fluctuation curve of each state of the delay chip provided by the embodiment of the present invention; Figure 10 Schematic diagram of the delay amount curve of the delay chip provided by the embodiment of the present invention; Figure 11Schematic diagram of the delay accuracy curve of the delay chip provided by the embodiment of the present invention;

[0103] Figure 12 Schematic diagram of the input voltage standing wave ratio of the zero state and the delay state of the delay chip provided by the embodiment of the present invention;

[0104] Figure 13 Schematic diagram of the output voltage standing wave ratio of the zero state and the delay state of the delay chip provided by the embodiment of the present invention. Figures 8 - 13 The test results show that in the range of 0.8 GHz - 6 GHz, the insertion loss is less than 11 dB, the insertion loss fluctuation is less than ±0.5 dB, the 1400 ps bit delay error can be adjusted to ±4 ps on-chip, the delay accuracy is as high as 3‰, and the input and output standing waves in the full state are both less than 1.5.

[0105] The circuit topology of the GaAs large-bit delay device of the present invention can be extended and applied to other semiconductor processes such as GaN. The large-bit delay device fabricated by the present invention has broad application prospects in the T / R delay components of modern antenna systems.

[0106] The present invention utilizes Figure 6 the circuit structure to design the circuit and determine the parameters of the components in the circuit. First, optimize the basic delay unit bit to obtain the optimal topology and lumped parameter values, and then convert the lumped parameters into distributed parameters. Cascade simulation is performed on the single-pole double-throw switch and the attenuation and equalization unit according to the results of the basic bit unit, and the zero state and the delay state of the delay chip are set according to the truth table. The amplitude difference between the delay state and the zero state gives the amplitude fluctuation curve of the delay, and the phase difference between the delay state and the zero state is converted into the delay amount, that is, the delay error curve of the delay is obtained. Adjust the circuit according to the simulation results to improve the circuit indexes that do not meet the requirements, and finally achieve the optimal indexes.

[0107] In the layout, the electromagnetic compatibility problem should be fully considered. In the design, add isolation belts formed by multiple groups of cascaded common ground vias to achieve electromagnetic space isolation and prevent signal crosstalk. At the same time, reduce the intersection of microwave transmission lines and DC transmission lines and add filter capacitors on the DC transmission lines to reduce the crosstalk coupling of external signals to the internal circuit. In the layout, first connect the RF transmission path, then connect the DC path, and finally make full use of the flexibility of the control end signal to layout the layout to realize the control of the attenuator, which significantly improves the layout efficiency.

[0108] Manufactured by using GaAs PHEMT microwave monolithic integrated circuit process technology. The main process of GaAs process includes: mesa isolation, ohmic contact, gate trenching and metallization, device passivation, metal stripping, air bridge preparation, backside chemical thinning, via process, etc. Before the process processing, it is necessary to provide the chip layout of the broadband delay chip as Figure 6 shown.

[0109] The chip is tested on - chip using a microwave probe platform, and the test results are as follows Figures 8 - 13 shown. In the range of 0.8 GHz - 6 GHz, the insertion loss is less than 11 dB, the insertion loss fluctuation is less than ±0.5 dB, the 1400 ps bit - delay error can be adjusted to ±4 ps on - chip, the delay accuracy is as high as 3‰, and the standing - wave ratios of all - state input and output are less than 1.5.

[0110] An embodiment of the present invention provides a delay device, including an on - chip adjustable delay chip in any of the above - mentioned possible implementation manners.

[0111] An embodiment of the present invention provides a method for adjusting the delay of an on - chip adjustable delay chip, which is applied to an on - chip adjustable delay chip in any of the above - mentioned possible implementation manners; the method includes:

[0112] Obtain the target delay range and the measured delay amount of the delay branch;

[0113] If the measured delay amount of the delay branch is greater than the target delay range, control to disconnect the intermediate transmission line, and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch;

[0114] If the measured delay amount of the delay branch is less than the target delay range, disconnect the intermediate transmission line, and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch.

[0115] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An on-chip adjustable delay chip, characterized in that, Comprising: A delay branch and a delay fine-tuning unit connected in series with the delay branch; The delay fine-tuning unit includes a plurality of transmission lines with different lengths; any one and only one of the transmission lines is used to be connected in series with the delay branch; wherein, before on-chip delay adjustment, the intermediate transmission line with the length closest to the average value among the transmission lines is connected in series with the delay branch; The delay fine-tuning unit is configured to, when the measured delay of the delay branch is greater than the target delay range, disconnect the intermediate transmission line and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch; The delay fine-tuning unit is further configured to, when the measured delay of the delay branch is less than the target delay range, disconnect the intermediate transmission line and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch.

2. The on-chip adjustable delay chip according to claim 1, wherein The intermediate transmission line is connected in series with the delay branch through an air bridge; correspondingly, the intermediate transmission line is disconnected by disconnecting the air bridge; The transmission lines other than the intermediate transmission line are connected in series with the delay branch through wire bonding.

3. The on-chip adjustable delay chip according to claim 1, characterized in that, The delay of the delay branch is at the nanosecond level; The delay of the delay fine-tuning unit is at the picosecond level.

4. The on-chip adjustable delay chip according to claim 1, wherein It further includes a delay coarse-tuning unit; the delay coarse-tuning unit is connected in series with the delay branch; The delay coarse-tuning unit includes a plurality of different delay amounts; The delay amount of any one of the delay coarse-tuning units is less than the delay amount of the delay branch, and the delay amount of any one of the delay coarse-tuning units is greater than the delay amount of the delay fine-tuning unit.

5. The on-chip adjustable delay chip according to claim 1, characterized in that The delay fine-tuning unit is further configured to, when the measured delay of the delay branch does not exceed the target delay range, keep the intermediate transmission line connected in series with the delay branch.

6. The on-chip adjustable delay chip according to claim 5, characterized in that The delay coarse-tuning unit is configured to adjust the delay amount of the delay coarse-tuning unit based on the magnitude relationship between the measured delay of the delay branch and the target delay range, so that the delay chip outputs the target delay.

7. The on-chip adjustable delay chip according to claim 5, characterized in that The delay coarse-tuning unit includes a plurality of delay units connected in series; Any one delay unit includes a delay line, a reference line and two switching switches; The switching switch is used to switch the delay unit between a delay state and a reference state.

8. The on-chip adjustable delay chip according to claim 1, characterized in that, The delay branch is a constant-resistance delay network.

9. A delay device, characterized in that, It includes an on-chip adjustable delay chip as described in any one of claims 1 to 8.

10. A method for adjusting the delay of an on-chip adjustable delay chip, characterized in that, Applied to an on-chip adjustable delay chip as described in any one of claims 1 to 8; the method includes: Obtaining the target delay range and the measured delay of the delay branch; If the measured delay of the delay branch is greater than the target delay range, then control to disconnect the intermediate transmission line and select a transmission line shorter than the intermediate transmission line to be connected in series with the delay branch; If the measured delay of the delay branch is less than the target delay range, then disconnect the intermediate transmission line and select a transmission line longer than the intermediate transmission line to be connected in series with the delay branch.

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