Chip based on reconfigurable neuromorphic interconnection architecture

Abstract

The invention discloses a chip based on a reconfigurable neuromorphic interconnection architecture, which comprises a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS (Complementary Metal Oxide Semiconductor) reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust a routing path through a dynamic routing algorithm. The dynamic routing algorithm has the advantages that the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, so that dynamic prediction of network congestion and dynamic adjustment of a routing path are carried out, meanwhile, the CMOS switch and the memristor switch are connected in parallel, limitation of a traditional single device or static interconnection is avoided, and the network congestion can be dynamically predicted. Not only are network performance and reliability improved, but also delay and power consumption of data transmission are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a chip based on a reconfigurable neuromorphic interconnection architecture. Background Art

[0002] With the rapid development of artificial intelligence technology, when the traditional von Neumann architecture processes computationally intensive tasks such as deep neural networks, due to the separation of the processor and the memory, it faces significant performance bottlenecks. Research shows that when running typical deep learning models, the power consumption ratio of data transfer can be as high as more than 50%, resulting in low system efficiency. Especially in the edge computing scenario, it is difficult to meet the requirement of controlling the power consumption below 1W. Neuromorphic computing attempts to break through the above limitations with low power consumption and high parallelism by learning from the human brain's information processing mechanism. However, existing neuromorphic chips mostly rely on a single interconnection topology or static switching units, facing problems such as limited bandwidth, high latency, and large power consumption, and lacking the combination of dynamic hierarchical communication and low-power high-speed switching, making it difficult to meet the stringent requirements of edge computing for real-time performance and energy efficiency. For example, in autonomous driving, the chip needs to complete complex perception and decision-making within milliseconds, but the efficiency of existing solutions often drops sharply when the scale of neurons expands. Existing hierarchical interconnections are mostly static topologies, and the application of memristors is limited to the storage field, neither of which is optimized for the pulse communication requirements of neuromorphic computing, nor is there a specific method of parallel connecting memristors and CMOS for neuromorphic interconnection. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a chip based on a reconfigurable neuromorphic interconnection architecture.

[0004] The purpose of the present invention is achieved through the following technical solutions: A chip based on a reconfigurable neuromorphic interconnection architecture includes a hierarchical dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit. The hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust the routing path through a dynamic routing algorithm;

[0005] The hierarchical dynamic reconfigurable interconnection network layer is used for each computing unit in the chip to dynamically communicate and cooperate;

[0006] The memristor-CMOS reconfigurable interconnection unit consists of a memristor switch, a CMOS switch, and a control circuit. The memristor switch controls whether current passes through by changing the resistance state to dynamically adjust the interconnection path. The CMOS switch is connected in parallel with the memristor switch, and the control circuit is used to control the on / off of the memristor switch and the CMOS switch.

[0007] Preferably, the hierarchical dynamic reconfigurable interconnection network layer has a three-layer architecture, namely an intra-neuron cluster interconnection layer, an inter-cluster interconnection layer, and a global reconfigurable interconnection layer;

[0008] The intra-cluster interconnection layer is the lowest layer, which is used for the interconnection within the neuron cluster;

[0009] The inter-cluster interconnection layer is the middle layer, which is used for the interconnection between different neuron clusters to establish communication paths;

[0010] The globally reconfigurable interconnection layer is the topmost layer, which is used for the global interconnection of the entire chip to provide communication paths across regions.

[0011] Preferably, the specific steps for dynamically adjusting the routing path based on the dynamic routing algorithm are as follows:

[0012] S1: Initialize all nodes and links, and set the initial routing table and congestion detection threshold;

[0013] S2: Collect real-time traffic data and link status information through sensors and monitoring points, and perform data cleaning and preprocessing;

[0014] S3: Analyze the data to predict the congested links that will appear in the future time period;

[0015] S4: According to the congestion prediction result, use the shortest path algorithm to select the optimal path,

[0016] dist[v] = min(dist[v], dist[u] + weight(u, v));

[0017] where dist[v] is the shortest distance from the source node to node v, and weight(u, v) is the link weight from node u to node v;

[0018] S5: Use the adaptive routing algorithm to dynamically adjust the routing path according to the current load of the link,

[0019] new_path = argpathminlink∈path∑load(link);

[0020] where load(link) is the current load of the link;

[0021] S6: When the network reaches a stable state and the loads of all links are within the set range, output the final routing configuration, otherwise return to step S2 and continue to execute.

[0022] Preferably, in step S3, a bidirectional gated recurrent network is used for long sequence prediction,

[0023] htf = GRU(Xt, ht-1f) htb = GRU(Xt, ht+1b) ht = htf + htb;

[0024] Among them, htf is the implicit information of forward propagation, htb is the implicit information of backward propagation, and ht is the final implicit state.

[0025] The present invention has the following advantages: By combining with the hierarchical dynamic reconfigurable Internet layer and the memristor-CMOS reconfigurable interconnection unit, the dynamic routing algorithm of the present invention can perform dynamic prediction of network congestion and dynamic adjustment of routing paths. At the same time, the CMOS switch is connected in parallel with the memristor switch to avoid the limitations of traditional single devices or static interconnections, which not only improves the network performance and reliability, but also reduces the latency and power consumption of data transmission. Brief Description of the Drawings

[0026] Figure 1 It is a schematic diagram of the three-layer topology structure of the hierarchical dynamic reconfigurable Internet layer;

[0027] Figure 2 It is a schematic diagram of the circuit principle of the memristor-CMOS reconfigurable interconnection unit;

[0028] Figure 3 It is a schematic diagram of the memristor material structure;

[0029] Figure 4 It is a schematic diagram of the timing of the memristor-CMOS reconfigurable interconnection unit. Detailed Embodiments

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0032] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0034] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, the terms "first", "second", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0035] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, the terms "arrange", "install", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0036] In this embodiment, as Figure 1 , Figure 2 and Figure 4 shown, a chip based on a reconfigurable neuromorphic interconnection architecture includes a hierarchical dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit. The hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust the routing path through a dynamic routing algorithm;

[0037] The hierarchical dynamic reconfigurable interconnection network layer is used for the computing units in the chip to dynamically communicate and cooperate;

[0038] The memristor-CMOS reconfigurable interconnection unit consists of a memristor switch, a CMOS switch, and a control circuit. The memristor switch controls whether current passes through by changing its resistance state, dynamically adjusting the interconnection path. The CMOS switch is connected in parallel with the memristor switch, and a 5nm SiO2 isolation layer and a 10nm porous SiO2 layer are added. The porosity of the SiO2 layer is 20%, thereby reducing capacitive coupling interference and local thermal diffusion. The control circuit is used to control the on / off states of the memristor switch and the CMOS switch. Specifically, the memristor switch controls the passage of current through the change of its resistance state, thereby realizing the dynamic adjustment of the interconnection path and logical operations; the CMOS switch is connected in parallel with the memristor switch, providing additional reliability guarantee. When the memristor switch fails or a backup path is needed, the CMOS switch can be used as a backup path to ensure the reliability of the interconnection, thus avoiding the limitations of traditional single devices or static interconnections. Preferably, as Figure 3 shown, the memristor switch is a TiO2 memristor, with a gray matrix TiN, a black matrix TiO2, and a gray matrix TiN stacked. The control circuit optimizes the working states of the memristor switch and the CMOS switch through dual-mode control, achieving the co-optimization of ultra-low power consumption and high-speed switching, that is, the static power consumption is lower than 0.05 μW, the dynamic switching frequency reaches 2 GHz, and the unit area is less than 0.3 μm 2 , as Figure 4 shown, the X-axis is time and the Y-axis is amplitude. The PROG(1.5V, 100ns) and EN(0V / 1.2V, 2GHz) waveforms are plotted. The static mode PROG triggers low resistance, and the dynamic mode EN switches at high frequency. The dynamic routing algorithm combines with the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit to dynamically predict network congestion and dynamically adjust the routing path. At the same time, the CMOS switch is connected in parallel with the memristor switch to avoid the limitations of traditional single devices or static interconnections, not only improving the network performance and reliability, but also reducing the delay and power consumption of data transmission. In this embodiment, the hierarchical dynamic reconfigurable interconnection network layer is used to provide a macroscopic interconnection framework, the memristor-CMOS reconfigurable interconnection unit is used to provide a microscopic interconnection framework, the dynamic routing algorithm avoids network congestion by dynamically adjusting the routing path, and the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit provide the hardware foundation and interconnection architecture for realizing this dynamic adjustment. Among them, the hierarchical dynamic reconfigurable interconnection network layer provides a hierarchical interconnection architecture, supports dynamic reconfiguration, and provides a communication path for the routing adjustment of the dynamic routing algorithm. The memristor-CMOS reconfigurable interconnection unit, as the basic building block of the hierarchical dynamic reconfigurable interconnection network layer, provides efficient interconnection and logical operation functions.

[0039] In this embodiment, the hierarchical dynamic reconfigurable interconnection network layer has a three-layer architecture, namely the intra-neuron cluster interconnection layer, the inter-cluster interconnection layer, and the global reconfigurable interconnection layer;

[0040] The intra-cluster interconnection layer is the lowest layer, which is used for the interconnection within the neuron cluster;

[0041] The inter-cluster interconnection layer is the middle layer, which is used for the interconnection between different neuron clusters to establish a communication path;

[0042] The globally reconfigurable interconnection layer is the topmost layer, which is used for the global interconnection of the entire chip to provide a communication path across regions. Specifically, the intra-cluster interconnection layer is responsible for the interconnection within the neuron cluster to ensure that neurons within the same cluster can communicate and exchange data quickly and efficiently. The inter-cluster interconnection layer is used for the interconnection between different neuron clusters to establish a communication path, enabling neurons in different clusters to work together to support complex neural network structures, that is, through path planning and load balancing strategies, to ensure the efficient utilization of communication paths and avoid communication bottlenecks; the globally reconfigurable interconnection layer is used for the global interconnection of the entire chip to provide a communication path across regions to support the communication requirements of large-scale neural networks. The globally reconfigurable interconnection layer also supports dynamic routing strategies and can dynamically adjust communication paths according to real-time communication requirements and network status to optimize communication efficiency. In this embodiment, the intra-cluster interconnection layer is a 16x16 crossbar switch matrix, the inter-cluster interconnection layer is a 64x64 mesh topology, and the globally reconfigurable interconnection layer is an 8x8 NoC with a bandwidth of 200 Mbps / channel.

[0043] In this embodiment, the specific steps for dynamically adjusting the routing path based on the dynamic routing algorithm are as follows:

[0044] S1: Initialize all nodes and links, and set the initial routing table and congestion detection threshold;

[0045] S2: Collect real-time traffic data and link status information through sensors and monitoring points, and perform data cleaning and preprocessing; specifically, the main function of data cleaning and preprocessing is to remove noise and outliers.

[0046] S3: Analyze the data to predict congested links in the future time period; further, use a bidirectional gated recurrent network for long sequence prediction,

[0047] htf = GRU(Xt, ht-1f) htb = GRU(Xt, ht+1b) ht = htf + htb;

[0048] where htf is the hidden information of forward propagation, htb is the hidden information of backward propagation, and ht is the final hidden state.

[0049] S4: According to the congestion prediction result, use the shortest path algorithm to select the optimal path,

[0050] dist[v] = min(dist[v], dist[u] + weight(u, v));

[0051] where dist[v] is the shortest distance from the source node to node v, and weight(u, v) is the link weight from node u to node v;

[0052] S5: Use the adaptive routing algorithm to dynamically adjust the routing path according to the current load of the link,

[0053] new_path = argpathminlink∈path∑load(link);

[0054] where load(link) is the current load of the link;

[0055] S6: When the network reaches a stable state and the loads of all links are within the set range, output the final routing configuration; otherwise, return to step S2 and continue execution. Specifically, the dynamic routing algorithm combines with the hierarchical dynamic reconfigurable Internet layer and the memristor-CMOS reconfigurable interconnection unit to achieve dynamic prediction of network congestion and adaptive adjustment of the routing path, which not only improves the reliability of the network but also significantly reduces the latency and power consumption of data transmission. Through the above algorithm steps, the dynamic routing algorithm can effectively avoid congestion in a complex network environment and ensure efficient data transmission.

[0056] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip based on a reconfigurable neuromorphic interconnection architecture, characterized in that: It includes a hierarchical dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit. The hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust the routing path through a dynamic routing algorithm. The hierarchical dynamic reconfigurable interconnection network layer is used for the computing units in the chip to dynamically communicate and cooperate. The memristor-CMOS reconfigurable interconnection unit consists of a memristor switch, a CMOS switch, and a control circuit. The memristor switch controls whether the current passes through by changing the resistance state to dynamically adjust the interconnection path. The CMOS switch is connected in parallel with the memristor switch, and the control circuit is used to control the on / off of the memristor switch and the CMOS switch.

2. The chip based on the reconfigurable neuromorphic interconnection architecture according to claim 1, characterized in that: The hierarchical dynamic reconfigurable interconnection network layer has a three-layer architecture, namely the intra-neuron cluster interconnection layer, the inter-cluster interconnection layer, and the global reconfigurable interconnection layer. The intra-neuron cluster interconnection layer is the lowest layer and is used for the interconnection within the neuron cluster. The inter-cluster interconnection layer is the middle layer and is used for the interconnection between different neuron clusters to establish communication paths. The global reconfigurable interconnection layer is the top layer and is used for the global interconnection of the entire chip to provide cross-region communication paths.

3. The chip based on the reconfigurable neuromorphic interconnection architecture according to claim 2, wherein: The specific steps for dynamically adjusting the routing path based on the dynamic routing algorithm are as follows: S1: Initialize all nodes and links, and set the initial routing table and congestion detection threshold. S2: Collect real-time traffic data and link status information through sensors and monitoring points, and perform data cleaning and preprocessing. S3: Analyze the data to predict the congested links that will appear in the future time period. S4: According to the congestion prediction result, use the shortest path algorithm to select the optimal path, dist[v] = min(dist[v], dist[u] + weight(u, v)); where dist[v] is the shortest distance from the source node to node v, and weight(u, v) is the link weight from node u to node v. S5: Use the adaptive routing algorithm to dynamically adjust the routing path according to the current load of the link, new_path = argpathminlink∈path∑load(link); where load(link) is the current load of the link. S6: When the network reaches a stable state and the load of all links is within the set range, output the final routing configuration, otherwise return to step S2 to continue execution.

4. The chip based on the reconfigurable neuromorphic interconnection architecture according to claim 3, characterized in that: In step S3, a bidirectional gated recurrent unit is used for long sequence prediction, htf = GRU(Xt, ht-1f) htb = GRU(Xt, ht+1b) ht = htf + htb; where htf is the hidden information of forward propagation, htb is the hidden information of backward propagation, and ht is the final hidden state.

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