Back pressure testing method, electronic device and storage medium based on IP verification

Abstract

The present invention relates to the field of chip design technology, and in particular to a back pressure test method, electronic device and storage medium based on IP verification, which uses the i-th interface to be tested inf of the IP module to test the back pressure test method. i Output multiple test instructions; add each test instruction to the design verification terminal DV inf i First queue vFIFO i ;DV takes out vFIFO i The test instructions in inf i Bus Functional Model BFM i The second queue bFIFO i ;BFM i Remove bFIFO i For the first test instruction with the back pressure test flag, the response data is returned after t3, and the vFIFO is back pressured. i ; For instructions other than the first one carrying the back pressure test flag, t2 i Then return the response data and press vFIFO again i , and so on, continuously pressing the vFIFO i , while reducing the back pressure vFIFO i time and the time of the entire simulation cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a back pressure testing method based on IP verification, an electronic device and a storage medium. Background Art

[0002] In IP-level verification, backstress testing is a critical step in ensuring design reliability and stability. Its core role is to thoroughly verify a design's various corner cases. In these complex scenarios, to induce backstress, the design must output a large amount of data to fill the design's first-in, first-out queue (FIFO). This process significantly increases backstress testing simulation time.

[0003] Specifically, for any interface from interface 1 to interface n, the average time per output is t1, the average time the bus functional model (BFM) takes to respond to each input is t2, and the designed queue (FIFO) depth is n. By derivation, the simulation time for backpressure on the FIFO is t2 × t1 × n / (t2 - t1), where t2 > t1. This formula clearly shows that the closer t2 approaches t1, the longer the backpressure time required. Therefore, from the perspective of backpressure testing itself, it is desirable to maximize t2. However, increasing t2 introduces a new problem: the simulation time (t2 × M) required to process M operations throughout the simulation cycle will significantly increase.

[0004] Currently, in the back-pressure test of IP-level verification, how to meet the back-pressure test's requirements for time parameters and ensure comprehensive test coverage while reasonably controlling the overall simulation time to avoid low verification efficiency due to excessive simulation time is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention adopts a technical solution: a back pressure testing method based on IP verification, which includes the following steps:

[0006] Get the i-th interface to be tested inf of the IP module i , the inf i Output multiple test instructions, the average time to output each test instruction is t1 i , the value of i ranges from 1 to N, where N is the number of interfaces of the IP module.

[0007] Get the inf in the design verification end DV i First queue vFIFO i , the vFIFO i Initialized to empty; wherein, the vFIFO i The depth is n.

[0008] Inf iEach test instruction output is added to the vFIFO i , wherein the test instruction is bound to the back pressure test identifier; the DV takes out the vFIFO i The test instructions in and store them in inf i Bus Functional Model BFM i The second queue bFIFO i ; The BFM i Remove bFIFO i The test instructions in are processed and returned, where: i From bFIFO i When the test instruction taken out is the first instruction carrying the back pressure test mark, and after the preset time interval t3, the vFIFO i fills up, the vFIFO i Being back-pressed, the IP module's inf i Pause sending the test instruction; and return the response data of the test instruction to the IP module, and the test instruction is processed; wherein, the t3 satisfies: t3≥t1 i ×n. When BFM i From bFIFO i When the test instruction taken out is not the first instruction with the back pressure test identifier, after the preset time interval t2 i After that, the vFIFO i fills up, the vFIFO i The IP module is inf i Pause sending test instructions; and return the response data of the test instructions to the IP module, and the test instructions are processed; wherein, t2 i ≥t1 i ×K, K is the multiple of the clock cycle in IP, j ranges from 1 to M, and M is the number of test instructions.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects:

[0012] The present invention provides a back pressure test method, electronic device and storage medium based on IP verification, which configures a back pressure test identifier in the test instruction, returns response data after t3 for the first instruction carrying the back pressure test identifier, and back pressures the vFIFO. i ; For instructions other than the first one carrying the back pressure test flag, t2 i Then return the response data and press vFIFO again i , and so on, continuously pressing the vFIFO i , achieving the purpose of back pressure test. The present invention can not only achieve the purpose of back pressure test, but also reduce the back pressure vFIFO i time and the time of the entire simulation cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a back pressure testing method based on IP verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0017] See also Figure 1 , which shows a flow chart of a back pressure testing method based on IP verification, the method includes the following steps:

[0018] S100, obtain the i-th interface to be tested inf of the IP module i , the inf i Output multiple test instructions, the average time to output each test instruction is t1 i , the value of i ranges from 1 to N, where N is the number of interfaces of the IP module.

[0019] IP verification refers to the functional verification of an independent intellectual property (IP) module in chip design to ensure that it meets design requirements. It is mainly used to verify the behavior of IP in different scenarios, including extreme cases (corner scenarios).

[0020] Among them, backpressure testing is a method that tests the robustness of upstream modules by simulating backpressure scenarios, that is, scenarios where downstream modules cannot receive data in a timely manner. It is used to ensure that the FIFO in the design can correctly handle data congestion when it is fully loaded.

[0021] Among them, inf i The input / output port of the IP module is responsible for exchanging data with external systems or other modules. For example, the TX interface of an Ethernet controller is responsible for sending data packets, and the RX interface is responsible for receiving data packets.

[0022] S200, obtain the inf in the design verification end DV i First queue vFIFO i , the vFIFO i Initialized to empty; wherein, the vFIFO i The depth is n.

[0023] Among them, vFIFO i It is a buffer queue. When the depth is n, it means storing n data.

[0024] S300, inf i Each test instruction output is added to the vFIFO i , wherein the test instruction is bound to the back pressure test identifier; the DV takes out the vFIFO i The test instructions in and store them in inf i Bus Functional Model BFM i The second queue bFIFO i ; The BFM i Remove bFIFO i The test instructions in are processed and returned.

[0025] Among them, each interface to be tested corresponds to a bus functional model (Bus Functional Model, BFM), that is, inf i Has its own bus functional model BFM i , the bus function models between each interface are independent of each other.

[0026] The bus functional model (BFM) is used in the verification environment to simulate interactions with IP interfaces. In backpressure testing scenarios, the IP's output interface must continuously send data until the downstream module can no longer receive it. This triggers backpressure when the FIFO fills up. In this scenario, the BFM simulates the downstream module's receiving behavior. The BFM can adjust the response time to the IP's output data to simulate the processing speed of the downstream module.

[0027] The interface simulates the actual data input / output behavior through the bus function model, for example, i BFM i Every t1 i Send a data entry and adjust the response time based on test requirements.

[0028] Among them, the bus function model BFM i Simulate inf i Data behavior, such as every t1 i When the downstream FIFO is full, the downstream module sends a back pressure signal to inf i , preventing BFM i Continue sending data.

[0029] Wherein, the BFM i Remove bFIFO i The steps for processing and returning the test instruction in include:

[0030] S310, when BFM i From bFIFO i When the test instruction taken out is the first instruction carrying the back pressure test flag, and after the preset time interval t3, the vFIFO i fills up, the vFIFO i Being back-pressed, the IP module's inf i Pause sending the test instruction; and return the response data of the test instruction to the IP module, and the test instruction is processed; wherein, the t3 satisfies: t3≥t1 i ×n.

[0031] In one embodiment, the vFIFO i The full judgment step includes: the IP module detects the vFIFO in real time i When the flag is a full flag or the status register is full, it is determined that the vFIFO i This method can prevent the vFIFO from filling up. i When the memory is full and cannot store data, data loss occurs.

[0032] It should be noted that due to inf i Every t1 i The time to send a test instruction, and vFIFO i The depth is n, so fill up the vFIFO i The minimum time required is t1 i ×n; BFM only works after the current test instruction is processed i The next instruction will be processed. Since no response data is returned to the RTL within t3, the vFIFO will not be processed again within t3. i Other instructions in, and t3 ≥ t1 i × n, so after t3 time vFIFO i Be filled.

[0033] S320, when BFM i From bFIFO i When the test instruction taken out is not the first instruction with the back pressure test identifier, after the preset time interval t2 i After that, the vFIFO i fills up, the vFIFO i The IP module is inf i Pause sending test instructions; and return the response data of the test instructions to the IP module, and the test instructions are processed; wherein, t2 i ≥t1 i ×K, K is the multiple of the clock cycle in IP, j ranges from 1 to M, and M is the number of test instructions.

[0034] It should be noted that since the first instruction carrying the back pressure test flag has already set the vFIFO i After the first instruction is processed, BFM i The next test instruction will be processed. If the next test instruction also carries the back pressure test flag, the vFIFO will be i You can also receive inf i A test command sent, inf i The time to send the test command is t1 i , the response time of the next test instruction is t2 i Satisfy t2 i ≥t1 i ×K, it can make vFIFO i Fill it up again, that is, press it back again. And so on, t3 and t2 i The configuration enables vFIFO i During verification, the corresponding interface can be continuously back-pressured, which means that the back-pressure scenario can be fully verified.

[0035] Among them, for the first test instruction carrying the back pressure test flag, BFM i If no response is returned within t3, back pressure is triggered. After t3, for test instructions other than the first one carrying the back pressure test flag, the response time is adjusted to t2. i , and t2 i T1 i K clock cycles, so even for the test instructions that are not the first to carry the back pressure test flag, the design can be continuously back pressured for verification. In the prior art, the back pressure test is performed by the average response time t2, and the time for back pressure FIFO is t2×t1 i ×n / (t2-t1 i ), where t2 is greater than t1 i In the present invention, t1 i ×n time counter pressure design, t1 i ×n is less than the back pressure time t2×t1 in the prior art i ×n / (t2-t1 i ).

[0036] The value of K is an integer multiple of the clock period.

[0037] Among them, the overall simulation time t satisfies: t=t1 i ×n+t2 i ×M.

[0038] In one embodiment, the value of K is 1. When the value of K is set to 1, the response time is exactly equal to the sending time, which can minimize the simulation time.

[0039] In one embodiment, when BFM i From bFIFO i When a test instruction retrieved from the program does not carry a back-pressure test identifier, the response data of the test instruction is returned to the IP module after the time interval originally bound to the test instruction has passed. It should be noted that a test instruction without a back-pressure test identifier is not used to test back-pressure testing, and therefore the response data can be returned according to the time interval originally bound.

[0040] In one embodiment, after the response data of the test instruction is returned to the IP module, the bFIFO is removed. i It should be noted that, remove the bFIFO i The test instruction in indicates that the current test instruction has been processed and the next test instruction can be executed.

[0041] In one embodiment, S310 further includes determining the BFMi From bFIFO i Steps to check whether the test instructions taken out carry the back pressure test flag: BFM i From bFIFO i The test instruction is extracted from the program, parsed, and the flag of the test instruction is checked during the parsing process. The flag value is used to determine whether the back pressure test flag is carried. As an example, when the flag is 1, it is a back pressure test flag, and when the flag is 0, it is a normal instruction flag. It should be noted that the purpose of parsing is to convert the test instruction into a signal that can be understood by the RTL.

[0042] In summary, the present invention provides a back pressure test method based on IP verification, which configures a back pressure test flag in the test instruction, returns response data after t3 for the first instruction carrying the back pressure test flag, and back pressures the vFIFO. i ; For instructions other than the first one carrying the back pressure test flag, t2 i Then return the response data and press vFIFO again i , continuously back pressure vFIFO i , achieving the purpose of back pressure test. The present invention can not only achieve the purpose of back pressure test, but also reduce the back pressure vFIFO i time and the time of the entire simulation cycle.

[0043] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0044] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0045] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0046] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0047] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A back pressure testing method based on IP verification, characterized in that: The method comprises: Get the i-th tested interface inf of the IP module i , the inf i Output multiple test instructions, the average time to output each test instruction is t1 i , 1≤i≤N, N is the number of interfaces of the IP module; Get the inf in the design verification end DV i First queue vFIFO i , the vFIFO i Initialized to empty; wherein, the vFIFO i The depth is n; Inf i Each test instruction output is added to the vFIFO i , wherein the test instruction is bound to the back pressure test identifier; the DV takes out the vFIFO i The test instructions in inf i Bus Functional Model BFM i The second queue bFIFO i ; The BFM i Remove bFIFO i The test instructions in are processed and returned, where: When BFM i From bFIFO i When the test instruction taken out is the first instruction carrying the back pressure test mark, and after the preset time interval t3, the vFIFO i fills up, the vFIFO i The IP module is inf i Pause sending the test instruction; and return the response data of the test instruction to the IP module, and the test instruction is processed; wherein, the t3 satisfies: t3≥t1 i ×n; When BFM i From bFIFO i When the test instruction taken out is not the first instruction with the back pressure test identifier, after the preset time interval t2 i After that, the vFIFO i fills up, the vFIFO i The IP module is inf i Pause sending test instructions; and return the response data of the test instructions to the IP module, and the test instructions are processed; wherein, t2 i ≥t1 i ×K, K is the multiple of the clock cycle in IP, 1≤j≤M, M is the number of test instructions.

2. The method according to claim 1, characterized in that The value of K is 1.

3. The method according to claim 1, characterized in that When BFM i From bFIFO i When the test instruction taken out does not carry the back pressure test identifier, the response data of the test instruction is returned to the IP module after the time interval originally bound to the test instruction.

4. The method according to claim 1, wherein After the response data of the test instruction is returned to the IP module, the bFIFO is removed. i The test instructions in .

5. The method according to claim 1, wherein The vFIFO i The full judgment step includes: the IP module detects the vFIFO in real time i When the flag is a full flag or the status register is full, it is determined that the vFIFO i Fill.

6. The method according to claim 1, characterized in that The method further includes determining BFM i From bFIFO i Steps to check whether the test instructions taken out carry the back pressure test flag: BFM i From bFIFO i The test instruction is taken out and parsed. During the parsing process, a flag of the test instruction is checked, and whether a back pressure test identifier is carried is determined according to the value of the flag.

7. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 7.

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