Mixed signal operational circuit

Abstract

The invention discloses a mixed signal operational circuit, which belongs to the technical field of integrated circuits, and is characterized in that for an operational circuit part, a first capacitor is used for determining the output end of a logic operational circuit, and a second capacitor is used for providing a certain voltage; the logical operation path gates a charge path from the second capacitor to the first capacitor based on each input data signal so as to superpose a voltage value at the output end; time division multiplexing is realized in a step-by-step injection mode, so that an analog voltage value related to a logical operation result is established at an output end, logical operation is realized only by adopting two capacitors, unit weight capacitor arrays with the same size as the logical operation number do not need to be constructed, the capacitor area overhead is greatly reduced, and the cost is reduced. While the working speed and precision are ensured, the area overhead of the operational circuit is reduced, and the operational energy efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, relates to a mixed-signal arithmetic circuit. Background Art

[0002] In application scenarios such as face detection in edge computing, wearable / implantable health detection, intelligent sensors, and intelligent Internet of Things, limited by the limited resources of mobile devices, the problem of high energy consumption overhead of traditional digital-domain operation-based embedded Graphics Processing Units (GPUs) and deep neural network hardware accelerators is very prominent. The mixed-signal arithmetic circuit is a new arithmetic architecture suitable for high-energy-efficiency deep neural network operations. This architecture processes the core complex operations of the neural network in the form of analog quantities, avoiding the high energy consumption overhead problem of complex digital operations while ensuring the accuracy of the neural network, and greatly improving the hardware energy efficiency performance of deep neural network applications.

[0003] In the design and implementation of the mixed-signal arithmetic circuit for deep neural networks, the arithmetic architecture based on switched capacitors is a technical route that has received extensive attention. Regarding the design principle of the switched-capacitor arithmetic circuit for deep neural networks, the amount of electric charge stored on the capacitor array is used as the change in the physical state. By controlling the charging and discharging of the capacitor through switches and the redistribution process of the charge between the capacitor arrays, an analog voltage value corresponding to digital operations or logical operations is established.

[0004] Focusing on computationally intensive algorithms, in recent years, many literatures have designed logic calculation circuits or matrix convolution calculation circuits based on switched-capacitor arrays, achieving significant energy consumption savings compared to digital operations while ensuring the operation speed and accuracy of the neural network. However, most of the existing designs are based on the principle of charge sharing between capacitors. During the calculation process, a charging and discharging voltage supply with a magnitude equal to the power supply voltage needs to be provided to the capacitor plates, resulting in a certain bottleneck in the energy consumption of the switched-capacitor adder circuit. Moreover, in the existing design of the switched-capacitor adder arithmetic circuit, a unit-weight capacitor array with a size equal to the number of addition operation data needs to be constructed, which usually brings a large capacitor area overhead in complex addition operations.

[0005] In summary, how to further reduce the area overhead of the arithmetic circuit and improve the arithmetic energy efficiency while ensuring the working speed and accuracy of the mixed-signal arithmetic circuit is still a key issue concerned and to be solved in the field of mixed-signal arithmetic circuit design. Summary of the Invention

[0006] In view of the above defects or improvement requirements of the prior art, the present invention provides a mixed-signal arithmetic circuit, aiming to reduce the area overhead of the arithmetic circuit and improve the arithmetic energy efficiency while ensuring the working speed and accuracy.

[0007] To achieve the above object, in a first aspect, the present invention provides a mixed-signal logic operation circuit, including: a first MOS transistor, a second MOS transistor, a third MOS transistor, a first capacitor, a second capacitor, a logic operation path, and a control unit; one end of the first capacitor serves as the output terminal VO of the logic operation circuit, and the other end is grounded; the source electrode of the first MOS transistor is connected to the drain electrode of the second MOS transistor, the source electrode of the second MOS transistor, the drain electrode of the third MOS transistor, and one end of the second capacitor are connected, and the source electrode of the third MOS transistor is connected to the other end of the second capacitor and is connected to the power supply voltage VDD;

[0008] The control unit is configured to input the data to be subjected to logic operation into the logic operation path during logic operation; and before each input, control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the second capacitor to the voltage VDD, and then control the first MOS transistor to turn on and the third MOS transistor to turn off;

[0009] The logic operation path is configured to control the connection state between the drain terminal of the first MOS transistor and the output terminal VO based on the level state of the input data.

[0010] Further preferably, when the logic operation implemented by the logic operation circuit is an AND summation operation:

[0011] The data to be subjected to logic operation includes: data signal x i and weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0012] The control unit inputs a set of x i and w i into the logic operation path each time;

[0013] The logic operation path is configured to, after receiving the input of x i and w i , when x i and w i are both high levels, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w i are not both high levels, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate electrode of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO corresponds to the voltage value corresponding to the AND summation operation result corresponding voltage value;

[0014] When the logic operation implemented by the logic operation circuit is an OR summation operation:

[0015] The data to be logically operated on includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals;

[0016] The control unit inputs a set of x i and w i into the logical operation path each time;

[0017] The logical operation path is used to, after receiving the inputs of x i and w i , when one of x i and w i is at a high level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a high level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the OR or summation operation result corresponding to;

[0018] When the logical operation implemented by the logical operation circuit is a non-summation operation:

[0019] The data to be logically operated on includes: data signal x i ; i = 1, 2, …, N; N is the total number of data signals;

[0020] The control unit inputs one x i into the logical operation path each time;

[0021] The logical operation path is used to, after receiving the input of x i , when x i is at a low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i is not at a low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the non-summation operation result corresponding to;

[0022] When the logical operation implemented by the logical operation circuit is a NAND non-summation operation:

[0023] The data to be logically operated on includes: data signal x i and weight signal w i; i = 1, 2, …, N; N is the total number of data signals or weight signals;

[0024] The control unit inputs a set of x i and w i into the logical operation path;

[0025] The logical operation path is used to, after receiving the inputs of x i and w i , when one of x i and w i is at a low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the NAND summation operation result corresponding to the voltage value;

[0026] When the logical operation implemented by the logical operation circuit is NOR summation operation:

[0027] The data to be logically operated includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals;

[0028] The control unit inputs a set of x i and w i into the logical operation path;

[0029] The logical operation path is used to, after receiving the inputs of x i and w i , when both x i and w i are at a low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w i are not both at a low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the NOR summation operation result corresponding to the voltage value;

[0030] When the logical operation implemented by the logical operation circuit is XNOR summation operation:

[0031] The data to be logically operated on includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals;

[0032] The control unit inputs a set of x i and w i into the logical operation path each time;

[0033] The logical operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are the same, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when the levels of x i and w i are different, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the XNOR summation operation result corresponding voltage value;

[0034] When the logical operation implemented by the logical operation circuit is an XOR summation operation:

[0035] The data to be logically operated on includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals;

[0036] The control unit inputs a set of x i and w i into the logical operation path each time;

[0037] The logical operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are different, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when the levels of x i and w i are the same, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superposed each time is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the XOR summation operation result corresponding voltage value.

[0038] Further preferably, when the logic operation implemented by the logic operation circuit is an AND summation operation: the logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the fourth MOS transistor is connected to the output terminal VO, and the source of the fifth MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i .

[0039] When the logic operation implemented by the logic operation circuit is an OR summation operation: the logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; the drains of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the output terminal VO, and the sources of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i ;

[0040] When the logic operation implemented by the logic operation circuit is a NOT summation operation: the logic operation path includes: a fourth MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO, the source is connected to the drain of the first MOS transistor, and if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ;

[0041] When the logic operation implemented by the logic operation circuit is a NAND summation operation: the logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the sources of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the drain of the first MOS transistor; the drains of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the output terminal VO; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ;

[0042] When the logic operation implemented by the logic operation circuit is a NOR summation operation: The logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO; the source of the fifth MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to w i 's inverted signal; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to x i 's inverted signal;

[0043] When the logic operation implemented by the logic operation circuit is an XNOR summation operation: The logic operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i 's inverted signal; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i 's inverted signal; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i 's inverted signal; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i 's inverted signal; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i ;

[0044] When the logic operation implemented by the logic operation circuit is an XOR summation operation: The logic operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to xi inverted signal; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i inverted signal; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i inverted signal; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i inverted signal; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i .

[0045] Further preferably, the above logic operation circuit further includes a MOS transistor C; the drain of the MOS transistor C is connected to the output terminal VO, and the source is grounded;

[0046] The control unit is further configured to perform a reset operation on the logic operation circuit before performing the logic operation: control the MOS transistor C to conduct, and turn off the first MOS transistor and the third MOS transistor to reset the output terminal VO to the ground; when performing the logic operation, control the MOS transistor C to be in the off state.

[0047] Further preferably, the control unit is further configured to adjust the conduction degree of the second MOS transistor by adjusting the magnitude of a preset bias voltage, thereby controlling the discharge current magnitude of the second capacitor, and further adjusting the magnitude of the superimposed voltage.

[0048] Further preferably, the control unit is further configured to input a clear signal to the gate of the first MOS transistor to control the switching state of the first MOS transistor, and input a pre-charge signal to the gate of the third MOS transistor to control the switching state of the third MOS transistor.

[0049] In a second aspect, the present invention provides a mixed-signal convolution operation circuit, including: a first MOS transistor, a second MOS transistor, a third MOS transistor, a first capacitor, a second capacitor, a third capacitor, an arithmetic operation path, and a control unit;

[0050] One end of the first capacitor serves as the positive-phase output terminal VP of the convolution operation circuit, and the other end is grounded; one end of the second capacitor serves as the inverted-phase output terminal VN of the convolution operation circuit, and the other end is grounded;

[0051] The source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor, the drain of the third MOS transistor, and one end of the third capacitor are connected, and the source of the third MOS transistor is connected to the other end of the third capacitor and is connected to the power supply voltage VDD;

[0052] The control unit is used to input the data signal x i and the weight signal w i into the arithmetic operation path when performing the convolution operation, and before each input of a group of x i and w i , control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the third capacitor to the voltage VDD, then control the first MOS transistor to turn on and the third MOS transistor to turn off, and input x i and w i into the arithmetic operation path; i = 1, 2, …, N; N is the length of the data to be convolved;

[0053] The arithmetic operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are the same, connect the drain of the first MOS transistor to the positive-phase output terminal VP to perform voltage superposition at the positive-phase output terminal VP; when the levels of x i and w i are opposite, connect the drain of the first MOS transistor to the negative-phase output terminal VN to perform voltage superposition at the negative-phase output terminal VN; wherein, the gate of the second MOS transistor is connected to a preset bias voltage to ensure that the magnitude of the voltage for each superposition is the same;

[0054] The final voltage difference between the positive-phase output terminal VP and the negative-phase output terminal VN is the voltage value corresponding to the convolution operation result .

[0055] Further preferably, the arithmetic operation path includes: the fourth to the eleventh MOS transistors; wherein, the sources of the fourth MOS transistor, the fifth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor; the drain of the fifth MOS transistor and the source of the seventh MOS transistor are connected; the drain of the eighth MOS transistor and the source of the tenth MOS transistor are connected; the drain of the ninth MOS transistor and the source of the eleventh MOS transistor are connected; the drains of the sixth MOS transistor and the tenth MOS transistor are commonly connected to the positive-phase output terminal VP; the drains of the seventh MOS transistor and the eleventh MOS transistor are commonly connected to the negative-phase output terminal VN;

[0056] If the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ;

[0057] If the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to wi inverted signal;

[0058] If the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i inverted signal;

[0059] If the eleventh MOS transistor is a PMOS transistor, its gate is connected to x i ; if the eleventh MOS transistor is an NMOS transistor, its gate is connected to x i inverted signal;

[0060] If the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to x i ;

[0061] If the tenth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the tenth MOS transistor is an NMOS transistor, its gate is connected to x i ;

[0062] If the eighth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the eighth MOS transistor is an NMOS transistor, its gate is connected to w i ;

[0063] If the ninth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the ninth MOS transistor is an NMOS transistor, its gate is connected to w i .

[0064] Further preferably, the above convolution operation circuit further includes: MOS transistor A and MOS transistor B; wherein, the drain of MOS transistor A is connected to the positive phase output terminal VP, and the source is grounded; the drain of MOS transistor B is connected to the inverted phase output terminal VN, and the source is grounded;

[0065] The control unit is further configured to perform a reset operation on the convolution operation circuit based on the DAC before performing the convolution operation: control MOS transistor A and MOS transistor B to conduct, and turn off the first MOS transistor and the third MOS transistor, so as to reset the positive phase output terminal VP and the inverted phase output terminal VN to ground; when performing the convolution operation, control MOS transistor A and MOS transistor B to be in the off state.

[0066] Further preferably, the control unit is further configured to adjust the conduction degree of the second MOS transistor by adjusting the magnitude of the preset bias voltage, so as to control the discharge current magnitude of the third capacitor, and further adjust the magnitude of the superimposed voltage.

[0067] Further preferably, the control unit is further configured to input a clearing signal to the gate of the first MOS transistor to control the switching state of the first MOS transistor, and input a pre-charging signal to the gate of the third MOS transistor to control the switching state of the third MOS transistor.

[0068] In a third aspect, the present invention provides a switched-capacitor arithmetic circuit, including: M charge injection calculation units, M first connection capacitors, and M second connection capacitors; wherein, the charge injection calculation unit is the logic arithmetic circuit provided in the first aspect of the present invention or the convolution arithmetic circuit provided in the second aspect of the present invention;

[0069] When the charge injection calculation unit is the logic arithmetic circuit provided in the first aspect of the present invention:

[0070] The output terminals VO of the M charge injection calculation units are respectively connected to one end of the M connection capacitors in a one-to-one correspondence, and the other ends of the M connection capacitors are connected together and used as the output terminal VOUT of the switched-capacitor arithmetic circuit;

[0071] The outputs of the output terminals VO of the M charge injection calculation units are superimposed at the output terminal VOUT through the corresponding connection capacitors;

[0072] A logic operation is divided into M groups of sub-logic operations; one charge injection calculation unit is used to implement one sub-logic operation; the output of the output terminal VOUT is the voltage value corresponding to the required logic operation result;

[0073] When the charge injection calculation unit is the convolution arithmetic circuit provided in the second aspect of the present invention:

[0074] The positive-phase output terminals VP of the M charge injection calculation units are respectively connected to one end of the M first connection capacitors in a one-to-one correspondence, and the other ends of the M first connection capacitors are connected together and used as the positive-phase output terminal VOUTP of the switched-capacitor arithmetic circuit;

[0075] The inverting output terminals VN of the M charge injection calculation units are respectively connected to one end of the M second connection capacitors in a one-to-one correspondence, and the other ends of the M second connection capacitors are connected together and used as the inverting output terminal VOUTN of the switched-capacitor arithmetic circuit;

[0076] The outputs of the positive-phase output terminals VP of the M charge injection calculation units are superimposed at the positive-phase output terminal VOUTP through the corresponding first connection capacitors;

[0077] The outputs of the inverting output terminals VN of the M charge injection calculation units are superimposed at the inverting output terminal VOUTN through the corresponding second connection capacitors;

[0078] A convolution operation is divided into M groups of sub-convolution operations; a charge injection calculation unit is used to implement a sub-convolution operation; the final voltage difference between the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN is the voltage value corresponding to the result of the convolution operation to be obtained.

[0079] Further preferably, when the charge injection calculation unit is the logic operation circuit provided in the first aspect of the present invention, the switched-capacitor operation circuit further includes: a reset circuit connected to the output terminal VOUT;

[0080] When the charge injection calculation unit is the convolution operation circuit provided in the second aspect of the present invention, the switched-capacitor operation circuit further includes: reset circuits respectively connected to the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN.

[0081] In a fourth aspect, the present invention provides an electronic chip, including the logic operation circuit provided in the first aspect of the present invention, or the convolution operation circuit provided in the second aspect of the present invention, or the switched-capacitor operation circuit provided in the third aspect of the present invention.

[0082] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0083] 1. The first aspect of the present invention provides a logic operation circuit, which is a charge injection logic based on a transmission channel-capacitor; wherein, the first capacitor is used to determine the output terminal of the logic operation circuit, the second capacitor is used to provide a certain voltage, and the logic operation path selects the charge path from the second capacitor to the first capacitor based on each input data signal, so as to superimpose the voltage value at the output terminal, thereby realizing digital-to-analog conversion (DAC); time division multiplexing is realized through a step-by-step injection method, so as to establish an analog voltage value related to the logic operation result at the output terminal. Only two capacitors are used to realize the logic operation, and there is no need to construct a unit weight capacitor array with the same size as the number of logic operations, which greatly reduces the capacitance area overhead. While ensuring the working speed and accuracy, it can reduce the area overhead of the operation circuit and improve the operation energy efficiency.

[0084] 2. Further, in the logic operation circuit provided by the present invention, the logic operation path is composed of multiple MOS transistors, forming data signals x i and w i are both at low level, data signals x i and w i are both at high level, data signal x i is at low level and w i is at high level, data signal x i is at high level and w iThe conduction of the charge path is determined by the paths in four cases where the level is low. By embedding logical operations in the charge path, a charge injection operation unit capable of implementing various basic logics is constructed, greatly reducing the energy consumption overhead of logical operations in the neural network convolution operation, and further improving the operation energy efficiency of the circuit.

[0085] 3. The second aspect of the present invention provides a convolution operation circuit. Among them, the first capacitor and the second capacitor are used to determine the positive-phase output terminal and the anti-phase output terminal of the convolution operation circuit. The third capacitor is used to provide a certain voltage. The arithmetic operation path selects the positive-phase charge path from the third capacitor to the first capacitor or the anti-phase charge path from the third capacitor to the second capacitor based on each input data signal and weight signal, so as to superimpose a voltage value on the positive-phase output terminal or the anti-phase output terminal; time-division multiplexing is realized through the step-by-step injection method, so as to establish an analog voltage value related to the convolution operation result at the differential output terminal. Only three capacitors are used to realize the convolution operation, without constructing a unit weight capacitor array with the same size as the number of addition operation data, greatly reducing the capacitance area overhead, and being able to reduce the area overhead of the operation circuit while ensuring the working speed and accuracy, and improving the operation energy efficiency.

[0086] 4. Further, in the convolution operation circuit provided by the present invention, the arithmetic operation path is composed of multiple MOS transistors, forming the data signal x i and the weight signal w i both being low level, the data signal x i and the weight signal w i both being high level, the data signal x i being low level and the weight signal w i being high level, the data signal x i being high level and the weight signal w i being low level. The paths in these four cases are used to select the positive-phase charge path or the anti-phase charge path. Binary arithmetic multiplication operation logic is embedded in the charge path, greatly reducing the energy consumption overhead of multiplication operations in the neural network convolution operation, and further improving the operation energy efficiency of the circuit.

[0087] 5. The third aspect of the present invention provides a switched-capacitor operation circuit. By integrating the step-by-step injection calculation method and the parallel calculation method, a charge injection - switched-capacitor operation circuit capable of flexibly weighing the core calculation indicators is constructed, and an optimal design implementation can be flexibly obtained in terms of core indicators such as hardware overhead, calculation performance, and calculation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 is a schematic structural diagram of the mixed-signal logic operation circuit provided by the first aspect of the present invention;

[0089] Figure 2Schematic diagram of the summation operation circuit provided in Embodiment 1 of the present invention;

[0090] Figure 3 Schematic diagram of the NAND summation operation circuit provided in Embodiment 2 of the present invention;

[0091] Figure 4 Schematic diagram of the OR summation operation circuit provided in Embodiment 3 of the present invention;

[0092] Figure 5 Schematic diagram of the NOR summation operation circuit provided in Embodiment 4 of the present invention;

[0093] Figure 6 Schematic diagram of the NOT summation operation circuit provided in Embodiment 5 of the present invention;

[0094] Figure 7 Schematic diagram of the XNOR summation operation circuit provided in Embodiment 6 of the present invention;

[0095] Figure 8 Schematic diagram of the XOR summation operation circuit provided in Embodiment 7 of the present invention;

[0096] Figure 9 Schematic diagram of the convolution operation circuit provided in Embodiment 8 of the present invention;

[0097] Figure 10 Schematic diagram of the convolution operation circuit provided in Embodiment 9 of the present invention;

[0098] Figure 11 Schematic diagram of the switched-capacitor operation circuit CISC-OC provided in the third aspect of the present invention;

[0099] Figure 12 Timing diagram of the switched-capacitor operation circuit CISC-OC provided in the third aspect of the present invention. Detailed implementation manners

[0100] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0101] To achieve the above objectives, in the first aspect, the present invention provides a mixed-signal logic operation circuit, which is a charge injection logic operation circuit based on a transmission channel-capacitor (denoted as TPC CI Logic circuit) for implementing various basic logic operations (AND, OR, NOT, NAND, NOR, XNOR, and XOR logic operations), such asFigure 1 As shown in the figure, it includes: a first MOS transistor 13, a second MOS transistor 12, a third MOS transistor 11, a first capacitor 16, a second capacitor 15, a logic operation path, and a control unit; one end of the first capacitor serves as the output terminal VO of the logic operation circuit, and the other end is grounded; the source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor, the drain of the third MOS transistor, and one end of the second capacitor are connected, and the source of the third MOS transistor is connected to the other end of the second capacitor and connected to the power supply voltage VDD;

[0102] The control unit is used to input the data to be logically operated into the logic operation path during logical operation; and before each input, the first MOS transistor is turned off and the third MOS transistor is turned on to charge the second capacitor to the voltage VDD, and then the first MOS transistor is turned on and the third MOS transistor is turned off;

[0103] The logic operation path is used to control the connection state between the drain end of the first MOS transistor and the output terminal VO based on the level state of the input data.

[0104] It should be noted that the above first MOS transistor 13, second MOS transistor 12, and third MOS transistor 11 can be PMOS transistors or NMOS transistors, and there is no limitation here.

[0105] Specifically, the above logic operation circuit can be: an AND summation operation circuit, an OR summation operation circuit, a NOT summation operation circuit, a NAND summation operation circuit, a NOR summation operation circuit, an XNOR summation logic circuit, or an XOR summation logic circuit; correspondingly, the logic operation path can be: an AND summation operation path, an OR summation operation path, a NOT summation operation path, a NAND summation operation path, a NOR summation operation path, an XNOR summation operation path, or an XOR summation operation path.

[0106] It should be noted that the specific operation process of each logic operation is as follows: when the logic operation result of the input data is 1, the logic operation circuit selects and conducts the charge injection path from the second capacitor to the first capacitor, and after a charge injection, a voltage value of a certain magnitude is superimposed on the output terminal VO; when the logic operation result of the input data is 0, the logic operation circuit disconnects the charge injection path from the second capacitor to the first capacitor and keeps the output terminal voltage unchanged. Taking the above working process as a cycle, the logic operation circuit based on the DAC can establish an analog voltage value related to the logic operation summation result at the output terminal through a step-by-step injection process according to the logic operation result of the input value.

[0107] Preferably, in an alternative embodiment, the control unit is further configured to input a clear signal to the gate of the first MOS transistor to control the switching state of the first MOS transistor, and input a pre-charge signal to the gate of the third MOS transistor to control the switching state of the third MOS transistor.

[0108] Preferably, in an alternative embodiment, the above-mentioned logic operation circuit further includes a MOS transistor C; wherein, the drain of the MOS transistor C is connected to the output terminal VO, and the source is grounded;

[0109] The control unit is further configured to reset the logic operation circuit before performing a logic operation: control the MOS transistor C to conduct, and the first MOS transistor and the third MOS transistor to turn off, so as to reset the output terminal VO to ground; when performing a logic operation, control the MOS transistor A to be in an off state.

[0110] It should be noted that the above-mentioned MOS transistor C can be a PMOS transistor or an NMOS transistor, and is not limited here.

[0111] The following is a detailed description in conjunction with specific embodiments. In the following embodiments, w i is a high-level signal or a low-level signal; x i is a high-level signal or a low-level signal; the high-level signal corresponds to the value 1, and the low-level signal corresponds to the value 0.

[0112] Embodiment 1

[0113] In this embodiment, the logic operation implemented by the logic operation circuit is an AND-summation operation (i.e., AND logic operation summation), the logic operation circuit is an AND-summation operation circuit; the logic operation path is an AND-summation operation path; the data to be subjected to the logic operation includes: the data signal x i and the weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0114] The control unit is configured to input the data signal x i and the weight signal w i into the AND-summation operation path when performing the AND-summation operation, and before each input of a group of x i and w i , control the first MOS transistor to turn off and the third MOS transistor to conduct, so as to charge the second capacitor to the voltage VDD, and then control the first MOS transistor to conduct and the third MOS transistor to turn off, and input x i and w i into the AND-summation operation path;

[0115] The AND-summation operation path is configured to, after receiving the input of x i and w i , when x i and wi When both are at high level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w i are not both at high level, do not connect the drain terminal of the first MOS transistor to the output terminal VO, and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superimposed voltage is the same; the final voltage value at the output terminal VO corresponds to the result of the summation operation The corresponding voltage value.

[0116] Specifically, there are multiple implementation manners for the summation operation path:

[0117] In an alternative implementation manner, the summation operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO; the source of the fifth MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i .

[0118] In another alternative implementation manner, the summation logic operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor; wherein, the drain of the fourth MOS transistor is connected to the output terminal VO; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor, and the source of the seventh MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to w i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i .

[0119] It should be noted that the input positions of the above x i and w i can be interchanged, and there is no restriction here.

[0120] The following is a detailed description with an implementation manner: Specifically, as Figure 2 shown is the first specific implementation manner of the AND summation operation circuit disclosed by the present invention. Taking PMOS as an example for all MOS transistors, in this implementation manner, the AND summation operation circuit 11 includes: six MOS transistors (111, 112, 113, 114, 115, 116), two capacitors (117 and 118), and two inverter logic circuits (119 and 1110). Among them, MOS transistors 113, 114, and 115 are respectively the above-mentioned first to third MOS transistors, and MOS transistors 111 and 112 are respectively the above-mentioned fourth and fifth MOS transistors; MOS transistor 116 is the above-mentioned MOS transistor C. Specifically, the source of MOS transistor 112 is connected to the drain of MOS transistor 113, the source of MOS transistor 111 is connected to the drain of MOS transistor 112, the drain of MOS transistor 111, the drain of MOS transistor 116, and the upper plate of the first capacitor 117 are connected and this terminal is defined as the output terminal VO of the AND summation operation circuit. The source of MOS transistor 113 is connected to the drain of MOS transistor 114, the source of MOS transistor 114, the drain of MOS transistor 115, and the upper plate of the second capacitor 118 are connected, the source of MOS transistor 115 is connected to the lower plate of the second capacitor 118 and connected to the power supply VDD, the source of MOS transistor 116 is connected to the lower plate of the first capacitor 117 and connected to the ground, the gate of MOS transistor 111 is connected to the output terminal of the first inverter 119, the gate of MOS transistor 112 is connected to the output terminal of the second inverter 1110, the input terminal of the first inverter 119 is connected to the input data signal x i , and the input terminal of the second inverter 1110 is connected to the input data signal w i , and its high level and low level correspond to the values 1 and 0. The gate of MOS transistor 113 is connected to the clear signal CLR, the gate of MOS transistor 114 is connected to the bias voltage VBIAS, the gate of MOS transistor 115 is connected to the precharge signal CHARGE, and the gate of MOS transistor 116 is connected to the reset signal RESET.

[0121] Embodiment 2

[0122] In this embodiment, the logic operation implemented by the logic operation circuit is NAND summation operation (NAND logic operation summation), the logic operation circuit is a NAND summation operation circuit, and the logic operation path is a NAND summation operation path; the data to be subjected to the logic operation includes: the data signal x i and the weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0123] The control unit is used to input the data signal x i and the weight signal w i into the NAND summation operation path, and before each group of x i and w i is input, the first MOS transistor is controlled to turn off and the third MOS transistor is controlled to turn on to charge the second capacitor to the voltage VDD, then the first MOS transistor is controlled to turn on and the third MOS transistor is controlled to turn off, and x i and w i are input into the NAND summation operation path;

[0124] The NAND summation operation path is used to, after receiving the inputs of x i and w i , when one of x i and w i is at a low level, connect the drain of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a low level, do not connect the drain of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the NAND summation operation result corresponding voltage value.

[0125] Specifically, there are various implementation manners of the NAND summation operation path:

[0126] In an optional implementation manner, the NAND summation operation path includes: a fourth MOS transistor and a fifth MOS transistor; among them, the source of the fourth MOS transistor and the source of the fifth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor and the drain of the fifth MOS transistor are commonly connected to the output terminal VO; the gate of the fourth MOS transistor is connected to w i ; the gate of the fifth MOS transistor is connected to x i . If the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ;

[0127] In another alternative embodiment, the AND-NOT operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; wherein, the sources of the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor; the drain of the sixth MOS transistor is connected to the source of the seventh MOS transistor; the drain of the eighth MOS transistor is connected to the source of the ninth MOS transistor; the sources of the fifth MOS transistor, the seventh MOS transistor, and the ninth MOS transistor are commonly connected to the output terminal VO; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the ninth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the ninth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the eighth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the eighth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i The inverted signal.

[0128] It should be noted that the input positions of the above x i and w i can be interchanged, and there is no restriction here.

[0129] The following is a detailed description with an embodiment: Specifically, Figure 3The following shows the first specific embodiment of the NAND summing operation circuit based on DAC disclosed by the present invention. In this embodiment, the NAND summing operation circuit 11 based on DAC includes: six MOS transistors (111, 112, 113, 114, 115, 116), two capacitors (117 and 118), and two inverter logic circuits (119 and 1110). Among them, MOS transistors 113, 114, and 115 are respectively the first to third MOS transistors mentioned above, and MOS transistors 111 and 112 are respectively the fourth and fifth MOS transistors mentioned above; MOS transistor 116 is the MOS transistor C mentioned above. Specifically, the source of MOS transistor 111, the source of MOS transistor 112, and the drain of MOS transistor 113 are connected. The drain of MOS transistor 111, the drain of MOS transistor 112, the drain of MOS transistor 116, and the upper plate of the first capacitor 117 are connected and this terminal is defined as the output terminal VO of CICU. The source of MOS transistor 113 and the drain of MOS transistor 114 are connected. The source of MOS transistor 114, the drain of MOS transistor 115, and the upper plate of the second capacitor 118 are connected. The source of MOS transistor 115 and the lower plate of the second capacitor 118 are connected to the power supply VDD. The source of MOS transistor 116 and the lower plate of the first capacitor 117 are connected to the ground. The gate of MOS transistor 111 is connected to the input data signal x i , and the gate of MOS transistor 112 is connected to the input data signal w i , whose high level and low level correspond to the values 1 and 0 respectively. The gate of MOS transistor 113 is connected to the clear signal CLR, the gate of MOS transistor 114 is connected to the bias voltage VBIAS, the gate of MOS transistor 115 is connected to the precharge signal CHARGE, and the gate of MOS transistor 116 is connected to the reset signal RESET.

[0130] Specifically elaborate Figure 2 and Figure 3 the circuit working principle. When the RESET signal is at a high level, the CLR signal is at a high level, and the CHARGE signal is at a high level, MOS transistor 116 conducts to the ground, the circuit output terminal is reset to a low level, the gate of MOS transistor 113 is at a high level, MOS transistor 113 is turned off, and the circuit stops working. When the RESET signal is at a low level, MOS transistor 116 is turned off, and the circuit is in a working state. At this time, when the CHARGE signal is at a low level and the CLR signal is at a high level, the circuit works in a precharge state, MOS transistor 113 is turned off, MOS transistor 115 conducts, and the upper plate of the second capacitor 118 is charged to the VDD level. When the CHARGE signal is at a high level and the CLR signal is at a low level, MOS transistor 113 conducts, MOS transistor 115 is turned off, and at this time:

[0131] For realizing the AND summing operation Figure 2Circuit. At this time, according to the value of the input data, the first inverter 119 and the second inverter 1110 output inverted signals; taking the signal x corresponding to the input data i and w i both being high level as an example. The output terminals of the first inverter 119 and the second inverter 1110 are at low level, the gates of the MOS transistors 111 and 112 are both at low level, and the MOS transistors 111 and 112 are turned on. At this time, the charge on the upper plate of the second capacitor 118 discharges to the upper plate of the first capacitor 117 through the path formed by the MOS transistors 114, 113, 112, and 111. By setting the bias voltage value, the conduction degree of the MOS transistor 114 can be adjusted, the magnitude of the discharge current of the second capacitor 118 can be controlled, and thus a fixed - sized voltage ΔV can be established at the output terminal of the circuit within a unit time. If one of the two input data signals is high level, one is low level, or both are low level, the CICU 11 circuit does not inject charge into the output terminal. Thereafter, taking N working cycles of the above - mentioned circuit as an example, according to the AND - sum operation result of the input data, a value of 1 corresponds to a high - level signal, and a value of 0 corresponds to a low - level signal; if the AND - sum operation result of the input data is 1, then a ΔV voltage is superimposed on the output terminal of the circuit, and if the AND - sum operation result of the input data is 0, the voltage at the output terminal of the circuit remains unchanged. After N circuit working cycles, assuming the number of cycles with the AND - sum operation result of 1 for the data is q, then the output voltage of the circuit is: V O = qΔV.

[0132] For the circuit that implements the NAND - sum operation Figure 3 taking the signal x corresponding to the input data i being low level and w i being high level as an example. The gate of the MOS transistor 111 is at low level, the gate of the MOS transistor 112 is at high level, the MOS transistor 111 is turned on, and the MOS transistor 112 is turned off. At this time, the charge on the upper plate of the second capacitor 118 discharges to the upper plate of the first capacitor 117 through the path formed by the MOS transistors 114, 113, and 111. By setting the bias voltage value, the conduction degree of the MOS transistor 114 can be adjusted, the magnitude of the discharge current of the second capacitor 118 can be controlled, and thus a fixed - sized voltage ΔV can be established at the output terminal of the circuit within a unit time. Similarly, if the signal x corresponding to the input data i is high level and w iIf either of them is at a low level or both are at low levels, the circuit injects charge into the output terminal; if both input data signals are at high levels, the circuit does not inject charge into the output terminal. Thereafter, taking N working cycles of the above circuit as an example, according to the NAND summation operation result of the input data, when the value is 1, it corresponds to a high-level signal, and when the value is 0, it corresponds to a low-level signal; if the NAND summation operation result of the input data is 1, a ΔV voltage is superimposed on the output terminal of the circuit, and if the NAND summation operation result of the input data is 0, the voltage at the output terminal of the circuit remains unchanged. After N circuit working cycles, assuming the number of cycles with the NAND summation operation result of the data being 1 is q, then the output voltage of the circuit is: V O = qΔV.

[0133] Embodiment 3

[0134] In this embodiment, the logic operation implemented by the logic operation circuit is an OR summation operation (OR logic operation summation), the logic operation circuit is an OR summation operation circuit, and the logic operation path is an OR summation operation path; the data to be subjected to the logic operation includes: data signal x i and weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0135] The control unit is used to input the data signal x i and the weight signal w i into the OR summation operation path during the OR summation operation, and before each group of x i and w i is input, control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the second capacitor to the voltage VDD, then control the first MOS transistor to turn on and the third MOS transistor to turn off, and input x i and w i into the OR summation operation path;

[0136] The OR summation operation path is used to, after receiving the inputs of x i and w i , when either of x i and w i is at a high level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a high level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superimposed voltage is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the OR summation operation result corresponding thereto.

[0137] Specifically, there are multiple implementation manners for the OR summation operation path:

[0138] In an alternative implementation manner, the OR summation operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source electrodes of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the drain electrode of the first MOS transistor; the drain electrodes of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the output terminal VO; if the fourth MOS transistor is a PMOS transistor, its gate electrode is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate electrode is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate electrode is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate electrode is connected to w i .

[0139] In another alternative implementation manner, the OR summation operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; wherein, the source electrodes of the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are commonly connected to the drain electrode of the first MOS transistor; the drain electrode of the fourth MOS transistor is connected to the source electrode of the fifth MOS transistor; the drain electrode of the sixth MOS transistor is connected to the source electrode of the seventh MOS transistor; the drain electrode of the eighth MOS transistor is connected to the source electrode of the ninth MOS transistor; the source electrodes of the fifth MOS transistor, the seventh MOS transistor, and the ninth MOS transistor are commonly connected to the output terminal VO; if the seventh MOS transistor is a PMOS transistor, its gate electrode is connected to w i ; if the seventh MOS transistor is an NMOS transistor, its gate electrode is connected to the inverted signal of w i ; if the eighth MOS transistor is a PMOS transistor, its gate electrode is connected to x i ; if the eighth MOS transistor is an NMOS transistor, its gate electrode is connected to the inverted signal of x i ; if the fifth MOS transistor is a PMOS transistor, its gate electrode is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate electrode is connected to w i ; if the ninth MOS transistor is a PMOS transistor, its gate electrode is connected to the inverted signal; if the ninth MOS transistor is an NMOS transistor, its gate electrode is connected to w i ; if the fourth MOS transistor is a PMOS transistor, its gate electrode is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate electrode is connected to x i ; if the sixth MOS transistor is a PMOS transistor, its gate electrode is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate electrode is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate electrode is connected to the inverted signal of x.

[0140] It should be noted that the input positions of the above-mentioned x i and w i can be interchanged, and there is no restriction here.

[0141] The following is a detailed description with an implementation manner: As Figure 4 shown is a specific implementation manner of the OR summation operation circuit based on DAC disclosed in the present invention. In this implementation manner, the OR summation operation circuit 11 based on DAC includes: six MOS transistors (111, 112, 113, 114, 115, 116), two capacitors (117 and 118), and two inverter logic circuits (119 and 1110). Among them, MOS transistors 113, 114, and 115 are the first to third MOS transistors respectively, and MOS transistors 111 and 112 are the fourth and fifth MOS transistors respectively; MOS transistor 116 is the MOS transistor C. Specifically, the source of MOS transistor 111, the source of MOS transistor 112, and the drain of MOS transistor 113 are connected together, and the drain of MOS transistor 111, the drain of MOS transistor 112, the drain of MOS transistor 116, and the upper plate of the first capacitor 117 are connected together and this terminal is defined as the output terminal VO of the circuit. The source of MOS transistor 113 is connected to the drain of MOS transistor 114, the source of MOS transistor 114, the drain of MOS transistor 115, and the upper plate of the second capacitor 118 are connected together, the source of MOS transistor 115 is connected to the lower plate of the second capacitor 118 and connected to the power supply VDD, the source of MOS transistor 116 is connected to the lower plate of the first capacitor 117 and connected to the ground, the gate of MOS transistor 111 is connected to the output terminal of the first inverter 119, the gate of MOS transistor 112 is connected to the output terminal of the second inverter 1110, the input terminal of the first inverter 119 is connected to the input data signal x i , and the input terminal of the second inverter 1110 is connected to the input data signal w i , and its high level and low level correspond to the values 1 and 0. The gate of MOS transistor 113 is connected to the clear signal CLR, the gate of MOS transistor 114 is connected to the bias voltage VBIAS, the gate of MOS transistor 115 is connected to the precharge signal CHARGE, and the gate of MOS transistor 116 is connected to the reset signal RESET.

[0142] Example 4

[0143] In this embodiment, the logic operation implemented by the logic operation circuit is NOR summation operation (NOR logic operation summation), the logic operation circuit is a NOR summation operation circuit, and the logic operation path is a NOR summation operation path; the data to be logically operated includes: the data signal x i and the weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0144] The control unit is used to input the data signal x i and the weight signal w i into the NOR summation operation path. And before each group of x i and w i is input, the first MOS transistor is controlled to turn off and the third MOS transistor is controlled to turn on to charge the second capacitor to the voltage VDD. Then the first MOS transistor is controlled to turn on and the third MOS transistor is controlled to turn off, and x i and w i are input into the NOR summation operation path;

[0145] The NOR summation operation path is used to, after receiving the inputs of x i and w i , when both x i and w i are at low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w ｉ are not both at low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superposed voltage is the same; the final voltage value at the output terminal VO is the voltage value corresponding to the NOR summation operation result corresponding voltage value.

[0146] Specifically, there are multiple implementation manners for the NOR summation operation path:

[0147] In an alternative implementation manner, the NOR summation operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source terminal of the fourth MOS transistor is connected to the drain terminal of the fifth MOS transistor; the drain terminal of the fourth MOS transistor is connected to the output terminal VO; the source terminal of the fifth MOS transistor is connected to the drain terminal of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w ｉ ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w ｉ ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x ｉ ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x ｉ .

[0148] In another alternative embodiment, the NOR summing operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the drain of the fourth MOS transistor is connected to the output terminal VO; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor, and the source of the seventh MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w ｉ ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w ｉ ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i .

[0149] It should be noted that the input positions of the above x i and w i can be interchanged, and there is no limitation here.

[0150] The following is a detailed description with an embodiment: As Figure 5The specific implementation of the NOR summing operation circuit based on DAC disclosed by the present invention is shown. The NOR summing operation circuit 11 based on DAC includes: six MOS transistors (111, 112, 113, 114, 115, 116) and two capacitors (117 and 118). Among them, the MOS transistors 113, 114, and 115 are respectively the first to third MOS transistors as described above, and the MOS transistors 111 and 112 are respectively the fourth and fifth MOS transistors; the MOS transistor 116 is the MOS transistor C as described above. Specifically, the source of the MOS transistor 112 is connected to the drain of the MOS transistor 113, the source of the MOS transistor 111 is connected to the drain of the MOS transistor 112, the drain of the MOS transistor 111, the drain of the MOS transistor 116, and the upper plate of the first capacitor 117 are connected and this terminal is defined as the output terminal VO of the circuit. The source of the MOS transistor 113 is connected to the drain of the MOS transistor 114, the source of the MOS transistor 114, the drain of the MOS transistor 115, and the upper plate of the second capacitor 118 are connected, the source of the MOS transistor 115 is connected to the lower plate of the second capacitor 118 and connected to the power supply VDD, the source of the MOS transistor 116 is connected to the lower plate of the first capacitor 117 and connected to the ground, and the gate of the MOS transistor 111 is connected to the input data signal x i , the gate of the MOS transistor 112 is connected to the input data signal w i , whose high level and low level correspond to the values 1 and 0. The gate of the MOS transistor 113 is connected to the clear signal CLR, the gate of the MOS transistor 114 is connected to the bias voltage VBIAS, the gate of the MOS transistor 115 is connected to the precharge signal CHARGE, and the gate of the MOS transistor 116 is connected to the reset signal RESET.

[0151] Specifically elaborate Figure 4 and Figure 5 the circuit working principle. As Figure 4 and Figure 5 shown, when the RESET signal is at high level, the CLR signal is at high level, and the CHARGE signal is at high level, the MOS transistor 116 conducts to the ground, the circuit output terminal is reset to low level, the gate of the MOS transistor 113 is at high level, the MOS transistor 113 is turned off, and the circuit stops working. When the RESET signal is at low level, the MOS transistor 116 is turned off, and the circuit is in the working state. At this time, when the CHARGE signal is at low level and the CLR signal is at high level, the circuit works in the precharge state, the MOS transistor 113 is turned off, the MOS transistor 115 is turned on, and the upper plate of the second capacitor 118 is charged to the VDD level. When the CHARGE signal is at high level and the CLR signal is at low level, the MOS transistor 113 is turned on, the MOS transistor 115 is turned off, and at this time:

[0152] For the CICU 11 circuit that implements an OR or summation operation, at this time, according to the value of the input data, the first inverter 119 and the second inverter 1110 output inverted signals; taking the signal x corresponding to the input data i as high level and w i as low level as an example. The output of the first inverter 119 is low level, the output terminal of the second inverter 1110 is high level, the gate of the MOS transistor 111 is low level, the gate of the MOS transistor 112 is high level, the MOS transistor 111 is turned on, and the MOS transistor 112 is turned off. At this time, the charge on the upper plate of the second capacitor 118 discharges to the upper plate of the first capacitor 117 through the path formed by the MOS transistor 114, the MOS transistor 113, and the MOS transistor 111. By setting the bias voltage value, the conduction degree of the MOS transistor 114 can be adjusted, and the magnitude of the discharge current of the second capacitor 118 can be controlled, so as to realize the establishment of a fixed voltage ΔV at the output terminal of the circuit within a unit time. Similarly, if the signal x corresponding to the input data i is high level and w i is low level or both are high level, the CICU 11 circuit injects charge into the output terminal; if the input data are all low level, the circuit does not inject charge into the output terminal. After that, taking N working cycles of the above circuit as an example, according to the OR or summation operation result of the input data, a high level signal corresponds to a value of 1, and a low level signal corresponds to a value of 0; if the OR or summation operation result of the input data is 1, a ΔV voltage is superimposed on the output terminal of the circuit, and if the OR or summation operation result of the input data is 0, the voltage at the output terminal of the circuit remains unchanged. After N circuit working cycles, assuming that the number of cycles with the OR or summation operation result of 1 for the data is q, the output voltage of the circuit is: V O = qΔV.

[0153] For the circuit that implements a NOR summation operation, taking the signals x i and w iTake the case where both are low levels. The gates of MOS transistor 111 and MOS transistor 112 are both at low levels, and MOS transistor 111 and MOS transistor 112 are turned on. At this time, the charge on the upper plate of the second capacitor 118 discharges to the upper plate of the first capacitor 117 through the path formed by MOS transistor 114, MOS transistor 113, MOS transistor 112, and MOS transistor 111. By setting the bias voltage value, the conduction degree of MOS transistor 114 can be adjusted, the magnitude of the discharge current of the second capacitor 118 can be controlled, and thus a fixed - sized voltage ΔV can be established at the output end of the CICU 11 circuit within a unit time. If one of the input data signals is at a low level, one is at a high level, or both are at high levels, the circuit does not inject charge into the output end. Thereafter, taking N working cycles of the above - mentioned circuit as an example, according to the NOR - sum operation result of the input data, when the value is 1, it corresponds to a high - level signal, and when the value is 0, it corresponds to a low - level signal; if the NOR - sum operation result of the input data is 1, a ΔV voltage is superimposed at the output end of the circuit, and if the NOR - sum operation result of the input data is 0, the voltage at the output end of the circuit remains unchanged. After N circuit working cycles, assuming the number of cycles with the NOR - sum operation result of 1 for the data is q, the output voltage of the CICU 11 circuit is: V O = qΔV.

[0154] Embodiment 5

[0155] In this embodiment, the logical operation implemented by the logical operation circuit is a NOR - sum operation (NOR logical operation summation), the logical operation circuit is a NOR - sum operation circuit, and the logical operation path is a NOR - sum operation path; the data to be logically operated includes: data signal x i ; i = 1, 2,..., N; N is the total number of data signals;

[0156] The control unit is used to input the data signal x i into the NOR - sum operation path during the NOR - sum operation, and before each input of an x i , turn off the first MOS transistor and turn on the third MOS transistor to charge the second capacitor to the voltage VDD, then turn on the first MOS transistor, turn off the third MOS transistor, and input x i into the NOR - sum operation path;

[0157] The NOR - sum operation path is used to, after receiving the input of x i , when x i is at a low level, connect the drain of the first MOS transistor to the output end VO to perform voltage superposition at the output end VO; when x iWhen it is not at a low level, the drain terminal of the first MOS transistor is not connected to the output terminal VO, and voltage superposition is no longer performed at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO corresponds to the non-summation operation result The corresponding voltage value.

[0158] Specifically, there are various implementation manners for the non-summation operation path:

[0159] In an alternative implementation manner, the non-summation operation path includes a fourth MOS transistor; the source of the fourth MOS transistor is connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i .

[0160] In another alternative implementation manner, the non-summation operation path includes a fourth MOS transistor and a fifth MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor; the drain of the fifth MOS transistor is connected to the output terminal VO; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i .

[0161] The following is a detailed description with an implementation manner: Specifically, as Figure 6The following shows an implementation of the DAC-based non-summation operation circuit disclosed by the present invention. In this implementation, the DAC-based non-summation operation circuit 11 includes: five MOS transistors (111, 112, 113, 114, 115) and two capacitors (116 and 117). Among them, MOS transistors 112, 113, and 114 are the first to third MOS transistors respectively, and MOS transistor 111 is the fourth MOS transistor; MOS transistor 115 is the MOS transistor C. Specifically, the source of MOS transistor 111 is connected to the drain of MOS transistor 112, and the drain of MOS transistor 111, the drain of MOS transistor 115, and the upper plate of the first capacitor 117 are connected and defined as the output terminal VO of the circuit. The source of MOS transistor 112 is connected to the drain of MOS transistor 113, the source of MOS transistor 113, the drain of MOS transistor 114, and the upper plate of the second capacitor 116 are connected, the source of MOS transistor 114 is connected to the lower plate of the second capacitor 116 and connected to the power supply VDD, the source of MOS transistor 115 is connected to the lower plate of the first capacitor 117 and connected to the ground, and the gate of MOS transistor 111 is connected to the input data signal x i , whose high level and low level correspond to the values 1 and 0. The gate of MOS transistor 112 is connected to the clear signal CLR, the gate of MOS transistor 113 is connected to the bias voltage VBIAS, the gate of MOS transistor 114 is connected to the precharge signal CHARGE, and the gate of MOS transistor 115 is connected to the reset signal RESET.

[0162] Specifically elaborate Figure 6 the circuit working principle. As Figure 6 shown, when the RESET signal is at a high level, the CLR signal is at a high level, and the CHARGE signal is at a high level, MOS transistor 115 conducts to the ground, the circuit output terminal is reset to a low level, the gate of MOS transistor 112 is at a high level, MOS transistor 112 is turned off, and the circuit stops working. When the RESET signal is at a low level, MOS transistor 115 is turned off, and the circuit is in a working state. At this time, when the CHARGE signal is at a low level and the CLR signal is at a high level, the circuit works in a precharge state, MOS transistor 112 is turned off, MOS transistor 114 conducts, and the upper plate of the second capacitor 116 is charged to the VDD level.

[0163] When the CHARGE signal is at a high level and the CLR signal is at a low level, MOS transistor 112 conducts and MOS transistor 114 is turned off. At this time, according to the value of the input data: with the signal x corresponding to the input data iTaking the case where the input is low level as an example. When the gate of MOS transistor 111 is at low level, MOS transistor 111 is turned on. At this time, the charge on the upper plate of the second capacitor 116 discharges to the upper plate of the first capacitor 117 through the path formed by MOS transistor 113, MOS transistor 112, and MOS transistor 111. By setting the bias voltage value, the conduction degree of MOS transistor 113 can be adjusted, and the magnitude of the discharge current of the second capacitor 116 can be controlled, so as to realize the establishment of a fixed voltage ΔV at the output end of the circuit within a unit time. If the signal corresponding to the input data is high level, the circuit does not inject charge into the output end. Thereafter, taking N working cycles of the above circuit as an example, according to the non-summation operation result of the input data, when the value is 1, it corresponds to a high-level signal, and when the value is 0, it corresponds to a low-level signal; if the non-summation operation result of the input data is 1, then a ΔV voltage is superimposed at the output end of the circuit, and if the non-summation operation result of the input data is 0, the voltage at the output end of the circuit remains unchanged. After N circuit working cycles, assuming the number of cycles with the non-summation operation result of 1 for the data is q, then the output voltage of the circuit is: V O = qΔV.

[0164] Embodiment 6

[0165] In this embodiment, the logical operation implemented by the logical operation circuit is the exclusive-NOR summation operation (exclusive-NOR logical operation summation), the logical operation circuit is an exclusive-NOR summation operation circuit, and the logical operation path is an exclusive-NOR summation operation path; the data to be logically operated includes: data signal x i and weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0166] The control unit is used to input the data signal x i and the weight signal w i into the exclusive-NOR summation operation path when performing the exclusive-NOR summation operation, and before each input of a group of x i and w i , control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the second capacitor to the voltage VDD, then control the first MOS transistor to turn on and the third MOS transistor to turn off, and input x i and w i into the exclusive-NOR summation operation path;

[0167] The exclusive-NOR summation operation path is used to connect the drain terminal of the first MOS transistor to the output terminal VO for voltage superposition at the output terminal VO when the levels of x i and w i are the same after receiving the input of x i and w i ; when the levels of x i and w iWhen the levels are different, the drain terminal of the first MOS transistor is not connected to the output terminal VO, and voltage superposition is no longer performed at the output terminal VO; among them, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO corresponds to the XNOR summation operation result The corresponding voltage value

[0168] Specifically, there are multiple implementation manners for the XNOR summation operation path

[0169] In an alternative implementation manner, the XNOR summation operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; among them, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i .

[0170] In another alternative implementation manner, the XNOR summation operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; among them, the source of the fourth MOS transistor, the drain of the fifth MOS transistor, the source of the sixth MOS transistor, and the drain of the seventh MOS transistor are connected; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to xi The inverted signal; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i The inverted signal.

[0171] It should be noted that the input positions of the above x i and w i can be interchanged, and there is no restriction here.

[0172] The following is a detailed description with an implementation manner: Specifically, as Figure 7 shown is a specific implementation manner of the exclusive-NOR summing operation circuit based on DAC disclosed in the present invention. In this implementation manner, the exclusive-NOR summing operation circuit 11 based on DAC includes: 8 MOS transistors (111, 112, 113, 114, 115, 116, 117, 118), two capacitors (119 and 1110), and two inverter logic circuits (1111 and 1112). Among them, MOS transistors 115, 116, and 117 are respectively the above-mentioned first to third MOS transistors, and MOS transistors 111, 113, 112, and 114 are respectively the above-mentioned fourth and seventh MOS transistors; MOS transistor 118 is the above-mentioned MOS transistor C. Specifically, the source of MOS transistor 111, the source of MOS transistor 112, and the drain of MOS transistor 115 are connected, the source of MOS transistor 113 is connected to the drain of MOS transistor 111, the source of MOS transistor 114 is connected to the drain of MOS transistor 112, the drain of MOS transistor 113, the drain of MOS transistor 114, the drain of MOS transistor 118, and the upper plate of the first capacitor 1110 are connected and this terminal is defined as the output terminal VO of the circuit. The source of MOS transistor 115 is connected to the drain of MOS transistor 116, the source of MOS transistor 116, the drain of MOS transistor 117, and the upper plate of the second capacitor 119 are connected, the source of MOS transistor 117 is connected to the lower plate of the second capacitor 119 and connected to the power supply VDD, the source of MOS transistor 118 is connected to the lower plate of the first capacitor 1110 and connected to the ground, the gate of MOS transistor 114 is connected to the output terminal of the first inverter 1111, the gate of MOS transistor 112 is connected to the output terminal of the second inverter 1112, the gate of MOS transistor 111 is connected to the weight signal w i , the gate of MOS transistor 113 is connected to the data signal x i , the input terminal of the first inverter 1111 is connected to the input data signal x i , the input terminal of the second inverter 1112 is connected to the input data signal w i, whose high level and low level correspond to the numerical values 1 and 0 respectively. The gate of MOS transistor 115 is connected to the clear signal CLR, the gate of MOS transistor 116 is connected to the bias voltage VBIAS, the gate of MOS transistor 117 is connected to the precharge signal CHARGE, and the gate of MOS transistor 118 is connected to the reset signal RESET.

[0173] Embodiment 7

[0174] In this embodiment, the logic operation implemented by the logic operation circuit is exclusive-or summation operation (exclusive-or logic operation summation), the logic operation circuit is an exclusive-or summation operation circuit, and the logic operation path is an exclusive-or summation operation path; the data to be subjected to the logic operation includes: data signal x i and weight signal w i ; i = 1, 2,..., N; N is the total number of data signals or weight signals;

[0175] The control unit is used to input the data signal x i and the weight signal w i into the exclusive-or summation operation path during the exclusive-or summation operation, and before each group of x i and w i is input, control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the second capacitor to the voltage VDD, then control the first MOS transistor to turn on and the third MOS transistor to turn off, and input x i and w i into the exclusive-or summation operation path;

[0176] The exclusive-or summation operation path is used to, after receiving the input of x i and w i , when the levels of x i and w i are different, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when the levels of x i and w i are the same, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to the bias voltage to ensure that the magnitude of each superposed voltage is the same; the final voltage value of the output terminal VO corresponds to the voltage value corresponding to the exclusive-or summation operation result corresponding voltage value.

[0177] Specifically, there are various implementation manners of the exclusive-or summation operation path:

[0178] In an alternative embodiment, the exclusive OR summation operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i .

[0179] In another alternative embodiment, the exclusive OR summation operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the sources of the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are connected; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor;

[0180] if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i .

[0181] It should be noted that the above xi and w i The input positions of and w can be interchanged, and there is no restriction here.

[0182] The following is a detailed description with an embodiment: Specifically, as Figure 8 shown is a specific embodiment of the XOR summation operation circuit based on DAC disclosed in the present invention. In this embodiment, the XOR summation operation circuit 11 based on DAC includes: eight MOS transistors (111, 112, 113, 114, 115, 116, 117, 118), two capacitors (119 and 1110), and two inverter logic circuits (1111 and 1112). Among them, MOS transistors 115, 116, and 117 are the first to third MOS transistors respectively, and MOS transistors 111, 113, 112, and 114 are the fourth and seventh MOS transistors respectively; MOS transistor 118 is the MOS transistor C. Specifically, the source of MOS transistor 111, the source of MOS transistor 112, and the drain of MOS transistor 115 are connected together, the source of MOS transistor 113 is connected to the drain of MOS transistor 111, the source of MOS transistor 114 is connected to the drain of MOS transistor 112, the drains of MOS transistors 113, 114, 118, and the upper plate of the first capacitor 1110 are connected together and this terminal is defined as the output terminal VO of the circuit. The source of MOS transistor 115 is connected to the drain of MOS transistor 116, the source of MOS transistor 116, the drain of MOS transistor 117, and the upper plate of the second capacitor 119 are connected together, the source of MOS transistor 117 is connected to the lower plate of the second capacitor 119 and connected to the power supply VDD, the source of MOS transistor 118 is connected to the lower plate of the first capacitor 1110 and connected to the ground, the gate of MOS transistor 113 is connected to the output terminal of the first inverter 1111, the gate of MOS transistor 112 is connected to the output terminal of the second inverter 1112, the gate of MOS transistor 111 is connected to the weight signal w i , the gate of MOS transistor 114 is connected to the data signal x i , the input terminal of the first inverter 1111 is connected to the input data signal x i , the input terminal of the second inverter 1112 is connected to the input data signal w i , and its high level and low level correspond to the numerical values 1 and 0. The gate of MOS transistor 115 is connected to the clear signal CLR, the gate of MOS transistor 116 is connected to the bias voltage VBIAS, the gate of MOS transistor 117 is connected to the precharge signal CHARGE, and the gate of MOS transistor 118 is connected to the reset signal RESET. Specifically elaborate Figure 7 and Figure 8 the circuit working principle.

[0183] Specifically elaborate Figure 7 and Figure 8 the circuit working principle:

[0184] As Figure 7 and Figure 8 shown, when the RESET signal is high, the CLR signal is high, and the CHARGE signal is high, the MOS transistor 118 conducts to ground, the circuit output terminal is reset to low level, the gate of the MOS transistor 115 is high level, the MOS transistor 115 is turned off, and the circuit stops working. When the RESET signal is low, the MOS transistor 118 is turned off, and the circuit is in the working state. At this time, when the CHARGE signal is low and the CLR signal is high, the circuit works in the pre-charge state, the MOS transistor 115 is turned off, the MOS transistor 117 conducts, and the upper plate of the second capacitor 119 is charged to the VDD level. When the CHARGE signal is high and the CLR signal is low, the MOS transistor 115 conducts, the MOS transistor 117 is turned off, and at this time:

[0185] For the circuit that implements the exclusive-NOR summation operation Figure 7 At this time, according to the value of the input data, the first inverter 1111 and the second inverter 1112 output inverted signals; taking the input data signal and the weight signal both being high level as an example. The output of the first inverter 1111 is low level, the output terminal of the second inverter 1112 is low level, the gate of the MOS transistor 111 is high level, the gate of the MOS transistor 113 is high level, the gate of the MOS transistor 112 is low level, the gate of the MOS transistor 114 is low level, the MOS transistors 111 and 113 are turned off, and the MOS transistors 112 and 114 conduct. At this time, the charge on the upper plate of the second capacitor 119 discharges to the upper plate of the first capacitor 1110 through the path formed by the MOS transistor 116, the MOS transistor 115, the MOS transistor 112, and the MOS transistor 114. By setting the bias voltage value, the conduction degree of the MOS transistor 116 can be adjusted, the magnitude of the discharge current of the second capacitor 119 can be controlled, and thus a fixed-size voltage ΔV can be established at the circuit output terminal within a unit time. Similarly, if the signal x corresponding to the input data i is low level, and w i is low level, then the circuit injects charge into the output terminal; if the input data and the weight signal are different, the circuit does not inject charge into the output terminal. After that, taking N working cycles of the above circuit as an example, according to the exclusive-NOR summation operation result of the input data, when the value is 1, it corresponds to a high-level signal, and when the value is 0, it corresponds to a low-level signal; if the exclusive-NOR summation operation result of the input data is 1, then a ΔV voltage is superimposed at the output terminal of the circuit, and if the exclusive-NOR summation operation result of the input data is 0, the voltage at the output terminal of the circuit remains unchanged. After N circuit working cycles, assuming the number of cycles with the exclusive-NOR summation operation result of 1 for the data is q, then the output voltage of the circuit is: V O = qΔV.

[0186] For the circuit that implements the exclusive-OR summation operation Figure 8Circuit. At this time, according to the value of the input data, the first inverter 1111 and the second inverter 1112 output inverted signals. Taking the input data signal as high level and the input weight signal as low level as an example. The output of the first inverter 1111 is low level, the output terminal of the second inverter 1112 is high level, the gate of MOS transistor 111 is low level, the gate of MOS transistor 113 is low level, the gate of MOS transistor 112 is high level, the gate of MOS transistor 114 is high level, MOS transistors 111 and 113 are turned on, and MOS transistors 112 and 114 are turned off. At this time, the charge on the upper plate of the second capacitor 119 discharges to the upper plate of the first capacitor 1110 through the path formed by MOS transistors 116, 115, 111 and 113. By setting the bias voltage value, the conduction degree of MOS transistor 116 can be adjusted to control the magnitude of the discharge current of the second capacitor 119, and then a fixed-size voltage ΔV can be established at the output terminal of the circuit within a unit time. Similarly, if the signal x corresponding to the input data i is low level, and w i is high level, then the circuit injects charge into the output terminal; if the input data and the weight signal are the same, then the circuit does not inject charge into the output terminal. After that, taking N working cycles of the above circuit as an example, according to the exclusive OR summation operation result of the input data, a high level signal corresponds to a value of 1, and a low level signal corresponds to a value of 0; if the exclusive OR summation operation result of the input data is 1, then a ΔV voltage is superimposed at the output terminal of the circuit, and if the exclusive OR summation operation result of the input data is 0, then the voltage at the output terminal of the circuit remains unchanged. After N working cycles of the circuit, assuming the number of cycles with the result of the exclusive NOR summation operation of the data being 1 is q, then the output voltage of the circuit is: V O = qΔV.

[0187] In a second aspect, the present invention provides a mixed-signal convolution operation circuit, which is a convolution operation circuit based on DAC (denoted as CICU circuit) for realizing the multiply-accumulate operation (convolution operation) of input data and weights, including: a first MOS transistor, a second MOS transistor, a third MOS transistor, a first capacitor, a second capacitor, a third capacitor, an arithmetic operation path, and a control unit;

[0188] One end of the first capacitor serves as the positive-phase output terminal VP of the convolution operation circuit, and the other end is grounded; one end of the second capacitor serves as the inverting output terminal VN of the convolution operation circuit, and the other end is grounded; the source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the second MOS transistor, the drain of the third MOS transistor, and one end of the third capacitor are connected, and the source of the third MOS transistor is connected to the other end of the third capacitor and is connected to the power supply voltage VDD;

[0189] The control unit is used for performing binary convolution operation, and the data signal x i and the weight signal wi is input into the arithmetic operation path, and for each input set of x i and w i when, the first MOS transistor is controlled to turn off and the third MOS transistor is controlled to turn on to charge the third capacitor to the voltage VDD, and then the first MOS transistor is controlled to turn on and the third MOS transistor is controlled to turn off, and charge injection is performed according to the input conditions of x i and w i input conditions; i = 1, 2,..., N; N is the length of the data to be convolved;

[0190] The arithmetic operation path is used to, after receiving the inputs of x i and w i when the levels of x i and w i are the same, connect the drain terminal of the first MOS transistor to the positive-phase output terminal VP to perform voltage superposition at the positive-phase output terminal VP; when the levels of x i and w i are opposite, connect the drain terminal of the first MOS transistor to the inverting output terminal VN to perform voltage superposition at the inverting output terminal VN; wherein, the gate of the second MOS transistor is connected to a preset bias voltage to ensure that the magnitude of the voltage superimposed each time is the same;

[0191] The final voltage difference between the positive-phase output terminal VP and the inverting output terminal VN is the voltage value corresponding to the convolution operation result corresponding thereto;

[0192] wherein, w i is a high-level signal or a low-level signal; x i is a high-level signal or a low-level signal; the high-level signal corresponds to the value 1, and the low-level signal corresponds to the value -1.

[0193] The specific operation process is as follows: when the multiplication result of the two input values is 1, the convolution operation circuit based on the DAC selects the positive-phase charge injection path from the third capacitor to the first capacitor, and after completing one charge injection, a voltage value of a certain magnitude is superimposed at the positive-phase output terminal VP; when the multiplication result of the two input values is -1, the convolution operation circuit based on the DAC selects the inverting charge injection path from the third capacitor to the second capacitor, and after completing one charge injection, a voltage value of a certain magnitude is superimposed at the inverting output terminal VN. Taking the above working process as one cycle, the convolution operation circuit based on the DAC can, according to the product result of the input values, establish an analog voltage value related to the multiply-accumulate operation result at the differential output terminal through a step-by-step injection process.

[0194] Preferably, the control unit is further configured to input a clearing signal to the gate of the first MOS transistor to control the switching state of the first MOS transistor, and input a pre-charging signal to the gate of the third MOS transistor to control the switching state of the third MOS transistor.

[0195] Preferably, the above convolution operation circuit further includes: MOS transistor A and MOS transistor B; wherein, the drain of MOS transistor A is connected to the positive-phase output terminal VP, and the source is grounded; the drain of MOS transistor B is connected to the inverting output terminal VN, and the source is grounded;

[0196] The control unit is further configured to perform a reset operation on the convolution operation circuit before performing the binary convolution operation: control MOS transistor A and MOS transistor B to conduct, and the first MOS transistor and the third MOS transistor to turn off, so as to reset the positive-phase output terminal VP and the inverting output terminal VN to ground; when performing the convolution operation, control MOS transistor A and MOS transistor B to be in the off state.

[0197] In an alternative embodiment, the arithmetic operation path includes: the fourth to eleventh MOS transistors; wherein, the sources of the fourth MOS transistor, the fifth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor; the drain of the fifth MOS transistor and the source of the seventh MOS transistor are connected; the drain of the eighth MOS transistor and the source of the tenth MOS transistor are connected; the drain of the ninth MOS transistor and the source of the eleventh MOS transistor are connected; the drains of the sixth MOS transistor and the tenth MOS transistor are commonly connected to the positive-phase output terminal VP; the drains of the seventh MOS transistor and the eleventh MOS transistor are commonly connected to the inverting output terminal VN; the gates of the fourth MOS transistor and the fifth MOS transistor are connected to w i ; the gates of the sixth MOS transistor and the eleventh MOS transistor are connected to x i ; the gates of the seventh MOS transistor and the tenth MOS transistor are connected to the inverted signal of x i ; the gates of the eighth MOS transistor and the ninth MOS transistor are connected to the inverted signal of w i of.

[0198] In another alternative embodiment, the arithmetic operation path includes: the fourth to eleventh MOS transistors; wherein, the sources of the fourth MOS transistor, the fifth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor, the source of the sixth MOS transistor, the drain of the eighth MOS transistor, and the source of the tenth MOS transistor are connected; the drain of the fifth MOS transistor, the source of the seventh MOS transistor, the drain of the ninth MOS transistor, and the source of the eleventh MOS transistor are connected; the drains of the sixth MOS transistor and the tenth MOS transistor are commonly connected to the positive-phase output terminal VP; the drains of the seventh MOS transistor and the eleventh MOS transistor are commonly connected to the inverting output terminal VN; the gates of the fourth MOS transistor and the fifth MOS transistor are connected to w i ; the gates of the seventh MOS transistor and the tenth MOS transistor are connected to x i; The gates of the sixth MOS transistor and the eleventh MOS transistor are connected to the inverted signal of x i ; The gates of the eighth MOS transistor and the ninth MOS transistor are connected to the inverted signal of w i .

[0199] The following is a detailed description in conjunction with specific embodiments:

[0200] Embodiment 8

[0201] As Figure 9 shown, it is a convolution operation circuit based on DAC disclosed in this embodiment. In this embodiment, the convolution operation circuit 11 based on DAC includes: 13 MOS transistors (111, 112, 113, 114, 115, 116, 117, 118, 119, 1110, 1111, 1112, and 1113), three capacitors (1114, 1115, and 1116), and two inverter logic circuits (1117 and 1118). Among them, MOS transistors 119, 1110, and 1111 are the first to third MOS transistors respectively, and MOS transistors 111, 112, 113, 114, 115, 116, 117, 118 are the fourth to eleventh MOS transistors respectively; MOS transistors 1112 and 1113 are MOS transistor A and MOS transistor B respectively. Specifically, the source of MOS transistor 111, the source of MOS transistor 112, the source of MOS transistor 115, the source of MOS transistor 116, and the drain of MOS transistor 119 are connected. The drain of MOS transistor 111 is connected to the source of MOS transistor 113, the drain of MOS transistor 112 is connected to the source of MOS transistor 114, the drain of MOS transistor 115 is connected to the source of MOS transistor 117, the drain of MOS transistor 116 is connected to the source of MOS transistor 118, the drains of MOS transistor 113, MOS transistor 117, MOS transistor 1112, and the upper plate of the first capacitor 1114 are connected and defined as the positive phase output terminal VP of CICU. The drains of the fourth MOS transistor 114, the eighth MOS transistor 118, MOS transistor 1113, and the upper plate of the second capacitor 1115 are connected and defined as the inverted phase output terminal VN of CICU. The source of MOS transistor 119 is connected to the drain of MOS transistor 1110. The source of MOS transistor 1110, the drain of MOS transistor 1111, and the upper plate of the third capacitor 1116 are connected. The source of MOS transistor 1111 is connected to the lower plate of the third capacitor 1116 and connected to the power supply VDD. The source of MOS transistor 1112 is connected to the lower plate of the first capacitor 1114 and connected to the ground. The source of MOS transistor 1113 is connected to the lower plate of the third capacitor 1115 and connected to the ground. The gates of MOS transistor 113 and MOS transistor 118 are connected to the input data signal x i, whose high level and low level correspond to the values 1 and -1 respectively, the gates of MOS transistor 111 and MOS transistor 112 are connected to the input weight signal w i , whose high level and low level correspond to the values 1 and -1 respectively, the gates of MOS transistor 114, MOS transistor 117 and the output terminal of the first inverter 1117 are connected together, the gates of MOS transistor 115, MOS transistor 116 and the output terminal of the second inverter 1118 are connected together, and the input terminal of the first inverter 1117 is connected to the input data signal x i , the input terminal of the second inverter 1118 is connected to the input weight signal w i . The gate of MOS transistor 119 is connected to the clear signal CLR, the gate of MOS transistor 1110 is connected to the bias voltage VBIAS, the gate of MOS transistor 1111 is connected to the precharge signal CHARGE, and the gates of MOS transistor 1112 and MOS transistor 1113 are connected to the reset signal RESET.

[0202] Specifically expound the circuit working principle of CICU 11. As Figure 9 shown, when the RESET signal is at high level, the CLR signal is at high level, and the CHARGE signal is at high level, MOS transistor 1112 and MOS transistor 1113 are turned on to ground, the positive and negative output terminals of CICU 11 are reset to low level, the gate of MOS transistor 119 is at high level, MOS transistor 119 is turned off, and the CICU 11 circuit stops working. When the RESET signal is at low level, MOS transistor 1112 and MOS transistor 1113 are turned off, and the CICU 11 circuit is in the working state. At this time, when the CHARGE signal is at low level and the CLR signal is at high level, CICU 11 works in the precharge state, MOS transistor 119 is turned off, MOS transistor 1111 is turned on, and the upper plate of the third capacitor 1116 is charged to the VDD level.

[0203] When the CHARGE signal is at high level and the CLR signal is at low level, MOS transistor 119 is turned on, MOS transistor 1111 is turned off. At this time, according to the values of the input data and the input weight, the inverter circuit 1117 and the second inverter 1118 output inverted signals; taking the signal x i corresponding to the input data and the signal w i corresponding to the input weight as an example: when the levels of x i and w i are the same: when both x i and w iWhen both are at high level, the output terminals of the first inverter 1117 and the second inverter 1118 are at low level, the gates of the MOS transistor 115 and the MOS transistor 117 are at low level, and the MOS transistor 115 and the MOS transistor 117 are turned on. At this time, the charge on the upper plate of the third capacitor 1116 discharges to the upper plate of the first capacitor 1114 through the path formed by the MOS transistor 1110, the MOS transistor 119, the MOS transistor 115 and the MOS transistor 117. By setting the bias voltage value, the conduction degree of the MOS transistor 1110 can be adjusted, the magnitude of the discharge current of the third capacitor 1116 can be controlled, and thus a fixed - sized voltage ΔV can be established at the positive - phase output terminal of the CICU 11 circuit within a unit time. Similarly, when the input data x i and the weight value w i are at different levels, a fixed - sized voltage ΔV is established at the inverting output terminal of the CICU 11 circuit. Thereafter, taking N working cycles of the above - mentioned circuit as an example, according to the numerical product of the input data and the weight, when the numerical value is 1, it corresponds to a high - level signal, and when the numerical value is - 1, it corresponds to a low - level signal; if the numerical product of the input data and the weight is 1, that is, the data signal x i and the weight signal w i are at the same level, then a voltage ΔV is superimposed on the positive - phase output terminal of the CICU 11 circuit. If the numerical product of the input data and the weight is - 1, that is, the data signal x i and the weight signal w i are at opposite levels, then a voltage ΔV is superimposed on the inverting output terminal of the CICU 11 circuit. After N circuit working cycles, assuming the number of cycles when the product of the data and the weight is 1 is q, the output voltage at the positive - phase end of the CICU circuit is: V P = qΔV; the output voltage at the inverting end of the CICU 11 circuit is: V N =(N - q)ΔV; the differential output voltage of the CICU 11 circuit is: The differential voltage value corresponds to the result of the multiply - accumulate operation of the input data x = [x i , x2, …, x N and the weight w = [w i , w2, …, w N .

[0204] It should be noted that the magnitude of the voltage ΔV can be adjusted not only by adjusting the magnitude of the preset bias voltage, but also by adjusting the pulse width of the CLR signal and / or the CHARGE signal. In addition, it can also be adjusted by adjusting the capacitance of the first capacitor and / or the second capacitor.

[0205] Embodiment 9

[0206] As Figure 10Shown is the DAC-based convolution operation circuit disclosed in this embodiment. In this embodiment, the DAC-based convolution operation circuit 11 includes: 13 MOS transistors (111, 112, 113, 114, 115, 116, 117, 118, 119, 1110, 1111, 1112, and 1113), three capacitors (1114, 1115, and 1116), and two inverter logic circuits (1117 and 1118). Among them, MOS transistors 119, 1110, and 1111 are the first to third MOS transistors respectively, and MOS transistors 111, 112, 113, 114, 115, 116, 117, and 118 are the fourth to eleventh MOS transistors respectively; MOS transistors 1112 and 1113 are MOS transistor A and MOS transistor B respectively. Specifically, the source electrodes of MOS transistor 111, MOS transistor 112, MOS transistor 115, MOS transistor 116, and the drain electrode of MOS transistor 119 are connected; the drain electrode of MOS transistor 111, the source electrode of MOS transistor 113, the drain electrode of MOS transistor 115, and the source electrode of MOS transistor 117 are connected; the drain electrode of MOS transistor 112, the source electrode of MOS transistor 114, the drain electrode of MOS transistor 116, and the source electrode of MOS transistor 118 are connected; the drain electrodes of MOS transistor 113, MOS transistor 117, MOS transistor 1112, and the upper plate of the first capacitor 1114 are connected and this terminal is defined as the positive-phase output terminal VP of CICU, and the drain electrodes of MOS transistor 114, MOS transistor 118, MOS transistor 1113, and the upper plate of the second capacitor 1115 are connected and this terminal is defined as the negative-phase output terminal VN of CICU. The source electrode of MOS transistor 119 is connected to the drain electrode of MOS transistor 1110, the source electrode of MOS transistor 1110, the drain electrode of MOS transistor 1111, and the upper plate of the third capacitor 1116 are connected, the source electrode of MOS transistor 1111 is connected to the lower plate of the third capacitor 1116 and connected to the power supply VDD, the source electrode of MOS transistor 1112 is connected to the lower plate of the first capacitor 1114 and connected to the ground, the source electrode of MOS transistor 1113 is connected to the lower plate of the third capacitor 1115 and connected to the ground, the gate electrodes of MOS transistor 114 and MOS transistor 117 are connected to the input data signal x i , whose high level and low level correspond to the values 1 and -1, and the gate electrodes of MOS transistor 111 and MOS transistor 112 are connected to the input weight signal w i , whose high level and low level correspond to the values 1 and -1, and the gate electrodes of MOS transistor 113, MOS transistor 118, and the output terminal of the first inverter 1117 are connected, the gate electrodes of MOS transistor 115, MOS transistor 116, and the output terminal of the second inverter 1118 are connected, and the input terminal of the first inverter 1117 is connected to the input data signal x i , and the input terminal of the second inverter 1118 is connected to the input weight signal w i. The gate of MOS transistor 119 is connected to the clear signal CLR, the gate of MOS transistor 1110 is connected to the bias voltage VBIAS, the gate of MOS transistor 1111 is connected to the precharge signal CHARGE, and the gates of MOS transistor 1112 and MOS transistor 1113 are connected to the reset signal RESET.

[0207] Specifically describe the circuit working principle of CICU 11. As Figure 10 shown, when the RESET signal is high level, the CLR signal is high level, and the CHARGE signal is high level, MOS transistors 1112 and 1113 conduct to ground, and the positive and negative output terminals of CICU 11 are reset to low level. The gate of MOS transistor 119 is at high level, and MOS transistor 119 is turned off, and the CICU 11 circuit stops working. When the RESET signal is low level, MOS transistors 1112 and 1113 are turned off, and the CICU 11 circuit is in the working state. At this time, when the CHARGE signal is low level and the CLR signal is high level, CICU 11 works in the precharge state, MOS transistor 119 is turned off, and MOS transistor 1111 conducts, and the upper plate of the third capacitor 1116 is charged to the VDD level.

[0208] When the CHARGE signal is high level and the CLR signal is low level, MOS transistor 119 conducts and MOS transistor 1111 is turned off. At this time, according to the values of the input data and the input weight, the inverter circuit 1117 and the second inverter 1118 output inverted signals; taking the signals x i corresponding to the input data and the signal w i corresponding to the input weight as an example: when x i and w i are both at low level, the gates of MOS transistors 111 and 117 are both at low level, and MOS transistors 111 and 117 conduct. At this time, the charge on the upper plate of the third capacitor 1116 discharges to the upper plate of the first capacitor 1114 through the path formed by MOS transistors 1110, 119, 111, and 117; when x i and w iWhen both are at high level, the output terminals of the first inverter 1117 and the second inverter 1118 are at low level, the gates of the MOS transistor 115 and the MOS transistor 113 are at low level, and the MOS transistor 115 and the MOS transistor 113 are turned on. At this time, the charge on the upper plate of the third capacitor 1116 discharges to the upper plate of the first capacitor 1114 through the path formed by the MOS transistor 1110, the MOS transistor 119, the MOS transistor 115 and the MOS transistor 113. By setting the bias voltage value, the conduction degree of the MOS transistor 1110 can be adjusted, the magnitude of the discharge current of the third capacitor 1116 can be controlled, and then a fixed-size voltage ΔV can be established at the positive-phase output terminal of the CICU 11 circuit within a unit time. Similarly, when the input data x i and the weight value w i are at different levels, a fixed-size voltage ΔV is established at the inverting output terminal of the CICU 11 circuit. Thereafter, taking N working cycles of the above circuit as an example, according to the numerical product of the input data and the weight, when the numerical value is 1, it corresponds to a high-level signal, and when the numerical value is -1, it corresponds to a low-level signal; if the numerical product of the input data and the weight is 1, that is, the data signal x i and the weight signal w i are at the same level, then a ΔV voltage is superimposed at the positive-phase output terminal of the CICU 11 circuit. If the numerical product of the input data and the weight is -1, that is, the data signal x i and the weight signal w i are at opposite levels, then a ΔV voltage is superimposed at the inverting output terminal of the CICU 11 circuit. After N circuit working cycles, assuming the number of cycles when the product of the data and the weight is 1 is q, then the output voltage at the positive phase end of the CICU circuit is: V P =qΔV; the output voltage at the inverting end of the CICU 11 circuit is: V N =(N - q)ΔV; the differential output voltage of the CICU 11 circuit is: The differential voltage value corresponds to the result of the multiply-accumulate operation of the input data x = [x i , x2,..., x N and the weight w = [w i , w2,..., w N .

[0209] It should be noted that the magnitude of the voltage ΔV can be adjusted not only by adjusting the magnitude of the preset bias voltage, but also by adjusting the pulse width of the CLR signal and / or the CHARGE signal. In addition, it can also be adjusted by adjusting the capacitance of the first capacitor and / or the second capacitor.

[0210] In a third aspect, the present invention provides a switched-capacitor arithmetic circuit based on a DAC (denoted as the CISC-OC circuit), including: M charge injection calculation units, M first connection capacitors, and M second connection capacitors; wherein, the charge injection calculation unit is the logic arithmetic circuit provided in the first aspect of the present invention or the convolution arithmetic circuit based on a DAC (CICU circuit) provided in the second aspect of the present invention; the related technical solutions are the same as those in the first and second aspects and will not be elaborated here;

[0211] 1), when the charge injection calculation unit is the convolution arithmetic circuit based on a DAC provided in the second aspect of the present invention:

[0212] The positive-phase output terminals VP of the M charge injection calculation units are respectively and correspondingly connected to one ends of the M first connection capacitors, and the other ends of the M first connection capacitors are connected together and used as the positive-phase output terminal VOUTP of the switched-capacitor arithmetic circuit;

[0213] The negative-phase output terminals VN of the M charge injection calculation units are respectively and correspondingly connected to one ends of the M second connection capacitors, and the other ends of the M second connection capacitors are connected together and used as the negative-phase output terminal VOUTN of the switched-capacitor arithmetic circuit;

[0214] The outputs of the positive-phase output terminals VP of the M charge injection calculation units are superimposed at the positive-phase output terminal VOUTP through the corresponding first connection capacitors;

[0215] The outputs of the negative-phase output terminals VN of the M charge injection calculation units are superimposed at the negative-phase output terminal VOUTN through the corresponding second connection capacitors;

[0216] A convolution operation is divided into M groups of sub-convolution operations; one charge injection calculation unit is used to implement one sub-convolution operation; the final voltage difference between the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN is the voltage value corresponding to the required convolution operation result.

[0217] Preferably, the above-mentioned switched-capacitor arithmetic circuit based on a DAC further includes: a reset circuit respectively connected to the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN.

[0218] In an alternative embodiment, when calculating the convolution operation of input data and weights, the CISC-OC circuit includes K groups of CICU circuits, two groups of unit-weight capacitance arrays, and two groups of common-mode reset circuits. For the multiply-accumulate operation of N groups of input data and weights, each of the K groups of CICU circuits is time-division multiplexed M times. According to the product result of the input data and weights, through successive charge injection, a voltage value related to the multiply-accumulate result of the input data and weights is established on the lower plates of the unit-weight capacitance array. After the charge redistribution process on the plates of the unit-weight capacitance array, an analog voltage value corresponding to the multiply-accumulate operation result of N groups of input data and weights can be established at the differential output terminal.

[0219] It should be noted that the CISC-OC circuit is applicable to the scenario when the length N of the data to be convolved takes a relatively large value. By splitting the convolution operation of the data to be convolved into multiple groups of sub-convolution operations, the operation efficiency can be improved.

[0220] Specifically, as Figure 11 shown in the first specific embodiment of the CISC-OC circuit provided by the present invention. In this embodiment, the CISC-OC 1 circuit includes sixteen groups of CICU 11, two groups of unit-weight capacitance arrays 12, two groups of common-mode reset circuits 13, and a PTAT voltage reference source circuit 14. Among them, each group of unit-weight capacitance arrays 12 is composed of sixteen capacitors with the same capacitance value. The upper plates of the first group of unit-weight capacitance arrays are connected together and this terminal is defined as the positive output terminal VOUTP of the CISC-OC. The lower plates of the sixteen capacitors in the first group of unit-weight capacitance arrays are respectively connected to the positive output terminals of the sixteen groups of CICU 11. The upper plates of the second group of unit-weight capacitance arrays are connected together and this terminal is defined as the negative output terminal VOUTN of the CISC-OC. The lower plates of the sixteen capacitors in the second group of unit-weight capacitance arrays are respectively connected to the negative output terminals of the sixteen groups of CICU 11. The first group of common-mode reset circuit 131 is connected to the positive output terminal VOUTP of the CISC-OC 1 circuit, the second group of common-mode reset circuit 132 is connected to the negative output terminal VOUTN of the CISC-OC 1 circuit, and the PTAT voltage reference 14 is connected to the VBIAS terminal of the sixteen groups of CICU 11 circuits.

[0221] As Figure 12 shown is the working timing diagram of the CISC-OC 1 circuit. Its working process includes a reset stage and an operation stage. The following specifically elaborates the working principle of the CISC-OC 1 circuit.

[0222] First is the reset stage: When the common-mode reset circuit 13 is turned on, the RESET signal is at a high level, the CHARGE signal is at a high level, and the CLR signal is at a high level, the CICU 11 circuit stops working, and its inverting and non-inverting output terminals are reset to a low-level voltage, and the inverting and non-inverting output terminals of the CISC-OC 1 circuit are reset to the common-mode voltage.

[0223] Then is the operation stage. In this stage, it is necessary to calculate the multiply-accumulate result of the input data and weights. When the common-mode reset circuit 13 stops working, taking 64 working cycles of the CLR signal and the CHARGE signal as an example, 64 groups of data signals and weight signals are sequentially input to each CICU 11 circuit. Specifically, the i-th group of data signal and weight signal input to the n-th CICU 11 circuit are x n,i and w n,i , where n = 1 to 16, i = 1 to 64, the high and low levels of the signal correspond to the values 1 and -1. If the levels of the data signal and the weight signal are in the same direction, that is, the product of the corresponding data and weight is 1, then a ΔV voltage is superimposed on the non-inverting output terminal of the CICU 11 circuit. If the levels of the data signal and the weight signal are in the opposite direction, that is, the product of the corresponding data and weight is -1, then a ΔV voltage is superimposed on the inverting output terminal of the CICU 11 circuit. Specifically, assuming that for the first group of CICU 11 circuits, the number of cycles with a product of data and weight equal to 1 is q, then the output voltage of the non-inverting terminal of the CICU 11 circuit is: V P = qΔV; the output voltage of the inverting terminal of the CICU 11 circuit is: V N = (64 - q)ΔV; the differential voltage output of the CICU 11 circuit is: The differential voltage value corresponds to the multiply-accumulate operation result of the input data and weights. Furthermore, through the charge redistribution process of the upper plate of the unit capacitor array, a voltage difference of is established. Similarly, for 16 groups of CICU 11 circuits, within 64 working cycles, a voltage difference of is established on the plates of the unit capacitor array, that is, the CISC-OC 1 circuit establishes an analog voltage value related to the multiply-accumulate sum of 1024 groups of input data and weights on the plates of the unit capacitor array within 64 working cycles. Considering that within a certain period, under the fixed bias voltage VBIAS with a certain value, the discharge amount of the CICU 11 circuit is positively correlated with the temperature, a voltage reference source 14 with a certain positive temperature coefficient is designed and implemented in the CISC-OC 1 circuit for compensation to ensure the high-temperature robustness of ΔV during each discharge process.

[0224] 2) When the charge injection calculation unit is the logic operation circuit provided in the first aspect of the present invention:

[0225] The output terminals VO of M charge injection calculation units are respectively and correspondingly connected to one ends of M connection capacitors, and the other ends of the M connection capacitors are connected together and used as the output terminal VOUT of the switched-capacitor operation circuit;

[0226] The outputs of the output terminals VO of the M charge injection calculation units are superimposed at the output terminal VOUT via the corresponding connection capacitors;

[0227] A logic operation is divided into M groups of sub-logic operations; a charge injection calculation unit is used to implement a sub-logic operation; the output of the output terminal VOUT is the voltage value corresponding to the required logic operation result.

[0228] Preferably, in an alternative embodiment, the switched-capacitor operation circuit further includes: a reset circuit connected to the output terminal VOUT.

[0229] In a fourth aspect, the present invention provides an electronic chip, including the logic operation circuit provided in the first aspect of the present invention, or the convolution operation circuit provided in the second aspect of the present invention, or the switched-capacitor operation circuit provided in the third aspect of the present invention. The related technical solutions are the same as those in the first, second, and third aspects of the present invention and will not be elaborated here.

[0230] In summary, the present invention discloses a mixed-signal operation circuit based on a DAC array. For the operation circuit part, the first capacitor is used to determine the output terminal of the logic operation circuit, the second capacitor is used to provide a certain voltage, and the operation path selects the charge path from the second capacitor to the first capacitor based on each input data signal to superimpose the voltage values at the output terminal; time division multiplexing is achieved through a step-by-step injection method, so as to establish an analog voltage value related to the logic operation result at the output terminal. Only two capacitors are used to implement the logic operation, and there is no need to construct a unit-weight capacitor array with the same size as the number of logic operations, which greatly reduces the area overhead of the capacitors. It can reduce the area overhead of the operation circuit while ensuring the working speed and accuracy, and improve the operation energy efficiency.

[0231] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A mixed-signal logic operation circuit, characterized in that, Comprising: A first MOS transistor, a second MOS transistor, a third MOS transistor, a first capacitor, a second capacitor, a logic operation path, and a control unit; one end of the first capacitor serves as the output terminal VO of the logic operation circuit, and the other end is grounded; the source electrode of the first MOS transistor is connected to the drain electrode of the second MOS transistor, the source electrode of the second MOS transistor, the drain electrode of the third MOS transistor, and one end of the second capacitor are connected, and the source electrode of the third MOS transistor is connected to the other end of the second capacitor and is connected to the power supply voltage VDD; The control unit is configured to input data to be subjected to a logic operation into the logic operation path when performing a logic operation; and before each input, control the first MOS transistor to be turned off and the third MOS transistor to be turned on to charge the second capacitor to the voltage VDD, and then control the first MOS transistor to be turned on and the third MOS transistor to be turned off; The logic operation path is configured to control the connection state between the drain terminal of the first MOS transistor and the output terminal VO based on the level state of the input data.

2. The logic operation circuit according to claim 1, wherein When the logic operation implemented by the logic operation circuit is an AND summation operation: The data to be logically operated includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; The control unit inputs a set of x each time i and w i into the logic operation path; The logic operation path is used to, after receiving the inputs of x i and w i , when both x i and w i are at high level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w i are not both at high level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage for each superposition is the same; the final voltage value of the output terminal VO corresponds to the voltage value corresponding to the summation operation result ; When the logic operation implemented by the logic operation circuit is an OR summation operation: The data to be logically operated includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; The control unit inputs a set of x each time i and w i into the logical operation path; The logic operation path is used to, after receiving the inputs of x i and w i , when either x i or w i is at a high level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a high level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superimposed voltage is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the OR or summation operation result corresponding thereto; When the logic operation implemented by the logic operation circuit is a NOT summation operation: The data to be subjected to logical operations includes: data signal x i ; i = 1, 2, …, N; N is the total number of data signals; The control unit inputs one x each time i into the logic operation path; The logic operation path is used to, after receiving the input of x i , when x i is at a low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i is not at a low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO, and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the result of the non-summation operation corresponding to When the logic operation implemented by the logic operation circuit is a NAND summation operation: The data to be subjected to logical operations includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; The control unit inputs a set of x i and w i into the logic operation path each time; The logic operation path is used to, after receiving the inputs of x i and w i , when one of x i and w i is at a low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when neither x i nor w i is at a low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO corresponds to the voltage value corresponding to the NAND summation operation result ; When the logic operation implemented by the logic operation circuit is a NOR summation operation: The data to be subjected to logical operations includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; The control unit inputs a set of x each time i and w i into the logic operation path; The logic operation path is used to, after receiving the inputs of x i and w i , when both x i and w i are at low level, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when x i and w i are not both at low level, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superposed voltage is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the NOR summation operation result corresponding thereto; When the logic operation implemented by the logic operation circuit is an XNOR summation operation: The data to be subjected to logical operations includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; Each time the control unit inputs a set of x i and w i into the logic operation path; The logical operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are the same, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when the levels of x i and w i are different, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of each superimposed voltage is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the result of the exclusive-NOR summation operation corresponding to; When the logic operation implemented by the logic operation circuit is an XOR summation operation: The data to be logically operated includes: data signal x i and weight signal w i ; i = 1, 2, …, N; N is the total number of data signals or weight signals; Each time the control unit inputs a set of x i and w i into the logic operation path; The logic operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are different, connect the drain terminal of the first MOS transistor to the output terminal VO to perform voltage superposition at the output terminal VO; when the levels of x i and w i are the same, do not connect the drain terminal of the first MOS transistor to the output terminal VO and no longer perform voltage superposition at the output terminal VO; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage value of the output terminal VO is the voltage value corresponding to the result of the exclusive OR summation operation corresponding to the voltage value.

3. The logic operation circuit according to claim 2, wherein When the logic operation implemented by the logic operation circuit is an AND summation operation: the logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the drain of the fourth MOS transistor is connected to the output terminal VO, and the source of the fifth MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i ; When the logic operation implemented by the logic operation circuit is an OR summation operation: The logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; the drains of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the output terminal VO, and the sources of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to w i ; When the logic operation implemented by the logic operation circuit is a non-summation operation: the logic operation path includes: a fourth MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO, and the source is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; When the logic operation implemented by the logic operation circuit is a NAND summation operation: the logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source electrodes of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the drain electrode of the first MOS transistor; the drain electrodes of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the output terminal VO; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; When the logic operation implemented by the logic operation circuit is a NOR summation operation: The logic operation path includes: a fourth MOS transistor and a fifth MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; the drain of the fourth MOS transistor is connected to the output terminal VO; the source of the fifth MOS transistor is connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; When the logic operation implemented by the logic operation circuit is an exclusive-NOR summation operation: The logic operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i ; When the logic operation implemented by the logic operation circuit is an exclusive OR summation operation: the logic operation path includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; wherein, the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the drains of the fourth MOS transistor and the sixth MOS transistor are connected and connected to the output terminal VO; the sources of the fifth MOS transistor and the seventh MOS transistor are connected to the drain of the first MOS transistor; if the fourth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; if the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to x i ; if the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to w i .

4. The logic operation circuit according to any one of claims 1-3, characterized in that Further comprising: MOS transistor C; wherein, the drain electrode of the MOS transistor C is connected to the output terminal VO, and the source electrode is grounded; The control unit is further configured to perform a reset operation on the logic operation circuit before performing a convolution operation: control the MOS transistor C to be turned on, and the first MOS transistor and the third MOS transistor to be turned off to reset the output terminal VO to be grounded; when performing a logic operation, control the MOS transistor C to be in an off state.

5. A mixed-signal convolution operation circuit, characterized in that Comprising: A first MOS transistor, a second MOS transistor, a third MOS transistor, a first capacitor, a second capacitor, a third capacitor, an arithmetic operation path, and a control unit; one end of the first capacitor serves as the positive-phase output terminal VP of the convolution operation circuit, and the other end is grounded; one end of the second capacitor serves as the anti-phase output terminal VN of the convolution operation circuit, and the other end is grounded; the source electrode of the first MOS transistor is connected to the drain electrode of the second MOS transistor, the source electrode of the second MOS transistor, the drain electrode of the third MOS transistor, and one end of the third capacitor are connected, and the source electrode of the third MOS transistor is connected to the other end of the third capacitor and is connected to the power supply voltage VDD; The control unit is configured to input the data signal x i and the weight signal w i into the arithmetic operation path, and before each group of x i and w i is input, control the first MOS transistor to turn off and the third MOS transistor to turn on to charge the third capacitor to the voltage VDD, and then control the first MOS transistor to turn on and the third MOS transistor to turn off, and input x i and w i into the arithmetic operation path; i = 1, 2, …, N; N is the length of the data to be convolved; The arithmetic operation path is used to, after receiving the inputs of x i and w i , when the levels of x i and w i are the same, connect the drain terminal of the first MOS transistor to the non-inverting output terminal VP to perform voltage superposition at the non-inverting output terminal VP; when the levels of x i and w i are opposite, connect the drain terminal of the first MOS transistor to the inverting output terminal VN to perform voltage superposition at the inverting output terminal VN; wherein, the gate of the second MOS transistor is connected to a bias voltage to ensure that the magnitude of the voltage superimposed each time is the same; the final voltage difference between the non-inverting output terminal VP and the inverting output terminal VN is the voltage value corresponding to the convolution operation result .

6. The convolution operation circuit according to claim 5, wherein The arithmetic operation path includes: the fourth to eleventh MOS transistors; wherein, the sources of the fourth MOS transistor, the fifth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are commonly connected to the drain of the first MOS transistor; the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor; the drain of the fifth MOS transistor is connected to the source of the seventh MOS transistor; the drain of the eighth MOS transistor is connected to the source of the tenth MOS transistor; the drain of the ninth MOS transistor is connected to the source of the eleventh MOS transistor; the drains of the sixth MOS transistor and the tenth MOS transistor are commonly connected to the positive-phase output terminal VP; the drains of the seventh MOS transistor and the eleventh MOS transistor are commonly connected to the negative-phase output terminal VN; If the fourth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fourth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; If the fifth MOS transistor is a PMOS transistor, its gate is connected to w i ; if the fifth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of w i ; If the sixth MOS transistor is a PMOS transistor, its gate is connected to x i ; if the sixth MOS transistor is an NMOS transistor, its gate is connected to the inverted signal of x i ; If the eleventh MOS transistor is a PMOS transistor, its gate is connected to x i ; if the eleventh MOS transistor is an NMOS transistor, its gate is connected to x i 's inverted signal; If the seventh MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the seventh MOS transistor is an NMOS transistor, its gate is connected to x i ; If the tenth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of x i ; if the tenth MOS transistor is an NMOS transistor, its gate is connected to x i ; If the eighth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the eighth MOS transistor is an NMOS transistor, its gate is connected to w i ; If the ninth MOS transistor is a PMOS transistor, its gate is connected to the inverted signal of w i ; if the ninth MOS transistor is an NMOS transistor, its gate is connected to w i .

7. The convolution operation circuit according to claim 5 or 6, characterized in that, It further includes: MOS transistor A and MOS transistor B; wherein, the drain of MOS transistor A is connected to the positive-phase output terminal VP, and the source is grounded; the drain of MOS transistor B is connected to the negative-phase output terminal VN, and the source is grounded; The control unit is further configured to perform a reset operation on the convolution operation circuit before performing the convolution operation: control MOS transistor A and MOS transistor B to conduct, and the first MOS transistor and the third MOS transistor to turn off, so as to reset the positive-phase output terminal VP and the negative-phase output terminal VN to ground; when performing the convolution operation, control MOS transistor A and MOS transistor B to be in the off state.

8. A switched-capacitor arithmetic circuit, characterized in that, It includes: M charge injection calculation units, M first connection capacitors, and M second connection capacitors; wherein, the charge injection calculation unit is the logic operation circuit according to any one of claims 1-4 or the convolution operation circuit according to any one of claims 5-7; When the charge injection calculation unit is the logic operation circuit according to any one of claims 1-4: The output terminals VO of the M charge injection calculation units are respectively connected to one ends of the M connection capacitors in one-to-one correspondence, and the other ends of the M connection capacitors are connected together and used as the output terminal VOUT of the switched-capacitor operation circuit; The outputs of the output terminals VO of the M charge injection calculation units are superimposed at the output terminal VOUT via the corresponding connection capacitors; A logic operation is divided into M groups of sub-logic operations; one charge injection calculation unit is used to implement one sub-logic operation; the output of the output terminal VOUT is the voltage value corresponding to the required logic operation result; When the charge injection calculation unit is the convolution operation circuit according to any one of claims 5-7: The positive-phase output terminals VP of the M charge injection calculation units are respectively connected to one ends of the M first connection capacitors in one-to-one correspondence, and the other ends of the M first connection capacitors are connected together and used as the positive-phase output terminal VOUTP of the switched-capacitor operation circuit; The negative-phase output terminals VN of the M charge injection calculation units are respectively connected to one ends of the M second connection capacitors in one-to-one correspondence, and the other ends of the M second connection capacitors are connected together and used as the negative-phase output terminal VOUTN of the switched-capacitor operation circuit; The outputs of the positive-phase output terminals VP of the M charge injection calculation units are superimposed at the positive-phase output terminal VOUTP via the corresponding first connection capacitors; The outputs of the negative-phase output terminals VN of the M charge injection calculation units are superimposed at the negative-phase output terminal VOUTN via the corresponding second connection capacitors; A convolution operation is divided into M groups of sub-convolution operations; one charge injection calculation unit is used to implement one sub-convolution operation; the final voltage difference between the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN is the voltage value corresponding to the result of the required convolution operation.

9. The switched-capacitor arithmetic circuit according to claim 8, wherein When the charge injection calculation unit is the logic operation circuit described in any one of claims 1-4, the switched-capacitor operation circuit further includes: a reset circuit connected to the output terminal VOUT; When the charge injection calculation unit is the convolution operation circuit described in any one of claims 5-7, the switched-capacitor operation circuit further includes: reset circuits respectively connected to the positive-phase output terminal VOUTP and the negative-phase output terminal VOUTN.

10. An electronic chip, characterized in that, Including the logic operation circuit described in any one of claims 1-4, or the convolution operation circuit described in any one of claims 5-7, or the switched-capacitor operation circuit described in any one of claims 8-9.

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