Synapse circuit, method, device and medium for avoiding displacement current of ferroelectric tunnel junction

Abstract

The invention discloses synaptic circuits, a method, equipment and a medium for avoiding displacement current of a ferroelectric tunnel junction, and relates to the technical field of pulse neural networks, the synaptic circuits and the post-neuron circuit are of the same structure, the synaptic circuits are used for generating tunneling current when voltage difference exists at two ends of the ferroelectric tunnel junction, and the post-neuron circuit is used for generating the displacement current when voltage difference exists at two ends of the ferroelectric tunnel junction. An internal capacitor in the ferroelectric tunnel junction is controlled to discharge, the voltage in the synaptic circuit is raised, and a charging voltage is output when a pre-synaptic neuron pulse signal is received; the post neuron circuit is respectively connected with the plurality of synaptic circuits and is used for outputting post-synaptic neuron pulse signals according to the accessed charging voltage; and the synaptic circuit is also used for changing the voltage amplitude applied to the two ends of the ferroelectric tunnel junction according to the time interval between the received post-synaptic neuron pulse signal and the input signal, so that the reading error and the pulse neural network application bottleneck caused by the capacitance current characteristic and the resistance current characteristic of the ferroelectric tunnel junction are solved.

Description

Technical Field

[0001] The present application relates to the technical field of spiking neural networks, and particularly to a synaptic circuit, method, device, and medium for avoiding displacement current in ferroelectric tunneling junctions. Background Art

[0002] With the development of artificial intelligence technology, the defect of the separation of storage and computing in the von Neumann architecture has led to a sharp increase in the computing energy consumption of AI large models. Neuromorphic computing has become a key direction for improving energy efficiency by simulating the processing mechanism of the biological brain. Spiking neural networks are widely recognized for their event-driven and brain-like characteristics, but their hardware implementation depends on new storage devices. Ferroelectric tunneling junctions have become an ideal choice for constructing spiking neural networks due to the controllable polarization direction of the ferroelectric layer, adjustable tunneling resistance, and low current density characteristics.

[0003] However, ferroelectric tunneling junctions face double interference from capacitive current and resistance characteristics in hardware deployment: the transient capacitive current generated during the polarization switching of the ferroelectric layer overlaps with the tunneling resistance current level, resulting in synaptic signal reading errors; at the same time, there is an adaptation bottleneck between the non-linear resistance characteristics in some polarization states and the dynamic computing requirements of spiking neural networks. Summary of the Invention

[0004] The main purpose of the present application is to provide a synaptic circuit, method, device, and medium for avoiding displacement current in ferroelectric tunneling junctions, aiming to solve the technical problems of reading errors and application bottlenecks of spiking neural networks caused by the capacitive current characteristics and resistance current characteristics of ferroelectric tunneling junctions.

[0005] To achieve the above purpose, the present application proposes a synaptic circuit for avoiding displacement current in ferroelectric tunneling junctions, which includes:

[0006] A plurality of sub-synaptic circuits with the same structure, on which ferroelectric tunneling junctions are connected. The sub-synaptic circuits are used to generate tunneling current when the voltage difference across the ferroelectric tunneling junctions changes, control the internal capacitance in the ferroelectric tunneling junctions to discharge, raise the voltage in the sub-synaptic circuits, and output a charging voltage based on the voltage in the sub-synaptic circuits when receiving a pre-synaptic neuron pulse signal;

[0007] A post-neuron circuit, which is respectively connected to a plurality of sub-synaptic circuits. The post-neuron circuit is used to output a post-synaptic neuron pulse signal according to the received charging voltage;

[0008] The sub-synaptic circuit is also used to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the received post-synaptic neuron pulse signal and the input signal.

[0009] In one embodiment, the sub-synaptic circuit includes a first transistor and a second transistor;

[0010] The input terminal of the first transistor is connected to the reset voltage terminal, the output terminal of the first transistor is connected to the cathode of the ferroelectric tunneling junction, the gate of the first transistor is used to access the enable reset signal, the input terminal of the second transistor is connected to the connection line between the first transistor and the ferroelectric tunneling junction, and the anode of the ferroelectric tunneling junction is connected to the platform voltage terminal. Among them, the connection point of the first transistor and the second transistor is the first node;

[0011] The sub-synaptic circuit is used to reset the voltage on the first node to the voltage value on the reset voltage terminal when the first transistor enters the conducting state according to the accessed enable reset signal;

[0012] The sub-synaptic circuit is further used to control the internal capacitor to discharge the first node and charge the voltage on the first node to the voltage value on the platform voltage terminal when the ferroelectric tunneling junction enters the discharging state according to the voltage value accessed from the platform voltage terminal.

[0013] In one embodiment, the sub-synaptic circuit further includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0014] The output terminal of the second transistor is connected to the control terminal of the fourth transistor, and the input terminal of the third transistor is connected to the connection line between the second transistor and the fourth transistor. Among them, the connection point of the second transistor and the fourth transistor is the second node;

[0015] The input terminal of the fourth transistor is connected to the output terminal of the fifth transistor, the output terminals of the fourth transistor and the third transistor are commonly grounded, the input terminals of the fifth transistor and the sixth transistor are commonly connected to the power supply voltage terminal, and the control terminal of the sixth transistor is connected to the connection line between the fourth transistor and the fifth transistor;

[0016] The control terminals of the second transistor and the third transistor are used to access the pre-synaptic neuron pulse signal, and the control terminal of the fifth transistor is used to access the amplifier output voltage;

[0017] The sub-synaptic circuit is further used to generate a charging voltage based on the voltage on the first node and transmit it to the second node to control the fourth transistor to enter the conducting state when the second transistor and the third transistor enter the conducting state according to the accessed pre-synaptic neuron pulse signal;

[0018] The sub-synaptic circuit is further used to access a constant voltage through the conducting fifth transistor to amplify the charging voltage and output the amplified charging voltage when the fourth transistor and the sixth transistor enter the conducting state.

[0019] In one embodiment, the post-neuron circuit includes a storage capacitor, a first comparator, and a delay element;

[0020] The first end of the storage capacitor is connected to the output end of the sixth transistor. The negative input end of the first comparator is connected to the first end of the storage capacitor, and the output end of the first comparator is connected to the input end of the delay element.

[0021] A post-neuron circuit is configured to charge the storage capacitor based on an applied charging voltage, causing the membrane potential at the negative input end of the first comparator to rise. When the membrane potential rises to reach a threshold value, the post-neuron circuit controls the first comparator to output a digital pulse signal to the delay element, enabling the delay element to output a post-synaptic neuron pulse signal according to the digital pulse signal.

[0022] In one embodiment, the sub-synaptic circuit further includes a seventh transistor.

[0023] The control end of the seventh transistor is connected to the output end of the delay element. The input end of the seventh transistor is configured to receive an input signal, and the output end of the seventh transistor is connected to the cathode of the ferroelectric tunneling junction.

[0024] The sub-synaptic circuit is configured to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction through the seventh transistor.

[0025] In addition, to achieve the above object, the present application further provides a control method for the ferroelectric tunneling junction in a synaptic circuit that avoids the displacement current of the ferroelectric tunneling junction. The control method is applied to the synaptic circuit that avoids the displacement current of the ferroelectric tunneling junction. The synaptic circuit that avoids the displacement current of the ferroelectric tunneling junction includes a sub-synaptic circuit and a post-neuron circuit, and the ferroelectric tunneling junction is disposed in the sub-synaptic circuit.

[0026] The control method includes:

[0027] When the voltage difference across the ferroelectric tunneling junction changes to generate a tunneling current, controlling the internal capacitor in the ferroelectric tunneling junction to discharge, raising the voltage in the sub-synaptic circuit, and when receiving a pre-synaptic neuron pulse signal, outputting a charging voltage to the post-neuron circuit based on the voltage in the sub-synaptic circuit.

[0028] Controlling the post-neuron circuit to output a post-synaptic neuron pulse signal according to the applied charging voltage.

[0029] Changing the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, thereby modulating the tunneling resistance of the ferroelectric tunneling junction.

[0030] In one embodiment, the step of changing the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, thereby modulating the tunneling resistance of the ferroelectric tunneling junction, includes:

[0031] If the first time point when the input signal is transmitted into the ferroelectric tunneling junction is earlier than the second time point when the postsynaptic neuron pulse signal is transmitted into the ferroelectric tunneling junction, the time interval is the positive time interval obtained by subtracting the first time point from the second time point;

[0032] Increase the forward voltage applied to the ferroelectric tunneling junction according to the positive time interval, thereby reducing the tunneling resistance.

[0033] In one embodiment, according to the time interval between the postsynaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, the steps of modulating the tunneling resistance of the ferroelectric tunneling junction by changing the voltage amplitude applied across the ferroelectric tunneling junction include:

[0034] If the third time point when the input signal is transmitted into the ferroelectric tunneling junction is later than the fourth time point when the postsynaptic neuron pulse signal is transmitted into the ferroelectric tunneling junction, the time interval is the negative time interval obtained by subtracting the third time point from the fourth time point;

[0035] Increase the reverse voltage applied to the ferroelectric tunneling junction according to the negative time interval, thereby increasing the tunneling resistance.

[0036] In addition, to achieve the above object, the present application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the control method as described above.

[0037] In addition, to achieve the above object, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program is executed by a processor, it implements the steps of the control method as described above.

[0038] One or more technical solutions proposed by the present application have at least the following technical effects:

[0039] A synaptic circuit for avoiding the displacement current of a ferroelectric tunneling junction is proposed. The synaptic circuit for avoiding the displacement current of a ferroelectric tunneling junction includes: a plurality of sub-synaptic circuits with the same structure and a postsynaptic neuron circuit. A ferroelectric tunneling junction is connected to the sub-synaptic circuit. The sub-synaptic circuit is used to generate a tunneling current when the voltage difference across the ferroelectric tunneling junction changes, control the internal capacitance in the ferroelectric tunneling junction to discharge, raise the voltage in the sub-synaptic circuit, and output a charging voltage based on the voltage in the sub-synaptic circuit when receiving a presynaptic neuron pulse signal; the postsynaptic neuron circuit, which is respectively connected to a plurality of sub-synaptic circuits, is used to output a postsynaptic neuron pulse signal according to the received charging voltage; the sub-synaptic circuit is also used to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the received postsynaptic neuron pulse signal and the input signal.

[0040] That is, the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction proposed in this application converts the capacitive current in the internal capacitance of the ferroelectric tunneling junction into a charging voltage, avoiding the direct interference of the capacitive current on the synaptic function, and since this charging voltage is electric charge, the electric charge is used to replace the current transmission, so the influence of the capacitive current characteristics of the ferroelectric tunneling junction on the network stability can be avoided; at the same time, the charging voltage is transmitted between the sub-synaptic circuit and the post-neuron circuit, cutting off the current path of the ferroelectric tunneling junction, so the direct influence of the resistance current in the ferroelectric tunneling junction on the post-neuron circuit can be avoided, and by adjusting the voltage amplitude applied across the ferroelectric tunneling junction through the time interval between the post-synaptic neuron pulse signal and the input signal, the resistance value modulation of the tunneling resistance in the ferroelectric tunneling junction is activated within a specific time window, realizing the local update of the synaptic weight and adapting to the dynamic calculation requirements of the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction. Description of the Drawings

[0041] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a schematic diagram of the module structure of the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction in this application;

[0044] Figure 2 It is a schematic diagram of an implementable structure of the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction in this application;

[0045] Figure 3 It is a schematic diagram of the flow of the control method in this application;

[0046] Figure 4 It is a schematic diagram of the waveform of the voltage amplitude adjustment;

[0047] Figure 5 It is another schematic diagram of the waveform of the voltage amplitude adjustment;

[0048] Figure 6 It is a schematic diagram of the device structure of the hardware operating environment involved in the control method in the embodiments of this application.

[0049] Explanation of the Reference Numerals in the Drawings:

[0050] 10. Sub - synaptic circuit; FTJ, ferroelectric tunneling junction; M1, first transistor; M2, second transistor; V Rst , reset voltage terminal; EN_Rst, enable reset signal; V PL , plateau voltage terminal; X, first node; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; Y, second node; VDD, power supply voltage terminal; LIF WL, pre - synaptic neuron pulse signal; V Amp , amplifier output voltage; STDP WL, input signal;

[0051] 20. Post - neuron circuit; C Mem , storage capacitor; U1, first comparator; V Mem , membrane potential; U2, delay element; Fire, digital pulse signal; STDP BL, post - synaptic neuron pulse signal.

[0052] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Embodiments

[0053] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not used to limit this application.

[0054] To better understand the technical solutions of this application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific embodiments.

[0055] The main solution of the embodiment of this application is: A synaptic circuit for avoiding the displacement current of ferroelectric tunneling junctions is proposed. The synaptic circuit for avoiding the displacement current of ferroelectric tunneling junctions includes: a plurality of sub - synaptic circuits with the same structure and a post - neuron circuit. A ferroelectric tunneling junction is connected to the sub - synaptic circuit. The sub - synaptic circuit is used to generate a tunneling current when the voltage difference across the ferroelectric tunneling junction changes, control the internal capacitance in the ferroelectric tunneling junction to discharge, raise the voltage in the sub - synaptic circuit, and when receiving a pre - synaptic neuron pulse signal, output a charging voltage based on the voltage in the sub - synaptic circuit; the post - neuron circuit, which is respectively connected to a plurality of sub - synaptic circuits, is used to output a post - synaptic neuron pulse signal according to the input charging voltage; the sub - synaptic circuit is also used to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the received post - synaptic neuron pulse signal and the input signal.

[0056] In the prior art, ferroelectric tunneling junctions face dual interference from capacitive current and resistance characteristics in hardware deployment: the transient capacitive current generated during polarization switching of the ferroelectric layer overlaps with the magnitude of the tunneling resistance current, resulting in synaptic signal reading errors; at the same time, there is an adaptation bottleneck between the non-linear resistance characteristics in some polarization states and the dynamic calculation requirements of pulse neural networks.

[0057] The present application provides a solution, which is designed to convert the capacitive current in the internal capacitance of the ferroelectric tunneling junction into a charging voltage, avoiding the direct interference of the capacitive current on synaptic functions, and since this charging voltage is a charge, using charge instead of current transmission, thus being able to circumvent the influence of the capacitive current characteristics of the ferroelectric tunneling junction on network stability; at the same time, the charging voltage is transmitted between the sub-synaptic circuit and the post-neuron circuit, cutting off the current path of the ferroelectric tunneling junction, so that the direct influence of the resistance current in the ferroelectric tunneling junction on the post-neuron circuit can be avoided, and by adjusting the voltage amplitude applied across the ferroelectric tunneling junction through the time interval between the post-synaptic neuron pulse signal and the input signal, modulating the resistance value of the tunneling resistance in the ferroelectric tunneling junction within a specific time window, realizing the local update of synaptic weights, and adapting to the dynamic calculation requirements of the synaptic circuit that circumvents the displacement current of the ferroelectric tunneling junction.

[0058] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of implementing the above functions. Hereinafter, an electronic device will be taken as an example to illustrate this embodiment and the following embodiments.

[0059] Based on this, the embodiments of the present application provide a synaptic circuit that circumvents the displacement current of the ferroelectric tunneling junction, referring to Figure 1 , Figure 1 which is the structural schematic diagram of the synaptic circuit that circumvents the displacement current of the ferroelectric tunneling junction of the present application.

[0060] The synaptic circuit that circumvents the displacement current of the ferroelectric tunneling junction includes:

[0061] Multiple sub-synaptic circuits 10 with the same structure are provided. A ferroelectric tunneling junction FTJ is connected to the sub-synaptic circuit 10. The sub-synaptic circuit 10 is configured to generate a tunneling current when the voltage difference across the ferroelectric tunneling junction FTJ changes, control the internal capacitance in the ferroelectric tunneling junction FTJ to discharge, raise the voltage in the sub-synaptic circuit 10, and output a charging voltage based on the voltage in the synaptic circuit when receiving a pre-synaptic neuron pulse signal LIFWL. A post-neuron circuit 20 is respectively connected to multiple sub-synaptic circuits 10. The post-neuron circuit 20 is configured to output a post-synaptic neuron pulse signal STDP BL according to the applied charging voltage. The sub-synaptic circuit 10 is further configured to change the voltage amplitude applied across the ferroelectric tunneling junction FTJ according to the time interval between the received post-synaptic neuron pulse signal STDP BL and the input signal STDP WL.

[0062] It should be noted that displacement current is the current generated by the change in electric field strength. Therefore, in this embodiment, it includes capacitive current and resistive current.

[0063] According to the above-mentioned synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction, it can be seen that the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction proposed in this embodiment integrates a post-neuron circuit 20 with the function of neuron LIF (Leaky Integrate-and-Fire) and a sub-synaptic circuit 10 with the function of synaptic STDP (Spike-Timing-Dependent Plasticity).

[0064] Among them, regarding the sub-synaptic circuit 10 with the function of synaptic STDP, in this embodiment, when the conduction between the sub-synaptic circuit 10 and the post-neuron circuit 20 is not yet conducted, there is no closed loop between the ferroelectric tunneling junction FTJ and the external circuit. Therefore, when the voltage difference across the ferroelectric tunneling junction FTJ changes at this time, the generated tunneling current will cause the internal capacitance of the ferroelectric tunneling junction FTJ to start discharging, thereby raising the voltage in the sub-synaptic circuit 10, that is, converting the transient effect existing in the capacitive current characteristic of the ferroelectric tunneling junction FTJ into a slow rise of the voltage in the sub-synaptic circuit 10, avoiding the direct interference of the capacitive current characteristic on the synaptic STDP function, and further avoiding the overlap of the transient capacitive current generated during the polarization switching of the ferroelectric layer and the magnitude of the tunneling resistance current, resulting in synaptic signal reading errors.

[0065] At the same time, because the voltage in the sub-synaptic circuit 10 is raised, when the sub-synaptic circuit 10 and the post-neuron circuit 20 are conducted, the charging voltage is transmitted between them, cutting off the current path of the ferroelectric tunneling junction FTJ, and can avoid the direct influence of the resistive current in the ferroelectric tunneling junction FTJ on the post-neuron circuit 20.

[0066] Regarding the post-neuronal circuit 20 for neuron LIF function, according to the timing difference (i.e., time interval) between the post-synaptic neuron pulse signal STDP BL and the input signal STDP WL reaching the ferroelectric tunneling junction FTJ respectively, dynamically adjust the voltage amplitude applied across the ferroelectric tunneling junction FTJ. That is, utilize the voltage-time integration characteristic of ferroelectric polarization to achieve non-volatile modulation of the internal resistance in the ferroelectric tunneling junction FTJ, realize the conversion of the non-linear change of the internal resistance into a programmable synaptic weight update rule, that is, realize the local update of synaptic weights, and break through the adaptation bottleneck existing in the dynamic calculation requirements of pulse neural networks.

[0067] The specific implementation process is as follows.

[0068] In a feasible implementation manner, the specific structure of a synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction proposed in this application can be as Figure 2 shown. The following will be described in segments according to the four stages that the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction proposed in this embodiment needs to execute.

[0069] The sub-synaptic circuit 10 includes a first transistor M1 and a second transistor M2. The input end of the first transistor M1 is connected to the reset voltage terminal V Rst , the output end of the first transistor M1 is connected to the cathode of the ferroelectric tunneling junction FTJ, the gate of the first transistor M1 is used to access the enable reset signal EN_Rst, the input end of the second transistor M2 is connected to the connection line between the first transistor M1 and the ferroelectric tunneling junction FTJ, and the anode of the ferroelectric tunneling junction FTJ is connected to the platform voltage terminal V PL , where the connection point of the first transistor M1 and the second transistor M2 is the first node X.

[0070] ① The sub-synaptic circuit 10 is used to reset the voltage on the first node X to the voltage value on the reset voltage terminal V Rst when the first transistor M1 enters the conducting state according to the accessed enable reset signal EN_Rst.

[0071] The first stage is the reset stage. Specifically: in the reset stage, the enable reset signal EN_Rst controls the first transistor M1 to enter the conducting state, while other transistors are in the cut-off state. Therefore, at this time, the first node X will be connected to the reset voltage terminal V Rst , and the voltage on its potential will be reset to the voltage value on the reset voltage terminal V Rst to avoid the interference of the historical state on the subsequent stages.

[0072] ② The sub-synaptic circuit 10 is also used to, when the ferroelectric tunneling junction FTJ is based on the platform voltage terminal V PLWhen the access voltage value enters the discharge state, the internal capacitor is controlled to discharge the first node X, and the voltage on the first node X is charged to the voltage value on the platform voltage terminal V PL of the voltage value on it.

[0073] The second stage is the discharge stage. Specifically: in the discharge stage, all transistors are in the cut-off state. Therefore, at this time, the cathode of the ferroelectric tunneling junction FTJ is floating. So when the platform voltage terminal V PL starts to discharge the ferroelectric tunneling junction FTJ, because the voltage on the first node X is still the voltage value on the reset voltage terminal V Rst of the voltage value on it. At this time, the voltage difference across the ferroelectric tunneling junction FTJ changes, and this voltage difference will cause the current on the platform voltage terminal V PL to flow through the tunneling resistance (i.e., the internal resistance of the ferroelectric tunneling junction FTJ). And because all transistors are in the cut-off state, there is no closed loop between the ferroelectric tunneling junction FTJ and the external circuit (such as the post-neuron circuit 20) at this stage. So the tunneling current generated by flowing through the tunneling resistance will discharge the internal capacitor of the ferroelectric tunneling junction FTJ itself. According to Figure 2 the path between the ferroelectric tunneling junction FTJ and the first node X shown, the discharge operation of the internal capacitor will cause the voltage on the first node X to rise slowly until it rises to the voltage value on the platform voltage terminal V PL of the voltage value on it. This process converts the original transient capacitive current into a slow-varying signal in the voltage domain, rather than directly participating in the synaptic STDP function of the sub-synaptic circuit 10, thus avoiding the instantaneous superposition of the capacitive current and the resistive current.

[0074] The sub-synaptic circuit 10 further includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The output terminal of the second transistor M2 is connected to the control terminal of the fourth transistor M4. The input terminal of the third transistor M3 is connected to the line connecting the second transistor M2 and the fourth transistor M4, where the connection point of the second transistor M2 and the fourth transistor M4 is the second node Y; the input terminal of the fourth transistor M4 is connected to the output terminal of the fifth transistor M5. The output terminals of the fourth transistor M4 and the third transistor M3 are commonly grounded. The input terminals of the fifth transistor M5 and the sixth transistor M6 are commonly connected to the power supply voltage terminal VDD, and the control terminal of the sixth transistor M6 is connected to the line connecting the fourth transistor M4 and the fifth transistor M5; the control terminals of the second transistor M2 and the third transistor M3 are used to access the pre-synaptic neuron pulse signal LIF WL, and the control terminal of the fifth transistor M5 is used to access the amplifier output voltage V Amp .

[0075] ③ The sub-synaptic circuit 10 is further configured to generate a charging voltage based on the voltage at the first node X and transmit it to the second node Y to control the fourth transistor M4 to enter the conducting state when the second transistor M2 and the third transistor M3 enter the conducting state according to the received pre-synaptic neuron pulse signal LIF WL.

[0076] The sub-synaptic circuit 10 is further configured to, when the fourth transistor M4 and the sixth transistor M6 enter the conducting state, access the constant voltage of the power supply voltage terminal VDD through the conducting fifth transistor M5 to amplify the charging voltage and output the amplified charging voltage.

[0077] The third stage is the neuron LIF stage. Specifically: in this stage, the pre-synaptic neuron pulse signal LIF WL controls the second transistor M2 and the third transistor M3 to enter the conducting state. Therefore, the path between the first node X and the second node Y is conducting at this time, and the voltage at the first node X will be transmitted to the second node Y as the charging voltage, causing the fourth transistor M4 to enter the conducting state. And when the fifth transistor M5 enters the conducting state based on the received amplifier output voltage V Amp the constant voltage it accesses from the power supply voltage terminal VDD will control the sixth transistor M6 to enter the conducting state.

[0078] The fourth transistor M4 and the sixth transistor M6 can perform signal secondary amplification on the charging voltage at the second node Y; in addition, through Figure 2 the eighth transistor (i.e., Figure 2 M8 in

[0079] being used as current leakage, the Vmem voltage can be slowly reduced.

[0080] Further, the post-neuron circuit 20 includes a storage capacitor C Mem , a first comparator U1, and a delay unit U2; the first terminal of the storage capacitor C Mem is connected to the output terminal of the sixth transistor M6, the negative input terminal of the first comparator U1 is connected to the first terminal of the storage capacitor C Mem and the output terminal of the first comparator U1 is connected to the input terminal of the delay unit U2.

[0081] ③ The post-neuron circuit 20 is configured to charge the storage capacitor C Mem based on the received charging voltage, so that the membrane potential V Memrises and at the membrane potential V Mem when the rise reaches the threshold value (i.e., Figure 2 V in Th ), control the first comparator U1 to output a digital pulse signal Fire to the delay U2, so that the delay U2 outputs a postsynaptic neuron pulse signal STDP BL according to the digital pulse signal Fire.

[0082] At this time, it is still the neuron LIF stage. Specifically: in the case where the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are in the conducting state, the charging voltage at this time will charge the storage capacitor C Mem such that the membrane potential V of the first comparator U1 Mem starts to rise. When the membrane potential V Mem rises to reach the threshold value, the first comparator U1 starts to output a digital pulse signal Fire, and transmits it to the delay U2 via the first pulse generator (i.e., Figure 2 U3 in

[0083] In this stage, because the charging voltage on the first node X is transmitted to the control terminal of the fourth transistor M4 (i.e., the second node Y) through the second transistor M2, driving the fourth transistor M4 to generate a discharge current inversely proportional to the internal resistance. At this time, the influence of the capacitive current has been solidified in the voltage of the first node X, and the resistive current indirectly affects the membrane potential integration of the post-neuron circuit 20 through the conduction characteristics of the fourth transistor M4. The two are completely decoupled in terms of timing and functional paths, avoiding the superimposed influence of the resistive current and the capacitive current.

[0084] The sub-synaptic circuit 10 further includes a seventh transistor M7. The control terminal of the seventh transistor M7 is connected to the output terminal of the delay U2. The input terminal of the seventh transistor M7 is used to access the input signal STDP WL, and the output terminal of the seventh transistor M7 is connected to the cathode of the ferroelectric tunneling junction FTJ.

[0085] ④ The sub-synaptic circuit 10 is used to change the voltage amplitude applied across the ferroelectric tunneling junction FTJ according to the time interval between the postsynaptic neuron pulse signal STDP BL and the input signal STDP WL transmitted into the ferroelectric tunneling junction FTJ through the seventh transistor M7.

[0086] The fourth stage is the synaptic STDP function. Specifically: the generated postsynaptic neuron pulse signal STDP BL will be transmitted to the control terminal of the seventh transistor M7 and introduced into the ferroelectric tunneling junction FTJ through the conducting seventh transistor M7. And according to Figure 2It can be seen that an input signal STDP WL is also connected to the input end of the seventh transistor M7. At this time, the ferroelectric tunneling junction FTJ determines the time interval according to the arrival timing and arrival timing difference between the postsynaptic neuron pulse signal STDP BL and the input signal STDP WL, and adjusts the voltage amplitude applied across its two ends according to the time interval, thereby changing the voltage difference between the anode and cathode of the ferroelectric tunneling junction FTJ.

[0087] In this embodiment, the ferroelectric tunneling junction FTJ adopts the design of charge domains. Therefore, when the voltage difference between the anode and cathode of the ferroelectric tunneling junction FTJ changes, the polarization direction of the ferroelectric layer is affected by the voltage difference on the electrodes, and it changes from the platform voltage terminal V PL The voltage value connected to it will also change dynamically, thereby changing the resistance value of the internal resistance (i.e., tunneling resistance). That is, the non-volatile modulation of the tunneling resistance is realized by utilizing the voltage-time integration characteristic of the ferroelectric layer polarization. This design converts the non-linear change of the tunneling resistance into a programmable synaptic weight update rule.

[0088] According to the above, the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction proposed in this embodiment integrates the sub-synaptic circuit 10 and the post-neuron circuit 20 into the same circuit. Through the charge domain conversion of the capacitive current, the non-linear compensation of the resistive current, and the operation stage of timing decoupling, the inherent capacitive current characteristic and resistive current characteristic of the ferroelectric tunneling junction FTJ are transformed from interference factors into the core resources for function realization, and finally, the synaptic-neuron integration of the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction with high robustness is realized at the hardware level.

[0089] It should be noted that in the actual application process, a post-neuron circuit 20 can be connected to multiple sub-synaptic circuits 10, and the specific number of sub-synaptic circuits 10 connected is determined by the storage capacitor C Mem The charge that can be stored.

[0090] Furthermore, it is illustrated that the device parameters such as the gate length, doping concentration, and gate insulation layer thickness of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 in this embodiment are adjustable. For example, by increasing the gate length of the fourth transistor M4, its transconductance can be reduced, and the noise amplification caused by the capacitive current can be suppressed; the ferroelectric layer material and ferroelectric layer thickness of the ferroelectric tunneling junction FTJ are adjustable. For example, by thinning the ferroelectric layer thickness of the ferroelectric tunneling junction FTJ, the control of polarization by the electric field can be enhanced, and the linearity of the tunneling resistance modulation can be improved; the pulse shapes and sizes of the presynaptic neuron pulse signal LIF WL, the input signal STDP WL, and the postsynaptic neuron pulse signal STDP BL are adjustable.

[0091] Among them, specifically illustrate the second pulse generator (i.e., Figure 2The function of U4) is to ensure precise control of the neuron firing threshold (i.e., the output time of the postsynaptic neuron pulse signal STDP BL output by the delay U2) by stabilizing the reference voltage (i.e., Ref in Figure 2 ), thereby triggering a digital pulse signal Fire with precise timing to drive STDP learning. The ninth transistor (i.e., M9 in Figure 2 ) is used as a switch. The presynaptic neuron pulse signal LIF WL comes from the presynaptic neuron, and the input signal STDP WL adjusts the input waveform according to the arrival time of the presynaptic neuron pulse signal LIF WL and the triggering time of the postsynaptic neuron pulse signal STDP BL.

[0092] In addition, the present application also provides a control method for the ferroelectric tunneling junction FTJ in a synaptic circuit that avoids the displacement current of the ferroelectric tunneling junction. Referring to Figure 3 , Figure 3 is a schematic flowchart of the control method of the present application. The control method includes steps S10 to S30:

[0093] Step S10, when the voltage difference across the ferroelectric tunneling junction FTJ changes, a tunneling current is generated, controlling the internal capacitance in the ferroelectric tunneling junction FTJ to discharge, raising the voltage in the sub-synaptic circuit 10, and when receiving the presynaptic neuron pulse signal LIF WL, outputting a charging voltage to the post-neuron circuit 20 based on the voltage in the sub-synaptic circuit 10.

[0094] Step S20, controlling the post-neuron circuit 20 to output the postsynaptic neuron pulse signal STDP BL according to the applied charging voltage.

[0095] Step S30, according to the time interval between the postsynaptic neuron pulse signal STDP BL and the input signal STDP WL entering the ferroelectric tunneling junction FTJ, changing the voltage amplitude applied across the ferroelectric tunneling junction FTJ to modulate the tunneling resistance of the ferroelectric tunneling junction FTJ.

[0096] The specific implementation manners of steps S10 to S30 are as described above for Figure 2 , and will not be repeated here.

[0097] In a feasible implementation manner, step S30 includes steps S31 to S32:

[0098] Step S31, if the first time point when the input signal STDP WL enters the ferroelectric tunneling junction FTJ is earlier than the second time point when the postsynaptic neuron pulse signal STDP BL enters the ferroelectric tunneling junction FTJ, the time interval is the positive time interval obtained by subtracting the first time point from the second time point.

[0099] Step S32: Increase the forward voltage applied to the ferroelectric tunneling junction FTJ according to a positive time interval to reduce the tunneling resistance.

[0100] Combined with Figure 4 and Figure 5 for illustration. It should be noted that Figure 4 The horizontal axis in represents the time interval between the input signal STDP WL and the post-synaptic neuron pulse signal STDP BL, ranging from -300 ns to 300 ns. Δt = 0 is the reference point for the alignment of the two pulse signals. The left and right sides respectively correspond to the time interval when the input signal STDP WL is earlier than the post-synaptic neuron pulse signal STDP BL (Δt > 0) and the time interval when the post-synaptic neuron pulse signal STDP BL is earlier than the input signal STDP WL (Δt < 0); V_PL is the voltage value on the platform voltage terminal V PL which can be regarded as the reference voltage level. The vertical axis represents the pulse voltage of the corresponding pulse signal. When the pulse voltage exceeds V_PL, the polarization direction of the ferroelectric layer changes significantly, thereby regulating the tunneling resistance state; when it is lower than V_PL, only partial polarization adjustment occurs, supporting multi-level resistance states.

[0101] If the first time point when the input signal STDP WL is transmitted into the ferroelectric tunneling junction FTJ is earlier than the second time point when the post-synaptic neuron pulse signal STDP BL is transmitted into the ferroelectric tunneling junction FTJ, it indicates that a larger tunneling current is allowed to pass at this time, which can enhance the activation probability of the post-synaptic neuron, that is, enhance the synaptic weight, triggering Figure 5 the LTP (Long-Term Potentiation) in Figure 5 and the weight (i.e., Δw / w in Figure 5 corresponding to the voltage value applied to the ferroelectric tunneling junction FTJ) increases. Among them, Figure 5 The curves in the LTP region represent different conductance values. In this embodiment, conductance values of 5 nS, 6 nS, 7 nS, 8 nS, 15 nS, and 21 nS are given. For example, when the conductance value is 21 nS and the time interval Δt = 100 ns, the corresponding weight is close to 10%, while when the conductance value is 5 nS and the time interval Δt = 100 ns, the corresponding weight is only about 20%.

[0102] It can be known that when the input signal STDP WL is earlier than the post-synaptic neuron pulse signal STDP BL, LTP will be triggered, and the forward voltage applied to the ferroelectric tunneling junction FTJ will be increased according to the conductance value of the ferroelectric tunneling junction FTJ and the time interval between the two pulse signals to make the polarization of the ferroelectric layer consistent with the electric field and reduce the resistance value of the tunneling resistance.

[0103] In a feasible implementation manner, step S30 may further include steps S33 to S34:

[0104] Step S33, if the third time point when the input signal STDP WL is transmitted into the ferroelectric tunneling junction FTJ is later than the fourth time point when the postsynaptic neuron pulse signal STDP BL is transmitted into the ferroelectric tunneling junction FTJ, the time interval is the negative time interval obtained by subtracting the third time point from the fourth time point.

[0105] Step S34, increase the reverse voltage applied to the ferroelectric tunneling junction FTJ according to the negative time interval, so as to increase the tunneling resistance.

[0106] If the fourth time point when the postsynaptic neuron pulse signal STDP BL is transmitted into the ferroelectric tunneling junction FTJ is earlier than the third time point when the second presynaptic neuron pulse signal is transmitted into the ferroelectric tunneling junction FTJ, it indicates that the tunneling current needs to be inhibited at this time, and the synaptic transmission efficacy is weakened, that is, the synaptic weight is inhibited, triggering Figure 5 the LTD (Long-Term Depression) in , and the weight decreases. For example, when the conductance value is 21 nS and the time interval Δt = -100 ns, the corresponding weight is close to -10%, and when the conductance value is 5 nS and the time interval Δt = -100 ns, the corresponding weight is only about 0%.

[0107] It can be known that when the postsynaptic neuron pulse signal STDP BL is earlier than the input signal STDP WL, LTD is triggered, and the reverse voltage applied to the ferroelectric tunneling junction FTJ is increased according to the conductance value of the ferroelectric tunneling junction FTJ and the time interval between the two pulse signals to determine the corresponding weight, so that the polarization of the ferroelectric layer is reversed and the resistance value of the tunneling resistance is increased.

[0108] Further explanation, according to Figure 4 and Figure 5 the waveforms of , it can be seen that the waveform curve in this embodiment suppresses the STDP learning window of the biological synapse, can simulate the timing priority learning characteristics of biological neurons, and at the same time, by setting the corresponding relationship between the time interval and the adjusted voltage amplitude, the progressive adjustment of the tunneling resistance is realized, and the online learning of the neural network is realized.

[0109] The present application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the control method in the first embodiment above.

[0110] Next, refer to Figure 6, which shows a schematic structural diagram of an electronic device suitable for implementing the embodiments of the present application. The electronic devices in the embodiments of the present application may include, but are not limited to, mobile terminals such as laptop computers, PDAs (Personal Digital Assistant), PADs (Portable Application Description: tablet computers), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device shown is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present application.

[0111] As Figure 6 shown, the electronic device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to the program stored in the read-only memory 1002 or the program loaded from the storage device 1003 into the random access memory 1004. In the random access memory 1004, various programs and data required for the operation of the electronic device are also stored. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other through a bus 1005. The input / output interface 1006 is also connected to the bus. Generally, the following systems may be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the electronic device to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows an electronic device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or had alternatively.

[0112] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart may be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program codes for performing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from the network through the communication device, or installed from the storage device 1003, or installed from the read-only memory 1002. When the computer program is executed by the processing device 1001, the above functions defined in the method of the embodiments disclosed in the present application are performed.

[0113] The electronic device provided by this application adopts the control method in the above embodiments, which can solve the technical problems of reading errors and application bottlenecks of pulse neural networks caused by the capacitance current characteristics and resistance current characteristics of ferroelectric tunneling junctions. Compared with the prior art, the beneficial effects of the electronic device provided by this application are the same as those of the control method provided by the above embodiments, and other technical features in this electronic device are the same as those disclosed in the method of the previous embodiment, and will not be elaborated here.

[0114] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0115] As described above, this is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

[0116] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the control method in the above embodiments.

[0117] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0118] The above computer-readable storage medium may be included in an electronic device; or it may exist independently without being assembled into the electronic device.

[0119] The above computer-readable storage medium carries one or more programs. When the above one or more programs are executed by an electronic device, the electronic device is caused to: generate a tunneling current when the voltage difference across the ferroelectric tunneling junction changes, control the internal capacitance in the ferroelectric tunneling junction to discharge, raise the voltage in the sub-synaptic circuit, and when receiving a pre-synaptic neuron pulse signal, output a charging voltage to the post-neuron circuit based on the voltage in the sub-synaptic circuit; control the post-neuron circuit to output a post-synaptic neuron pulse signal according to the accessed charging voltage; and change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, thereby modulating the tunneling resistance of the ferroelectric tunneling junction.

[0120] Computer program code for performing the operations of the present application may be written in one or more programming languages or combinations thereof. The above programming languages include object-oriented programming languages such as Java, Smalltalk, C++; and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, execute as a stand-alone software package, execute partially on the user's computer and partially on a remote computer, or execute entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by connecting through the Internet using an Internet service provider).

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions denoted in the blocks may occur in a different order than that denoted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0122] The modules described in the embodiments of the present application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0123] The readable storage medium provided by the present application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for executing the above control method, which can solve the technical problems of reading errors and application bottlenecks of pulse neural networks caused by the capacitive current characteristics and resistive current characteristics of ferroelectric tunneling junctions. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as those of the control method provided by the above embodiments, and will not be elaborated here.

[0124] The above are only some embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made using the specification and drawings of the present application under the technical concept of the present application, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A synaptic circuit for avoiding displacement current in a ferroelectric tunneling junction, characterized in that The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction includes: Multiple sub-synaptic circuits with the same structure. A ferroelectric tunneling junction is connected to the sub-synaptic circuit. The sub-synaptic circuit is used to generate a tunneling current when the voltage difference across the ferroelectric tunneling junction changes, control the internal capacitance in the ferroelectric tunneling junction to discharge, raise the voltage in the sub-synaptic circuit, and output a charging voltage based on the voltage in the sub-synaptic circuit when receiving a presynaptic neuron pulse signal; A post-neuron circuit, which is respectively connected to multiple sub-synaptic circuits. The post-neuron circuit is used to output a postsynaptic neuron pulse signal according to the applied charging voltage; The sub-synaptic circuit is also used to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the received postsynaptic neuron pulse signal and the input signal.

2. The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction according to claim 1, wherein The sub-synaptic circuit includes a first transistor and a second transistor; The input end of the first transistor is connected to the reset voltage terminal, the output end of the first transistor is connected to the cathode of the ferroelectric tunneling junction, the gate of the first transistor is used to receive an enabling reset signal, the input end of the second transistor is connected to the connection line between the first transistor and the ferroelectric tunneling junction, and the anode of the ferroelectric tunneling junction is connected to the platform voltage terminal. Wherein, the connection point of the first transistor and the second transistor is the first node; The sub-synaptic circuit is used to reset the voltage at the first node to the voltage value at the reset voltage terminal when the first transistor enters the conducting state according to the received enabling reset signal; The sub-synaptic circuit is also used to control the internal capacitance to discharge the first node and charge the voltage at the first node to the voltage value at the platform voltage terminal when the ferroelectric tunneling junction enters the discharging state according to the voltage value applied from the platform voltage terminal.

3. The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction according to claim 2, wherein The sub-synaptic circuit further includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The output end of the second transistor is connected to the control end of the fourth transistor, and the input end of the third transistor is connected to the connection line between the second transistor and the fourth transistor. The connection point of the second transistor and the fourth transistor is the second node; The input end of the fourth transistor is connected to the output end of the fifth transistor, the output ends of the fourth transistor and the third transistor are commonly grounded, the input ends of the fifth transistor and the sixth transistor are commonly connected to the power supply voltage terminal, and the control end of the sixth transistor is connected to the connection line between the fourth transistor and the fifth transistor; The control ends of the second transistor and the third transistor are used to receive the presynaptic neuron pulse signal, and the control end of the fifth transistor is used to receive the amplifier output voltage; The sub-synaptic circuit is further configured to generate the charging voltage based on the voltage at the first node and transmit it to the second node to control the fourth transistor to enter the conducting state when the second transistor and the third transistor enter the conducting state according to the received pre-synaptic neuron pulse signal; The sub-synaptic circuit is further configured to access a constant voltage through the conducting fifth transistor to amplify the charging voltage and output the amplified charging voltage when the fourth transistor and the sixth transistor enter the conducting state.

4. The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction according to claim 3, wherein The post-neuron circuit includes a storage capacitor, a first comparator, and a delay element; A first end of the storage capacitor is connected to an output end of the sixth transistor, a negative input end of the first comparator is connected to the first end of the storage capacitor, and an output end of the first comparator is connected to an input end of the delay element; The post-neuron circuit is configured to charge the storage capacitor based on the received charging voltage, cause the membrane potential at the negative input end of the first comparator to rise, and when the membrane potential rises to reach a threshold value, control the first comparator to output a digital pulse signal to the delay element, so that the delay element outputs the post-synaptic neuron pulse signal according to the digital pulse signal.

5. The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction according to claim 4, characterized in that, The sub-synaptic circuit further includes a seventh transistor; A control end of the seventh transistor is connected to an output end of the delay element, an input end of the seventh transistor is configured to access an input signal, and an output end of the seventh transistor is connected to a cathode of the ferroelectric tunneling junction; The sub-synaptic circuit is configured to change the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction through the seventh transistor.

6. A control method, characterized in that, The control method is applied to the synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction according to any one of claims 1 to 5. The synaptic circuit for avoiding the displacement current of the ferroelectric tunneling junction includes a sub-synaptic circuit and a post-neuron circuit, and the ferroelectric tunneling junction is disposed in the sub-synaptic circuit; The control method includes: Generating a tunneling current when the voltage difference across the ferroelectric tunneling junction changes, controlling the internal capacitor in the ferroelectric tunneling junction to discharge, raising the voltage in the sub-synaptic circuit, and outputting a charging voltage to the post-neuron circuit based on the voltage in the sub-synaptic circuit when receiving a pre-synaptic neuron pulse signal; Controlling the post-neuron circuit to output a post-synaptic neuron pulse signal according to the received charging voltage; Changing the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, thereby modulating the tunneling resistance of the ferroelectric tunneling junction.

7. The control method according to claim 6, wherein The step of changing the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the post-synaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction, thereby modulating the tunneling resistance of the ferroelectric tunneling junction includes: If the first time point at which the input signal is transmitted into the ferroelectric tunneling junction is earlier than the second time point at which the postsynaptic neuron pulse signal is transmitted into the ferroelectric tunneling junction, then the time interval is a positive time interval obtained by subtracting the first time point from the second time point; Increase the forward voltage applied to the ferroelectric tunneling junction according to the positive time interval, thereby reducing the tunneling resistance.

8. The control method according to claim 6, characterized in that, The step of modulating the tunneling resistance of the ferroelectric tunneling junction by changing the voltage amplitude applied across the ferroelectric tunneling junction according to the time interval between the postsynaptic neuron pulse signal and the input signal transmitted into the ferroelectric tunneling junction includes: If the third time point at which the input signal is transmitted into the ferroelectric tunneling junction is later than the fourth time point at which the postsynaptic neuron pulse signal is transmitted into the ferroelectric tunneling junction, then the time interval is a negative time interval obtained by subtracting the third time point from the fourth time point; Increase the reverse voltage applied to the ferroelectric tunneling junction according to the negative time interval, thereby increasing the tunneling resistance.

9. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the control method according to any one of claims 6 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the control method according to any one of claims 6 to 8 are implemented.

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