Memory and electronic equipment

Abstract

The invention provides a memory and electronic equipment, and relates to the technical field of memories. The memory comprises a memory array, an input / output circuit and a plurality of parallel data buses used for connecting the memory array and the input / output circuit, a part of the plurality of parallel data buses comprises a time delay circuit, and the time delay circuit is used for delaying data transmitted on the data bus where the time delay circuit is located, so that the time when adjacent data buses in the plurality of parallel data buses are overturned is different. According to the delay circuit disclosed by the invention, delay processing is carried out on part of the data bus, so that the signal transmission overturning moments on the data bus are staggered, and the influence of inter-line coupling capacitance is reduced, thereby avoiding wrong overturning of the signal on the data bus while ensuring the wiring overturning speed.

Description

Background Art

[0002] In the field of memory technology, memories such as Dynamic Random Access Memory (DRAM) generally include circuit units such as a memory array for storing data, a data input / output circuit, and related timing control circuits. In a memory chip, a relatively long path is often required for data transmission from the data input / output interface to the memory array, which is usually presented in the form of long traces in the layout. It should be noted that each memory array includes multiple banks, and each bank includes multiple memory cells for storing data.

[0003] However, the coupling capacitance between data lines increases with the increase in the trace length, thereby affecting the switching speed of the traces. In a more serious case, it may even cause incorrect switching of the signals on the data lines.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The present disclosure provides a memory and an electronic device, which at least reduce the influence of the inter-line coupling capacitance to a certain extent.

[0006] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be learned in part through the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, there is provided a memory, including: a memory array, an input / output circuit, and a plurality of parallel data buses for connecting the memory array and the input / output circuit; a part of the plurality of parallel data buses includes delay circuits, wherein the delay circuits are used to delay the data transmitted on the data buses where the delay circuits are located, so that the switching times of adjacent data buses in the plurality of parallel data buses are different.

[0008] In some exemplary embodiments of the present disclosure, all the odd-numbered data buses in the plurality of parallel data buses include delay circuits, and the delay circuits are used to perform the same delay on the data transmitted on each of the odd-numbered data buses, so that the switching times of the adjacent data buses are different.

[0009] In some exemplary embodiments of the present disclosure, all the even-numbered data buses among the multiple parallel data buses include delay circuits, and the delay circuits are configured to perform the same delay on the data transmitted on each of the even-numbered data buses, so that the adjacent data buses flip at different times.

[0010] In some exemplary embodiments of the present disclosure, the delay time of each of the delay circuits is greater than or equal to the time for the data bus where the delay circuit is located to flip from the first level or the second level to the intermediate level, and the intermediate level is 50% of the first level.

[0011] In some exemplary embodiments of the present disclosure, the delay time is the maximum value among the times for the data buses where the respective delay circuits are located to flip from the first level or the second level to the intermediate level.

[0012] In some exemplary embodiments of the present disclosure, the storage array includes a plurality of memory banks, where each memory bank corresponds to one of the multiple parallel data buses; the memory further includes latches and data selectors corresponding to each memory bank one by one. Each data bus includes a global input / output line, and each data selector is connected to the latch through the global input / output line.

[0013] In some exemplary embodiments of the present disclosure, the delay time of each of the delay circuits is less than the data update period of the data bus, so that the time when the data transmitted on the data bus including the delay circuit and the data bus without the delay circuit is valid together is greater than the minimum sampling window time of the latch.

[0014] In some exemplary embodiments of the present disclosure, the output signal of each of the delay circuits flips after a delay of the delay time at the enabling moment of the data loading enabling signal of each data selector.

[0015] In some exemplary embodiments of the present disclosure, delay circuits are provided on all the odd-numbered global input / output lines; or, delay circuits are provided on all the even-numbered global input / output lines.

[0016] In some exemplary embodiments of the present disclosure, each of the delay circuits includes an even number of inverters.

[0017] According to another aspect of the present disclosure, an electronic device is provided, including: the memory as described above.

[0018] In an embodiment of the present disclosure, the electronic device is a memory.

[0019] The present disclosure provides a memory and an electronic device, including a storage array, an input / output circuit, and a plurality of parallel data buses for connecting the storage array and the input / output circuit; a part of the plurality of parallel data buses includes a delay circuit, where the delay circuit is used to delay the data transmitted on the data bus where the delay circuit is located, so that the adjacent data buses among the plurality of parallel data buses have different moments of flipping. The delay circuit in the present disclosure performs delay processing on some data buses, staggering the moments when the signals on the data buses send flips, reducing the influence of the inter-line coupling capacitance, thereby avoiding incorrect flips of the signals on the data buses while ensuring the flipping speed of the traces.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 Layout schematic diagram showing a parallel data bus with increased static traces.

[0023] Figure 2 Schematic diagram showing the internal structure of the memory in an embodiment of the present disclosure.

[0024] Figure 3 Schematic diagram showing the connection relationship between the delay circuit and the data bus in an embodiment of the present disclosure.

[0025] Figure 4 Schematic diagram showing the delay circuit in an embodiment of the present disclosure.

[0026] Figure 5 Schematic diagram showing the connection relationship between the delay circuit and the data bus in another embodiment of the present disclosure.

[0027] Figure 6 Schematic diagram showing the delay circuit in another embodiment of the present disclosure.

[0028] Figure 7 Schematic diagram showing the memory in an embodiment of the present disclosure.

[0029] Figure 8 Schematic diagram showing the data IO path in an embodiment of the present disclosure.

[0030] Figure 9Shows the timing diagram of the memory when it is working in the embodiments of the present disclosure.

[0031] Figure 10 Shows the structural block diagram of an electronic device in the embodiments of the present disclosure. Detailed implementation manners

[0032] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete, and can fully convey the scope of the present disclosure to those skilled in the art.

[0033] The terms "first" and "second" in the text are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0034] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or communication with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0036] Memories such as dynamic random access memories generally include circuit units such as a memory array for storing data, data input / output circuits, and associated timing control circuits. Inside the memory chip, there is often a long path from the data input / output interface to the memory array storing data, which is usually presented in the form of long traces in the layout. However, the coupling capacitance between data lines increases as the trace length increases. For critical signals such as data buses, this coupling capacitance is fatal to the normal operation of the circuit: if one of the parallel traces flips or remains unchanged and the two adjacent traces flip in the opposite direction, the presence of the inter-line coupling capacitance will affect the flipping speed of this trace, and in a more serious case, it will cause the signal on this trace to flip incorrectly. For example, the flipping directions of odd and even data buses are different, the flipping directions of data bus 0 (even data bus) and data bus 1 (odd data bus) are different. When data bus 1 reverses and at the same time data bus 0 and data bus 2 both flip in the opposite direction, due to the presence of the inter-line coupling capacitance, the flipping speed of data bus 1 becomes slower and the signal on data bus 1 also flips incorrectly. Another example is that the data on data bus 0 is 0 and data bus 0 does not flip, and the data on data bus 1 flips from 0 to 1. Due to the presence of the inter-line coupling capacitance, the signal on data bus 0 is prone to flip incorrectly.

[0037] As Figure 1 shown, taking 4 parallel data buses as an example, static traces (referred to as static traces) are inserted between the data buses, so that the data buses that flip simultaneously can be isolated, reducing the data flipping problem caused by the coupling capacitance between the data buses. However, for n parallel data buses, n - 1 static traces need to be inserted, where n is a positive integer, and the number of tracks increases sharply, requiring a large layout area to implement. It cannot meet the requirements of the semiconductor industry for small areas of memories.

[0038] To prevent the above situation from occurring and causing abnormal operation of the circuit, and to be able to exchange a small layout area for correct data flipping, the present disclosure proposes a memory for reducing data bus coupling inside the memory.

[0039] The following will describe this exemplary embodiment in detail with reference to the accompanying drawings and embodiments.

[0040] Figure 2 shows a schematic diagram of the internal structure of the memory in the embodiment of the present disclosure. As Figure 2As shown in the figure, the memory 10 provided in the embodiments of the present disclosure may include: a storage array 101, an input / output circuit 102, and multiple parallel data buses for connecting the storage array and the input / output circuit; some of the multiple parallel data buses may include a delay circuit 103, where the delay circuit 103 may be used to delay the data transmitted on the data bus where the delay circuit 103 is located, so that the adjacent data buses among the multiple parallel data buses have different moments of inversion.

[0041] It should be noted that a chip refers to a single chip obtained by cutting a wafer during the semiconductor manufacturing process. The storage array of the chip may include multiple memory banks, and each memory bank may include multiple memory cells (Cells) composed of word lines (WordLine, WL) and bit lines (Bit Line, BL) for storing data. The aforementioned storage array is connected to the input / output circuit through a data bus. Multiple storage arrays may be included on the memory, for example, 2. Regarding the number of memory banks included in each storage array, the present disclosure does not make any limitations. For example, it may include 8 memory banks or may also include 16 memory banks.

[0042] In the embodiments of the present disclosure, since a delay circuit is connected to some of the data buses, the signal inversion on the data buses connected with the delay circuit can be delayed. The signals on the data buses without the delay circuit are inverted normally, so that the signals on the data buses connected with the delay circuit and the signals on the data buses without the delay circuit have staggered inversion moments, thereby reducing the influence of the inter-line coupling capacitance. It can achieve avoiding incorrect signal inversion on the data buses while ensuring the inversion speed of the traces.

[0043] Furthermore, in the embodiments of the present disclosure, by adding a delay circuit to reduce the influence of the inter-line coupling capacitance, compared with adding static traces to reduce interference, the layout area can be reduced. That is to say, the layout area increased due to adding the delay circuit in the present disclosure is smaller than the layout area that needs to be increased due to adding static traces.

[0044] The connection position of the delay circuit will be described below.

[0045] In an exemplary embodiment, all the odd-numbered data buses among the multiple parallel data buses may include a delay circuit, and the delay circuit is used to perform the same delay on the data transmitted on each odd-numbered data bus, so that the adjacent data buses have different moments of inversion.

[0046] Exemplarily, such as Figure 3As shown, the odd-numbered data buses are respectively data bus 1, data bus 3, data bus 5, …, data bus 2n - 1. The odd-numbered data buses are connected to the delay circuits, which are used to perform the same delay on the data transmitted on the odd-numbered data buses, so that the adjacent data buses have different moments of flipping, thereby reducing the inter-line coupling capacitance.

[0047] In one embodiment, the delay time of each delay circuit is greater than or equal to the time for the data bus where the delay circuit is located to flip from the first level or the second level to the intermediate level, and the intermediate level is 50% of the first level.

[0048] In the embodiments of the present disclosure, the first level is greater than the intermediate level, and the intermediate level is greater than the second level. The present disclosure embodiments do not limit what specific levels the first level and the second level are. For example, the first level can be the power supply level, the second level can be the ground level, and the intermediate level is 50% of the first level.

[0049] It should be noted that the delay time of each delay circuit is greater than or equal to the time for the data bus where the delay circuit is located to flip from the first level or the second level to the intermediate level. That is to say, the delay setting of the delay circuit: according to the time for the data bus to flip from the power supply level or the ground level to 50% or more of the power supply level. Flipping to 50% or more can represent that the signal is stable and is hardly affected by the flipping direction of adjacent signals.

[0050] The present disclosure embodiments do not limit what specific circuit the delay circuit is. For example, each delay circuit can include an even number of inverters. Exemplarily, as Figure 4 shown, the odd-numbered data buses are respectively data bus 1, data bus 3, data bus 5, …, data bus 2n - 1, and each odd-numbered data bus is connected to a delay circuit, and each delay circuit is formed by stacking 4 inverters.

[0051] The embodiments of the present disclosure perform delay processing on a part of the signals by using delay circuits, and the delay time is greater than or equal to the time for the data bus where the delay circuit is located to flip from the first level or the second level to the intermediate level, which improves the stability of the signals and is not easily affected by the flipping direction of adjacent signals. Further reduces the influence of inter-line coupling capacitance.

[0052] In another embodiment, the delay time takes the maximum value among the times for the data buses where the respective delay circuits are located to flip from the first level or the second level to the intermediate level.

[0053] It should be noted that the flipping time may have slight differences according to different surrounding / upper and lower layer wiring environments. If the differences are large, the slowest flipping time can be taken as the delay time.

[0054] In the embodiments of the present disclosure, the delay time is taken as the maximum value among the times when the data buses where each delay circuit is located flip from the first level or the second level to the intermediate level, so as to ensure that the delay times of all odd-numbered data buses are the same, and further ensure the accuracy of later data reading.

[0055] In the embodiments of the present disclosure, since the odd-numbered data buses are connected to the delay circuits, the delay circuits delay the data on the odd-numbered data buses, so that the flip moments of the signals on the odd-numbered data buses are staggered from the data on the even-numbered data buses, thereby reducing the influence of the inter-line coupling capacitance. It can be realized that while ensuring the flip speed of the traces, the signals on the data buses are prevented from flipping erroneously. In addition, the layout area that needs to be increased in the embodiments of the present disclosure is small.

[0056] In another exemplary embodiment, all even-numbered data buses among multiple parallel data buses include delay circuits, and the delay circuits are used to perform the same delay on the data transmitted on each even-numbered data bus, so that the flip moments of adjacent data buses are different.

[0057] Exemplarily, as Figure 5 shown, the even-numbered data buses are respectively data bus 0, data bus 2, data bus 4,..., data bus 2n. The odd-numbered data buses are respectively data bus 1, data bus 3, data bus 5,..., data bus 2n - 1. The even-numbered data buses 0 / 2 / 4 / …… / 2n are delayed in the delay circuit and then transmitted, and the odd-numbered data buses 1 / 3 / 5 / …… / 2n - 1 are directly transmitted without processing, so that the flip moments of the signals on the odd-numbered data buses and the even-numbered data buses are staggered, and the influence of adjacent buses on each other in the case of simultaneous flipping can be reduced to a certain extent.

[0058] In one embodiment, the delay time of each of the foregoing delay circuits is greater than or equal to the time when the data bus where the delay circuit is located flips from the first level or the second level to the intermediate level, and the intermediate level is 50% of the first level.

[0059] In the embodiments of the present disclosure, the first level, the second level, and the intermediate level are similar to those in the foregoing embodiment of setting delay circuits on the odd-numbered data buses, and will not be elaborated here.

[0060] Regarding what specific circuit the delay circuit is, the embodiments of the present disclosure do not make any limitations. For example, each delay circuit may include an even number of inverters. Exemplarily, as Figure 6 shown, the even-numbered data buses are respectively data bus 0, data bus 2, data bus 4,..., data bus 2n, and a delay circuit is connected to each even-numbered data bus, and each delay circuit is formed by stacking 4 inverters.

[0061] In the embodiments of the present disclosure, a delay circuit is used to delay a part of signals, and the delay time is greater than or equal to the time when the data bus where the delay circuit is located flips from the first level or the second level to the intermediate level, which improves the stability of the signals and is not easily affected by the flipping direction of adjacent signals. Further, the influence of the inter-line coupling capacitance is reduced.

[0062] In another embodiment, the delay time is taken as the maximum value among the times when the data buses where the respective delay circuits are located flip from the first level or the second level to the intermediate level.

[0063] It should be noted that the flipping time may have slight differences according to different surrounding / upper and lower layer routing environments. If the difference is large, the slowest flipping time can be taken as the delay time.

[0064] In the embodiments of the present disclosure, the delay time is taken as the maximum value among the times when the data buses where the respective delay circuits are located flip from the first level or the second level to the intermediate level, so as to ensure that the delay times of the even-numbered data buses are the same, and further ensure the accuracy of later data reading.

[0065] In the embodiments of the present disclosure, for multiple parallel data buses, a part of them are separately delayed so that they do not flip simultaneously, in order to reduce the inter-line coupling influence during flipping.

[0066] It should be noted that the above two exemplary embodiments are only two actual ways of the present disclosure, and there is no limitation on which data buses are specifically selected for delay processing.

[0067] Next, the location where the data bus is located will be described.

[0068] In an exemplary embodiment, the storage array may include multiple memory banks, where each memory bank corresponds to a plurality of parallel data buses one by one; the memory may further include latches and data selectors corresponding to each memory bank one by one, where each data bus includes a global input / output line, and each data selector is connected to the latch through the global input / output line.

[0069] Exemplarily, such as Figure 7As shown, the memory includes eight memory banks 701. Each memory bank 701 may include multiple memory cells (Cells) formed by word lines and bit lines, and eight LIOS (Local I / Os), that is, each memory bank 701 can output 8-bit data in parallel. Each memory bank 701 is connected to a multiplexer (MUX) 703 through multiple parallel data buses. It should be noted that a second sense amplifier (SSA, Second Sensor Amplifier) 702 may be connected between the memory bank and the multiplexer. The data read from the memory bank can be output first, and the read data passes through the first sense amplifier, the second sense amplifier inside the memory bank, and the multiplexer to reach the latch 704, and then is output to the DQ (data input / output) pads 705.

[0070] It should be noted that the second sense amplifier is an amplification circuit at the bank level. Based on the first sense amplifier SA (Sense amplifier, not shown) on the bit line in the memory bank, it further amplifies the data read from the memory bank to the full swing, and then sends it to the multiplexer 703. The multiplexer 703 can control the reading and writing of data through the selection control signals RDEN (read enable signal) and WREN (write enable signal). The multiplexer 703 includes AND logic. When the read control signal RDEN is pulled high, the read control signal RDEN and the read data are AND-operated and then output to the latch 704. The multiplexer 703 also selects to output the latch enable signal output by the delay unit as shown to the latch 704. In the embodiment of the present disclosure, the reading time of the memory bank can be adjusted by adjusting the delay unit, so that the reading times of the above eight memory banks tend to be consistent. Figure 7 It should be noted that the delay unit is different from the delay circuit of the present disclosure. The delay unit is connected between the memory bank and the multiplexer, while the delay circuit of the present disclosure is connected to the data bus.

[0071] Exemplarily, referring to

[0072] As shown, after the data is read from the memory cells of the memory bank 701, it is sent from the bit line (Bit Line, BL) to the LIO (Local I / O, LIO is the internal data bus of the memory bank 701) after being amplified by the first sense amplifier SA. First, it passes through the LSA inside the memory bank (not shown in Figure 7 the figure). Figure 7As shown, the LSA is an in - memory data strobe circuit. In some embodiments, there may also be no LSA. The data is sent from the memory bank 701 to the MIO (the data bus coupling the memory bank 701 and the data selector 703), then amplified to full swing by the second sense amplifier SSA 702, and then processed by the data selector 703 for precharge - evaluate (a read operation of a memory). As Figure 8 shown, after receiving the raised RDEN signal, the data selector 703 latches the read data and then sends it to the latch 704 via the GIO (Globle IO, the data bus between the MUX703 and the latch 704). Subsequently, it undergoes parallel - to - serial conversion (P2S) and impedance matching (OCD), and finally outputs the data to the DQ pad 705 (P2S and OCD are not shown in the figure).

[0073] The data selector 703 selects RDEN and WREN to control whether the data is read or written. The Mux module also includes AND logic, which performs an operation on RDEN / WREN and the data and then gives the result to the latch 704.

[0074] It should be noted that the complete layout trace of the data is from BL to LIO, then to MIO, and then to GIO (which can also be called the datapath, the global input - output line). Both LIO and MIO are relatively short, and only the trace of GIO is the longest. The embodiments of the present disclosure mainly focus on the improvement of this section of GIO from the MUX 703 to the latch 704. That is to say, a delay circuit is added to part of the data bus of GIO, but the present disclosure is not limited to this.

[0075] In the embodiments of the present disclosure, by connecting a delay circuit to part of the data bus of the global input - output line GIO, delay processing is performed on part of the data bus, so that their inversion times are staggered, reducing the influence of inter - wire coupling, and to a certain extent reducing the influence of inter - wire coupling on data transmission. That is to say, the present disclosure can stagger the inversion times of the signals on the data bus connected with the delay circuit and the signals on the data bus without the connected delay circuit, thereby reducing the influence of the inter - wire coupling capacitance. It can achieve avoiding incorrect signal inversion on the data bus while ensuring the inversion speed of the trace.

[0076] Furthermore, in the embodiments of the present disclosure, by adding a delay circuit to reduce the influence of the inter - wire coupling capacitance, compared with adding static traces to reduce interference, the layout area can be reduced. That is to say, the layout area increased due to adding the delay circuit in the present disclosure is less than the layout area that needs to be increased due to adding static traces.

[0077] In another exemplary embodiment, the delay time of each delay circuit is less than the data update period of the data bus, such that the time when the data transmitted on the data bus including the delay circuit and the data bus without the delay circuit are both valid is greater than the minimum sampling window time of the latch 704.

[0078] In the embodiments of the present disclosure, the meaning of the data update period is the time taken by one read / write operation to occupy the datapath. The minimum value of the data update period is tccd_s (CAS-to-CAS delay, the time interval between CAS (Column Address Strobe) commands) specified in the datasheet of the memory. If the time exceeds this value, the next read / write data will occupy the data bus.

[0079] It should be noted that, in order to ensure the correctness of the data, in an embodiment of the present disclosure, it is necessary to ensure that the delay time generated by the delay circuit is less than the aforementioned data update period. That is to say, the delay time of the data by the aforementioned delay circuit needs to be controlled within tccd_s. That is, within tccd_s, a data read operation and the latching operation of the latch 704 can be completed to ensure the correctness of the data. The time when the data transmitted on the data bus connected to the delay circuit and the data bus not connected to the delay circuit are both valid needs to be greater than the setup-hold time (also referred to as the minimum sampling window time) of the latch 704, so as to ensure that all signals on all data buses (including the data bus with the delay circuit set and the data bus without the delay circuit set) can be latched simultaneously when the latch 704 is enabled.

[0080] In an embodiment, the output signals of each delay circuit are inverted after delaying the aforementioned delay time at the enabling moment of the data loading enabling signal (such as the aforementioned read enabling signal RDEN) of each data selector MUX 703.

[0081] In the embodiments of the present disclosure, the data loading enabling signal can align the data on a group of data buses and then output it to the input of the next-stage circuit (delay voltage). The data loading enabling signal is the data loading enabling signal of the circuit module at the previous stage of the delay circuit. Exemplarily, the data loading enabling signal can be the RDEN (read enabling) and / or WREN (write enabling) signal of the data selector, and the present disclosure is not limited thereto.

[0082] It should be noted that in the previous circuit module of the delay circuit, the data on a group of data buses arrives at different speeds (without a certain pattern). Through a relatively late data release enable signal, the data on the group of data buses is aligned and then released to the input of the next-level circuit during its valid period. That is to say, in an embodiment of the present disclosure, the effective level overlap window of the data on the two types of data buses with and without the delay circuit is greater than the setup-hold time of the latch 704 (which can also be referred to as the minimum sampling window time), so that all the signals on the data buses can be locked simultaneously when the latch 704 is enabled.

[0083] Exemplarily, referring to Figure 9 , Figure 9 For the time of two pens of read / write data, the previous-stage circuit (data selector) of the delay circuit periodically outputs a data release enable signal, and the output signals of each delay circuit are inverted after a delay time at the enabling moment of the data release enable signal of each data selector. Corresponding to Figure 6 the example, delay circuits are added to data buses 0 / 2 / 4 / ... / 2n, and the delay magnitude is the time for the data bus to flip from the power supply level or the ground level to 50% of the power supply level.

[0084] The subsequent-stage circuit of the delay circuit (such as the latch 704) periodically samples, and the sampling time can be the aforementioned minimum sampling window time. The delay time of each delay circuit is less than the data update period of the data bus, so that the common valid time of the data transmitted on the data bus including the delay circuit and the data bus without the delay circuit is greater than the minimum sampling window time of the latch 704.

[0085] It should be noted that the present disclosure embodiment does not limit the latching form of the latch 704, which can be a latch (such as a high-pass low-lock latch) or a D flip-flop DFF.

[0086] Exemplarily, referring to Figure 6 and Figure 7 for Figure 9 the timing is described. A delay circuit is added to the even-numbered data buses. When the data is sent out from the MUX 703 of Figure 7 , the data is placed on the data bus by the data release enable (RDEN) spaced by tccd_s (corresponding to Figure 9Align them on the first - group data - bus schematic diagram. At the rising edge of the output data enable (RDEN) of the MUX 703, the signals on all data buses are flipped simultaneously. The signals on the odd - numbered data buses and the even - numbered data buses are flipped in opposite directions. The delay circuit delays the signals on the even - numbered data buses, and the delay time is the time when the data bus flips from the power supply level or the ground level to 50% of the power supply level. The common valid time of the odd - numbered data buses and the even - numbered data buses is greater than the minimum sampling window time of the latch 704. When the latch 704 is enabled, it latches the signals on all data buses.

[0087] It should be noted that the data update period (such as tccd_s) is the interval between two adjacent data enables. The common valid time is the time when the valid levels of the data on the two types of data buses with and without the delay circuit overlap. The original common valid time is the time when the valid levels of the data on the data buses in the pre - stage circuit of the delay circuit overlap. Among them, the common valid time is the difference between the original valid time and the delay time.

[0088] In the embodiments of the present disclosure, the latch 704 can latch the data on all data buses within the common valid time. The value of the common valid time in the embodiments of the present disclosure is not limited, as long as it meets the setup - hold timing requirements of the latch 704. In one embodiment, the aforementioned common valid time needs to be greater than the minimum sampling window time of the latch 704 to ensure that the latch 704 can latch the data on all data buses during the common valid period.

[0089] In another embodiment, delay circuits are provided on all odd - numbered global input - output lines; or, delay circuits are provided on all even - numbered global input - output lines.

[0090] In the embodiments of the present disclosure, whether delay circuits are provided on odd - numbered global input - output lines or on even - numbered global input - output lines, the flipping moments of the signals on adjacent two data buses can be staggered, reducing the influence of inter - line capacitance coupling. And the increase in layout area is relatively small.

[0091] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuit", "module", or "system" here.

[0092] In addition, the embodiments of the present disclosure also provide an electronic device.

[0093] Figure 10 The structural schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. As Figure 10 shown, the electronic device 100 includes a memory 1001.

[0094] Among them, the memory 1001 can be any one of the memories shown in the above embodiments shown in combination with Figures 2 - 9 the above embodiments.

[0095] Exemplarily, the electronic device 100 can be a terminal device such as a mobile phone or a computer, or a network device such as a server, and no specific limitation is made thereto.

[0096] Another exemplarily, the electronic device can be a memory. The memory can be a non-volatile memory or a volatile memory. Among them, the non-volatile memory includes flash memories such as NOR Flash and NAND Flash, or includes read-only memories such as PROM (Programmable Read-Only Memory), EAROM (Electrically Alterable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory). The volatile memory can be DRAM, SDRAM (Synchronous Dynamic RAM), or PSRAM (Pseudo Static RAM).

[0097] Yet another exemplarily, the electronic device 100 can include a memory, where the memory delays the signals on part of the data bus by a delay circuit. The memory can refer to the relevant descriptions in the above part of the embodiments of the present disclosure and will not be elaborated here.

[0098] It should be clear that each embodiment in this specification is described in a progressive manner. The same or similar parts between each embodiment can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. The present disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of the present disclosure. And, for the sake of brevity, the detailed descriptions of known technologies are omitted here.

[0099] In several embodiments provided by the present disclosure, it should be understood that the disclosed circuits, units, and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some ports. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0100] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, in each embodiment of the present disclosure, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0102] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure.

[0103] Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims. The present disclosure aims to cover any variations, uses, or adaptable changes of the present disclosure, which follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The description and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A memory, characterized in that, Comprising: A storage array, input / output circuitry, and a plurality of parallel data buses for connecting the storage array and the input / output circuitry; Some of the plurality of parallel data buses include delay circuits, wherein, The delay circuit is configured to delay the data transmitted on the data bus where the delay circuit is located, so that the adjacent data buses among the plurality of parallel data buses have different inversion times.

2. The memory according to claim 1, wherein All odd-numbered data buses among the plurality of parallel data buses include delay circuits, and the delay circuits are configured to perform the same delay on the data transmitted on each of the odd-numbered data buses, so that the adjacent data buses have different inversion times.

3. The memory according to claim 1, wherein All even-numbered data buses among the plurality of parallel data buses include delay circuits, and the delay circuits are configured to perform the same delay on the data transmitted on each of the even-numbered data buses, so that the adjacent data buses have different inversion times.

4. The memory according to any one of claims 1-3, characterized in that, The delay time of each of the delay circuits is greater than or equal to the time for the data bus where the delay circuit is located to flip from the first level or the second level to the intermediate level, and the intermediate level is 50% of the first level.

5. The memory according to claim 4, wherein The delay time takes the maximum value among the times for the data buses where each of the delay circuits is located to flip from the first level or the second level to the intermediate level.

6. The memory according to claim 1, wherein The storage array includes a plurality of memory banks, wherein each memory bank corresponds to one of the plurality of parallel data buses; The memory further includes latches and data selectors corresponding to each memory bank, wherein each data bus includes a global input / output line, and each data selector is connected to the latch through the global input / output line.

7. The memory according to claim 6, wherein The delay time of each of the delay circuits is less than the data update period of the data bus, so that the time when the data transmitted on the data bus including the delay circuit and the data bus without the delay circuit are both valid is greater than the minimum sampling window time of the latch.

8. The memory according to claim 6, wherein The output signal of each of the delay circuits flips after delaying the delay time at the enabling moment of the data loading enabling signal of each data selector.

9. The memory according to claim 7, wherein Delay circuits are provided on all odd-numbered global input / output lines; or delay circuits are provided on all even-numbered global input / output lines.

10. The memory according to claim 1, characterized in that, Each of the delay circuits includes an even number of inverters.

11. An electronic device, characterized in that, A memory comprising the memory according to any one of claims 1 to 10.

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