Wafer level screening test method and system of built-in RRAM microcontroller

Abstract

The invention belongs to the technical field of chip screening and testing, particularly relates to a wafer level screening and testing method and system for a microcontroller with a built-in RRAM, and aims to solve the problem that an efficient production screening method for the microcontroller with the built-in RRAM is not perfect. According to the connection test, connectivity verification is carried out on all PADs of a tested crystal grain, an electrical parameter test is carried out if the verification is passed, input and output electrical parameters of the tested crystal grain are tested, a function test is carried out if the verification is passed, test verification is carried out on a basic instruction and peripheral operation of the tested crystal grain, an RRAM initialization test is carried out if the verification is passed, and iteration forming is carried out on the tested crystal grain. Performing RRAM read-write test, iteratively writing 0 and 1 on the produced crystal grains and verifying the correctness, and if all the test processes pass, judging that the screening process of the currently tested built-in RRAM microcontroller crystal grains is completed. According to the invention, the wafer level of the microcontroller with the built-in RRAM is rapidly screened.

Description

Technical Field

[0001] The invention belongs to the technical field of chip screening and testing, and in particular relates to a wafer-level screening and testing method and system for a built-in RRAM microcontroller. Background Art

[0002] Resistive random access memory (RRAM) is a new type of non-volatile memory with the characteristics of fast operation speed, low power consumption and high integration. Based on the resistive random access structure, the resistive random access memory can change the resistance value by applying different voltages. Its resistance state is divided into high resistance state (HRS) and low resistance state (LRS), corresponding to digital logic 1 and logic 0 respectively. Both the high resistance state and the low resistance state have a certain range of process fluctuations, and the resistance state transition of the resistive random access structure is unstable.

[0003] For the wafer-level production of microcontrollers with built-in RRAM, on the one hand, it is necessary to test and verify the basic functions and electrical parameters of the microcontrollers to quickly screen out functionally defective products; on the other hand, it is necessary to efficiently complete the production and basic operation verification of the RRAM program memory.

[0004] At present, the efficient production screening method for microcontrollers with built-in RRAM is still imperfect. How to quickly evaluate the impact of process fluctuations on the functional reliability of microcontrollers with built-in RRAM, achieve efficient testing of the basic functions and electrical parameters of microcontrollers, and complete the production and basic operation verification of RRAM memory are technical problems that need to be solved urgently in this field. Summary of the invention

[0005] In order to solve the above-mentioned problem in the prior art, that is, the problem that the efficient production screening method of the microcontroller with built-in RRAM is still imperfect, the first aspect of the present invention proposes a wafer-level screening test system for the microcontroller with built-in RRAM, including host computer vector test software, a test machine, and a microcontroller grain with built-in RRAM;

[0006] The host computer vector test software generates a test instruction and sends it to the test machine;

[0007] The test machine applies the test instruction to the built-in RRAM microcontroller die for testing, and monitors the test data of the built-in RRAM microcontroller die;

[0008] The test machine feeds back the test data to the host computer vector test software for processing and analysis to obtain test results.

[0009] In some preferred embodiments, the built-in RRAM microcontroller die includes RRAM cells, and the RRAM cells include a field-effect transistor T0 and a resistive switching device R0;

[0010] The field-effect transistor T0 includes an N-type field-effect transistor and a P-type field-effect transistor;

[0011] The first pole of the field-effect transistor T0 is connected to the SL terminal, the second pole of the forward operation terminal of the resistive switching device is connected to the BL terminal, the third pole of the reverse operation terminal of the resistive switch is connected to the transistor device terminal, and the word line WL and the gate of the field-effect transistor T0 are the fourth pole;

[0012] Apply a write pulse to the second pole and a write gate voltage pulse to the fourth pole to initialize the on-chip RRAM;

[0013] Apply a write pulse to the second pole and a write gate voltage pulse to the fourth pole to write to the on-chip RRAM;

[0014] Apply a read pulse to the second pole and a write gate voltage pulse to the fourth pole to read the on-chip RRAM.

[0015] The second invention of the present invention proposes a wafer-level screening and testing method for a built-in RRAM microcontroller, based on the wafer-level screening and testing system for a built-in RRAM microcontroller, including the following steps:

[0016] Step 1: Execute a preset test process on the built-in RRAM microcontroller die, and sequentially determine whether each test process passes; the test process includes connection testing, electrical parameter testing, function testing, RRAM initialization testing, and RRAM read / write testing;

[0017] Step 2: If all preset test processes pass, determine that the currently tested built-in RRAM microcontroller die is a qualified product and pass the screening process; if any preset test process fails, immediately determine that the currently tested built-in RRAM microcontroller die is a non-qualified product and does not pass the screening process;

[0018] Step 3: After completing the screening process of the currently tested built-in RRAM microcontroller die, the testing machine automatically switches to the next built-in RRAM microcontroller die;

[0019] Step 4: Repeat steps 1-3 until the screening of all built-in RRAM microcontroller dies on the entire wafer is completed.

[0020] In some preferred embodiments, the connection test is configured as follows: Apply a test signal to all PADs of the currently tested built-in RRAM microcontroller die; Monitor whether the test machine receives normal feedback signals from all PADs. If all PADs can be normally connected and feedback signals, it is determined that the currently tested built-in RRAM microcontroller die passes the connection test, and the electrical parameter test is performed; If any PAD cannot be normally connected or does not feedback a signal, it is determined that the currently tested built-in RRAM microcontroller die fails the connection test.

[0021] In some preferred embodiments, the electrical parameter test is configured as follows: Apply a test vector to the currently tested built-in RRAM microcontroller die, and monitor the test results feedback by the test machine; Based on the test results, if all test vectors pass the verification, it is determined that the currently tested built-in RRAM microcontroller die passes the electrical parameter test, and the function test is performed; If any test electrical vector fails to pass the verification, it is determined that the currently tested built-in RRAM microcontroller die fails the electrical parameter test;

[0022] The test vectors include output high-level voltage, output low-level voltage, input high-level voltage, input low-level voltage, input high-level leakage current, input low-level leakage current, and high-low level conversion current.

[0023] In some preferred embodiments, the function test is configured as follows: Apply a function test vector to the currently tested built-in RRAM microcontroller die, and monitor the test results feedback by the test machine. Based on the test results, if all function vectors can pass the verification, it is determined that the function test passes, and the RRAM initialization test is performed. Otherwise, it is determined that the function test fails;

[0024] The microcontroller operates in an off-chip mode;

[0025] The function test vectors include basic instruction tests and peripheral function tests.

[0026] In some preferred embodiments, the RRAM initialization test includes the following steps:

[0027] CS1, The host computer vector test software generates and sends the test vectors for RRAM initialization to the test machine, and the test machine then applies the initialized test vectors to the currently tested built-in RRAM microcontroller die, and the microcontroller operates in the programming mode;

[0028] CS2, Perform a full-address read operation on the currently tested built-in RRAM microcontroller die;

[0029] CS3, according to the read operation result, perform a forming operation on all high-impedance cells and perform a no-operation on low-impedance cells;

[0030] CS4, under different operating conditions 1-m, repeatedly perform the above full-address read operation and the corresponding forming operation or no-operation;

[0031] CS5, after completing m operations, perform a full-address read operation again and calculate the production success rate of the currently tested built-in RRAM microcontroller die;

[0032] CS6, if the production success rate of the currently tested built-in RRAM microcontroller die exceeds X%, it is determined that the current RRAM test die passes the initialization test and perform an RRAM read / write test; otherwise, it is determined that the current RRAM test die fails the initialization test.

[0033] In some preferred embodiments, the RRAM read / write test includes the following steps:

[0034] DX1, the host computer vector test software generates and sends read / write test vectors to the currently tested built-in RRAM microcontroller die, and the microcontroller operates in the programming mode;

[0035] DX 2, under different operating conditions 1-n, perform continuous full-address iterative write 0 and iterative write 1 operations on the currently tested built-in RRAM microcontroller die, and calculate the production success rate of the currently tested built-in RRAM microcontroller die after each iteration;

[0036] DX 3, if the success rates of all iterative write 0 and iterative write 1 operations can exceed Y%, it is determined that the current RRAM test die passes the read / write test and it is determined that the currently tested built-in RRAM microcontroller die is a qualified product and passes the screening process; otherwise, it is determined that the current RRAM test die fails the read / write test.

[0037] In some preferred embodiments, it further includes further optimization and call of the vectors for full-address writing, specifically:

[0038] Before each iterative write operation, perform a full-address iterative read operation, and judge the read result in groups of K bits;

[0039] If all cells in a group need to perform a write operation, directly call the K-bit write operation vector;

[0040] If there are cells that do not need to perform a write operation in a group of cells, call the 1-bit write operation vector in sequence according to the test result.

[0041] In some preferred embodiments, the value of K is set according to the process characteristics and error correction capabilities of the built-in RRAM microcontroller.

[0042] Advantages of the present invention:

[0043] Formulate a preset test process: connection test, electrical parameter test, function test, RRAM initialization test, RRAM read / write test. After each process is completed, there will be a result indicating whether the process passes. If it passes, the tests are carried out one by one in sequence. If all the preset test processes pass, it is determined that the currently tested microcontroller is a qualified product and passes the screening process; if any one of the preset test processes fails, it is immediately determined that the currently tested microcontroller is a non-qualified product and does not pass the screening process, thereby realizing rapid screening of the wafers of the microcontroller with built-in RRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] By reading the detailed description of the non-restrictive embodiments with reference to the following drawings, other features, objectives, and advantages of the present application will become more apparent:

[0045] Figure 1 is the preset test flow chart of a wafer-level screening and testing method for a microcontroller with built-in RRAM according to the present invention;

[0046] Figure 2 is the schematic diagram of the RRAM unit structure according to the present invention;

[0047] Figure 3 is the further optimization and call flow chart of the vector for full-address writing according to the present invention.

[0048] Figure 4 is the block diagram of the structure of a wafer-level screening and testing system for a microcontroller with built-in RRAM according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The following further elaborates on the present application with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention and are not intended to limit the invention. Additionally, it should be noted that for the sake of description, only parts related to the relevant invention are shown in the drawings.

[0050] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0051] To more clearly illustrate a method for implementing a distributed seat free layout of the present invention, the following combines Figures 1 to 4 elaborates on each step in the embodiments of the present invention in detail.

[0052] A wafer-level screening and testing system for an embedded RRAM microcontroller according to the first embodiment of the present invention, refer to Figure 4 , comprising a host computer vector test software, a test machine, and an embedded RRAM microcontroller die. The host computer vector test software generates and sends test instructions to the test machine;

[0053] The test machine applies the test instructions to the embedded RRAM microcontroller die for testing and monitors the test data of the embedded RRAM microcontroller die;

[0054] The test data is fed back to the host computer vector test software for processing and analysis to obtain a test result;

[0055] In this embodiment, refer to Figure 2 , the embedded RRAM microcontroller die includes RRAM cells. The RRAM cell includes a field effect transistor T0 and a resistive switching device R0. Here, it should be noted that the embedded RRAM microcontroller die is a chip before packaging. There are several dice on a wafer. The embedded RRAM microcontroller is a part of the chip. The embedded RRAM microcontroller includes two major parts: an RRAM array and a microcontroller. The RRAM array is composed of multiple RRAM cells. The RRAM array is also equivalent to the on-chip RRAM;

[0056] The field effect transistor T0 includes an N-type field effect transistor and a P-type field effect transistor;

[0057] The first pole of the field effect transistor T0 is connected to the SL terminal, the positive operation terminal of the resistive switching device is connected to the BL terminal as the second pole, the reverse operation terminal of the resistive switch is connected to the transistor connection terminal as the third pole, and the word line WL is connected to the gate of the field effect transistor T0 as the fourth pole;

[0058] Applying a write pulse to the second pole and a write gate voltage pulse to the fourth pole, the on-chip RRAM is initialized. The write pulse is a pulse with an amplitude V F and a pulse width P F . The write gate voltage pulse is a pulse with an amplitude V gF and a pulse width P gF ;

[0059] Applying a write pulse to the second pole and a write gate voltage pulse to the fourth pole, the on-chip RRAM is written. The write pulse is a pulse with an amplitude V W and a pulse width P W . The write gate voltage pulse is a pulse with an amplitude V gW and a pulse width P gW . The pulse changes the resistance value of the RRAM to reach a high resistance state or a low resistance state;

[0060] A read pulse is applied to the second pole and a write gate voltage pulse is applied to the fourth pole, and the on-chip RRAM is read out. The read pulse is a pulse with an amplitude of V R and a pulse width of P R The write gate voltage pulse is a pulse with an amplitude of V gR and a pulse width of P gR The pulse change reads the resistance value of the RRAM to obtain the digital logic value stored in the RRAM.

[0061] It should be noted that the microcontroller screening test system with an on-chip RRAM memory provided in the above embodiment is only illustrated by dividing the above functional modules. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the modules or steps in the embodiments of the present invention can be further decomposed or combined. For example, the modules in the above embodiment can be combined into one module, or further split into multiple sub-modules to complete all or part of the functions described above. For the names of the modules and steps involved in the embodiments of the present invention, they are only used to distinguish each module or step and are not regarded as an improper limitation of the present invention.

[0062] A wafer-level screening test method for a microcontroller with an on-chip RRAM according to the second embodiment of the present invention is based on the wafer-level screening test system for a microcontroller with an on-chip RRAM, see Figure 1 and includes the following steps:

[0063] Step 1: Based on the host computer vector test software, the test machine, and the microcontroller die with an on-chip RRAM, a series of preset test processes are executed, and it is sequentially determined whether each process passes; the test processes include connection tests, electrical parameter tests, function tests, RRAM initialization tests, and RRAM read and write tests, and the tests are carried out one by one in sequence;

[0064] Step 2: If all the preset test processes pass, it is determined that the microcontroller die with an on-chip RRAM being currently tested is a qualified product and passes the screening process; if any one of the preset test processes fails, it is immediately determined that the microcontroller die with an on-chip RRAM being currently tested is a non-qualified product and does not pass the screening process;

[0065] Step 3: After completing the screening process of the microcontroller die with an on-chip RRAM being currently tested, the test machine automatically switches to the next microcontroller die with an on-chip RRAM;

[0066] Step 4: Repeat steps 1-3 until the screening of all the microcontroller dies with an on-chip RRAM on the entire wafer is completed;

[0067] In this embodiment, see Figure 1, before the test, connect the host computer vector test software to the test machine platform to ensure normal communication. Install the built-in RRAM microcontroller die on the test machine platform and configure the corresponding test parameters. The connection test configuration is as follows: Generate and send a test signal to the test machine platform through the host computer vector test software; the test machine platform then applies the test signal to all PADs of the currently tested built-in RRAM microcontroller die. Monitor whether the test machine platform receives normal feedback signals from all PADs. If all PADs can be normally connected and feedback signals, it is determined that the currently tested built-in RRAM microcontroller die passes the connection test, and an electrical parameter test is performed; if any PAD cannot be normally connected or does not feedback a signal, it is determined that the currently tested built-in RRAM microcontroller die fails the connection test;

[0068] The electrical parameter test configuration is as follows: Generate and send a test vector to the test machine platform through the host computer vector test software; the test machine platform then applies the test vector to the currently tested built-in RRAM microcontroller die and monitors the test results feedback by the test machine platform. Based on the test results, if all test vectors pass the verification, it is determined that the currently tested built-in RRAM microcontroller die passes the electrical parameter test, and a function test is performed; if any test electrical vector fails to pass the verification, it is determined that the currently tested built-in RRAM microcontroller die fails the electrical parameter test;

[0069] The test vector includes output high-level voltage, output low-level voltage, input high-level voltage, input low-level voltage, input high-level leakage current, input low-level leakage current, and high-low level conversion current;

[0070] The function test configuration is as follows: Generate and send a function test vector to the test machine platform through the host computer vector test software. The test machine platform then applies the function test vector to the currently tested built-in RRAM microcontroller die and monitors the test results feedback by the test machine platform. Based on the test results, if all function vectors can pass the verification, it is determined that the function test passes, and an RRAM initialization test is performed; otherwise, it is determined that the function test fails;

[0071] The microcontroller operates in an off-chip mode;

[0072] The function test vector includes basic instruction test and peripheral function test;

[0073] The RRAM initialization test includes the following steps:

[0074] CS1, the host computer vector test software generates and sends a test vector for RRAM initialization to the on-chip RRAM memory, and the microcontroller operates in a programming mode;

[0075] CS2, perform a full-address read operation on the on-chip RRAM memory;

[0076] CS3, according to the result of the read operation, perform a forming operation on all high-resistance cells and an empty operation on low-resistance cells;

[0077] CS4, under different operating conditions 1 - m, repeat the above full-address read operation and the corresponding forming operation or empty operation, and perform the operations m times in total;

[0078] CS5, after completing m operations, perform a full-address read operation again and calculate the production success rate of the RRAM memory;

[0079] CS6, if the production success rate of the RRAM memory exceeds X%, preferably 90% here, then determine that the current RRAM test die passes the initialization test and perform the RRAM read-write test; otherwise, determine that the current RRAM test die fails the initialization test;

[0080] The RRAM read-write test includes the following steps:

[0081] DX1, the host computer vector test software generates and sends read-write test vectors to the on-chip RRAM memory, and the microcontroller operates in the programming mode;

[0082] DX 2, under different operating conditions 1 - n, perform continuous full-address iterative write 0 and iterative write 1 operations on the on-chip RRAM memory, perform the operations N times in total, and calculate the production success rate of the RRAM memory after each iteration;

[0083] DX 3, if the success rates of all iterative write 0 and iterative write 1 operations can exceed Y%, preferably 90% here, then determine that the current RRAM test die passes the read-write test and determine that the current tested built-in RRAM microcontroller die is a qualified product and passes the screening process; otherwise, determine that the current RRAM test die fails the read-write test;

[0084] See Figure 3 , and also includes further optimization and call of the vectors for full-address writing, specifically:

[0085] Before each iterative write operation, perform a full-address iterative read operation, and judge the read result in groups of K bits. According to the process characteristics and error correction ability of the RRAM, the value of K here is set according to the process characteristics and error correction ability of the built-in RRAM microcontroller, and 8 bits are selected as a group for subsequent tests, and the read result is judged in groups of 8 bits;

[0086] If all the units in a group need to perform write operations, directly call the K-bit write operation vector, and correspondingly directly call the 8-bit write operation vector;

[0087] If there are units in a group that do not need to perform write operations, call the 1-bit write operation vector sequentially according to the test results, form the full-address write vector through the above method and execute it. The above efficient RRAM read / write test method can reduce the time overhead by about 45.5% compared with the conventional process.

[0088] Although the various steps are described in the above order in the above embodiments, those skilled in the art can understand that in order to achieve the effects of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reversed order, and these simple changes are all within the protection scope of the present invention.

[0089] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0090] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, so that a process, method, article or device / equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent in these processes, methods, articles or devices / equipment.

[0091] So far, the technical solution of the present invention has been described in conjunction with the preferred embodiments shown in the drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A wafer-level screening and testing system with an embedded RRAM microcontroller, characterized in that, It includes a host computer vector test software, a test machine platform, and an embedded RRAM microcontroller die; The host computer vector test software generates test instructions and sends them to the test machine platform; The test machine platform applies the test instructions to the embedded RRAM microcontroller die for testing and monitors the test data of the embedded RRAM microcontroller die; The test machine platform feeds back the test data to the host computer vector test software for processing and analysis to obtain the test results.

2. The wafer-level screening and testing system for an in-built RRAM microcontroller according to claim 1, characterized in that, The embedded RRAM microcontroller die includes RRAM cells, and the RRAM cells include a field effect transistor T0 and a resistive switching device R0; The field effect transistor T0 includes an N-type field effect transistor and a P-type field effect transistor; The first pole of the field effect transistor T0 is connected to the SL terminal, the second pole of the forward operation terminal of the resistive switching device is connected to the BL terminal, the third pole of the reverse operation terminal of the resistive switch is connected to the transistor device terminal, and the word line WL and the gate of the field effect transistor T0 are the fourth pole; Apply a write pulse to the second pole and a write gate voltage pulse to the fourth pole to initialize the on-chip RRAM; Apply a write pulse to the second pole and a write gate voltage pulse to the fourth pole to write to the on-chip RRAM; Apply a read pulse to the second pole and a write gate voltage pulse to the fourth pole to read from the on-chip RRAM.

3. A wafer-level screening and testing method for an embedded RRAM microcontroller, based on the wafer-level screening and testing system for an embedded RRAM microcontroller according to any one of claims 1-2, characterized in that, It includes the following steps: Step 1, execute a preset test process on the embedded RRAM microcontroller die and sequentially determine whether each test process passes; the test process includes connection test, electrical parameter test, function test, RRAM initialization test, and RRAM read / write test; Step 2, if all the preset test processes pass, then determine that the currently tested embedded RRAM microcontroller die is a qualified product and passes the screening process; if any one of the preset test processes fails, then immediately determine that the currently tested embedded RRAM microcontroller die is a non-qualified product and fails the screening process; Step 3, after completing the screening process of the currently tested embedded RRAM microcontroller die, the test machine platform automatically switches to the next embedded RRAM microcontroller die; Step 4, repeat Steps 1-3 until the screening of all the embedded RRAM microcontroller dies on the entire wafer is completed.

4. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 3, characterized in that, The connection test is configured as follows: Apply a test signal to all the PADs of the currently tested embedded RRAM microcontroller die; monitor whether the test machine platform receives normal feedback signals from all the PADs. If all the PADs can be normally connected and feedback signals, then determine that the currently tested embedded RRAM microcontroller die passes the connection test and proceed to the electrical parameter test; if any one of the PADs cannot be normally connected or does not feedback a signal, then determine that the currently tested embedded RRAM microcontroller die fails the connection test.

5. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 3, characterized in that, The electrical parameter test is configured as follows: Apply test vectors to the built-in RRAM microcontroller die under current test, and monitor the test results fed back by the test machine. Based on the test results, if all test vectors pass the verification, it is determined that the built-in RRAM microcontroller die under current test passes the electrical parameter test, and the function test is carried out; if any test vector fails to pass the verification, it is determined that the built-in RRAM microcontroller die under current test fails the electrical parameter test. The test vectors include output high-level voltage, output low-level voltage, input high-level voltage, input low-level voltage, input high-level leakage current, input low-level leakage current, and high-low level conversion current.

6. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 3, characterized in that The function test is configured as follows: Apply function test vectors to the built-in RRAM microcontroller die under current test, and monitor the test results fed back by the test machine. Based on the test results, if all function vectors pass the verification, it is determined that the function test passes, and the RRAM initialization test is carried out; otherwise, it is determined that the function test fails. The microcontroller operates in an off-chip mode. The function test vectors include basic instruction test and peripheral function test.

7. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 3, characterized in that The RRAM initialization test includes the following steps: CS1, The host computer vector test software generates and sends test vectors for RRAM initialization to the test machine, and the test machine then applies the initialized test vectors to the built-in RRAM microcontroller die under current test, and the microcontroller operates in the programming mode. CS2, Perform a full-address read operation on the built-in RRAM microcontroller die under current test. CS3, According to the read operation results, perform a forming operation on all high-impedance cells and an empty operation on low-impedance cells. CS4, Under different operating conditions 1-m, repeat the above full-address read operation and the corresponding forming operation or empty operation. CS5, After completing m operations, perform a full-address read operation again, and calculate the production success rate of the built-in RRAM microcontroller die under current test. CS6, If the production success rate of the built-in RRAM microcontroller die under current test exceeds X%, it is determined that the current RRAM test die passes the initialization test, and the RRAM read-write test is carried out; otherwise, it is determined that the current RRAM test die fails the initialization test.

8. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 3, characterized in that, The RRAM read-write test includes the following steps: DX1, The host computer vector test software generates and sends read-write test vectors to the built-in RRAM microcontroller die under current test, and the microcontroller operates in the programming mode. DX 2, Under different operating conditions 1-n, perform continuous full-address iterative write 0 and iterative write 1 operations on the built-in RRAM microcontroller die under current test, and calculate the production success rate of the built-in RRAM microcontroller die under current test after each iteration. DX 3. If the success rates of all iterative write 0 and iterative write 1 operations can exceed Y%, it is determined that the read-write test of the current RRAM test die passes, and it is determined that the built-in RRAM microcontroller die under the current test is a qualified product and passes the screening process; otherwise, it is determined that the read-write test of the current RRAM test die fails.

9. A wafer-level screening and testing method for an in-built RRAM microcontroller according to claim 8, characterized in that, It also includes further optimization and invocation of the vector for full-address writing, specifically: Before each iterative write operation, perform a full-address iterative read operation, and judge the read results in groups of K bits; If all units in a group need to be written, directly call the K-bit write operation vector; If there are units that do not need to be written in a group of units, call the 1-bit write operation vector in sequence according to the test results.

10. A wafer-level screening and testing method for a built-in RRAM microcontroller according to claim 9, characterized in that, The value of K is set according to the process characteristics and error correction capabilities of the built-in RRAM microcontroller.

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