Electronic device and method of forming same

Abstract

The invention provides an electronic device and a forming method thereof. The method comprises the following steps: providing a packaging substrate; forming a bridge interposer within the package substrate, and exposing a top surface of the bridge interposer from the package substrate; attaching a step interposer on a top surface of the bridge interposer, wherein the step interposer has a step structure on one side thereof; mounting a bottom semiconductor die on the package substrate, wherein the bottom semiconductor die is adjacent to the step interposer; mounting one or more upper semiconductor dies on the step structure of the bottom semiconductor die and the step interposer to electrically couple each of the upper semiconductor dies with the bridge interposer through the step interposer; mounting an electronic component on a top surface of the bridge interposer to electrically couple the electronic component with the one or more upper semiconductor dies through the bridge interposer and the step interposer; and forming a mold cover on the package substrate.

Description

Technical Field

[0001] This application generally relates to semiconductor packaging technology, and more particularly, to an electronic device and a method of forming the same. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers desire smaller, faster, and higher-performance electronic devices and pack more and more functions into a single device. In recent years, system-on-chip (SOC) modules have been widely used in integrated electronic devices. Generally, in some high-performance devices, SOC modules can be combined with various semiconductor module packages to provide better performance and versatility. However, it should be noted that the manufacturing process of semiconductor packages with SOC modules and other semiconductor modules is complex and not cost-effective. In addition, such complex processes may adversely affect the device performance of semiconductor packages with such modules.

[0003] Therefore, there is a need for further improvement in the method for forming an electronic device with an SOC module. Summary of the Invention

[0004] An object of this application is to provide an electronic device and a method for forming a higher-performance electronic device, and the method has a simple process.

[0005] According to one aspect of this application, a method for forming an electronic device is provided. The method includes: providing a packaging substrate; forming a bridging interposer within the packaging substrate and exposing a top surface of the bridging interposer from the packaging substrate; attaching a stepped interposer on the top surface of the bridging interposer, wherein the stepped interposer has a stepped structure on one side thereof; mounting a bottom semiconductor die on the packaging substrate, and the bottom semiconductor die is adjacent to the stepped interposer; mounting one or more upper semiconductor dies on the bottom semiconductor die and the stepped structure of the stepped interposer to electrically couple each of the upper semiconductor dies to the bridging interposer through the stepped interposer; mounting an electronic component on the top surface of the bridging interposer to electrically couple the electronic component to the one or more upper semiconductor dies through the bridging interposer and the stepped interposer; and forming a mold cover on the packaging substrate to encapsulate the bottom semiconductor die, the one or more upper semiconductor dies, the stepped interposer, and the electronic component.

[0006] According to another aspect of the present application, an electronic device is provided. The electronic device includes: a package substrate; a bridging interposer formed within the package substrate, wherein the bridging interposer includes a top surface exposed from the package substrate; a stepped interposer attached to the top surface of the bridging interposer, wherein the stepped interposer has a stepped structure on one side thereof; a bottom semiconductor die mounted on the package substrate and adjacent to the stepped interposer; one or more upper semiconductor dies mounted on the bottom semiconductor die and the stepped structure of the stepped interposer, wherein each upper semiconductor die is electrically coupled to the bridging interposer through the stepped interposer; an electronic component mounted on the top surface of the bridging interposer, wherein the electronic component is electrically coupled to the one or more upper semiconductor dies through the bridging interposer and the stepped interposer; and a mold cover formed on the package substrate and encapsulating the bottom semiconductor die, the one or more upper semiconductor dies, the stepped interposer, and the electronic component.

[0007] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings incorporated in this specification and constituting a part of this specification illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings referred to herein form a part of the specification. Unless otherwise expressly indicated in the detailed description, the features shown in the drawings only illustrate some embodiments of the present application and not all embodiments of the present application, and readers of this specification should not make an opposite inference.

[0009] Figures 1A to 1G Illustrates the various steps of a method for forming an electronic device according to a first embodiment of the present application.

[0010] Figure 2 Illustrates an electronic device according to a second embodiment of the present application.

[0011] Figure 3 Illustrates an electronic device according to a third embodiment of the present application.

[0012] The same reference numerals will be used throughout the drawings to refer to the same or similar parts. DETAILED DESCRIPTION

[0013] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the present application may be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical, and other changes without departing from the spirit or scope of the present application. Accordingly, the reader of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0014] In the present application, unless otherwise expressly stated, the use of the singular includes the plural form. In the present application, unless otherwise stated, the use of "or" means "and / or". Additionally, the use of the term "comprising" is not restrictive. Further, unless otherwise expressly stated, terms such as "element" or "component" cover both elements and components that include one unit and elements and components that include more than one sub-unit. Additionally, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0015] As used herein, for ease of description, spatial relative terms such as "under", "below", "above", "over", "on", "upper", "lower", "left", "right", "vertical", "horizontal", "side", etc. may be used to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or there may be intervening elements.

[0016] As mentioned above, one or more system-on-chip (SOC) modules and various semiconductor modules can be incorporated into a single device to provide better performance and versatility. During the manufacturing process of the device, the semiconductor modules can be pre-packaged before being mounted onto a package substrate. Subsequently, the pre-packaged semiconductor modules and one or more SOC modules can be separately mounted onto the package substrate. Next, a mold cap can be formed on the package substrate to encapsulate all the pre-packaged semiconductor modules and SOC modules, thereby forming an integrated device. However, it should be noted that the manufacturing process of the integrated device can be complex and not cost-effective. In addition, the pre-packaged semiconductor modules within the integrated device form a structure of package within package, which can cause warping of the entire device and adversely affect device performance. To address this issue, a new method for forming an electronic device is provided, which introduces a stepped interposer with a stepped structure onto the package substrate. Two or more semiconductor dies can be mounted in a stepped form on the stepped structure of the package substrate and the stepped interposer. The semiconductor dies can then be electrically coupled to the SOC modules at least partially through the stepped interposer. Consequently, a one-step encapsulation can be implemented to form a one-piece mold cap for the entire device.

[0017] Figures 1A to 1G Illustrates the various steps of a method for forming an electronic device according to a first embodiment of the present application. Hereinafter, the method will be described in more detail with reference to Figures 1A to 1G the same.

[0018] As Figure 1A shown, a package substrate 100 having a front surface and a back surface is provided. The front surface of the package substrate 100 can serve as a platform for mounting one or more electronic components and one or more interposers. In some embodiments, the electronic device can be a dual-sided molded (DSM) package, and thus, the back surface can also serve as another platform for mounting one or more other electronic components and one or more other interposers.

[0019] Next, a cavity is formed within the package substrate 100, and a bridging interposer 101 is formed within the cavity. The top surface of the bridging interposer 101 is exposed from the package substrate 100 for mounting one or more electronic components and / or one or more interposers. In some embodiments, the bridging interposer 101 can provide electrical connections between one or more electronic components and one or more interposers. In Figure 1AIn the embodiments shown, the bridging interposer 101 may include at least one conductive line 103 surrounded by an interposer substrate 102. The interposer substrate 102 may include a dielectric material such as silica or a semiconductor material such as silicon, or may include other dielectric materials such as epoxy resin or a similar polymeric material. Each of the one or more conductive lines 103 may have a first conductive pad at one end and a second conductive pad at the other end, and both the first conductive pad and the second conductive pad are exposed from the top surface of the bridging interposer 101, while the main section of the conductive line 103 connecting the two ends of the conductive line 103 is embedded in the interposer substrate 102. In some embodiments, depending on the number of one or more electronic components and one or more interposers attached to the bridging interposer 101 and requiring electrical connection to other components, the number of conductive lines 103 included in the bridging interposer 101 may be two, three, or even more.

[0020] In some embodiments, in addition to the bridging interposer 101, a redistribution structure (not shown) may also be formed in the package substrate 100, and the redistribution structure may include a plurality of top conductive patterns, a plurality of bottom conductive patterns, and a plurality of conductive vias electrically connecting at least one of the top conductive patterns to at least one of the bottom conductive patterns. Multiple sets of conductive pads may be formed on the top conductive patterns and the bottom conductive patterns for mounting one or more electronic components and one or more interposers. It can be understood that the multiple sets of conductive pads may be exposed portions of conductive patterns formed within the package substrate 100. In some embodiments, the redistribution structure may optionally be connected to the bridging interposer 101.

[0021] Next, as Figure 1B shown, a plurality of connection interposer units with continuously increasing heights are placed side by side on the top surface of the bridging interposer 101 through solder bumps 111. The plurality of connection interposer units together form a stepped interposer 110. Each of the connection interposers may be an eBar module, which includes a plurality of conductive posts and a dielectric interposer substrate surrounding the conductive posts and electrically isolating them from each other. The interposer substrate may include a dielectric material such as silica, or a semiconductor material such as silicon, or a polymeric material with or without fillers such as epoxy resin. Additionally, the bottom surface of the conductive posts is exposed from the bottom surface of the interposer substrate for contacting the solder bumps 111. In some embodiments, a plurality of conductive pads may be formed on the bottom surface of the conductive posts for mounting the plurality of connection interposer units to the bridging interposer 101 through the corresponding solder bumps 111. In Figure 1BIn the embodiments shown, for each of the plurality of connection intermediary units, at least one of the plurality of conductive pillars included in the connection intermediary unit is attached to one of the plurality of conductive lines 103, thereby allowing an electrical connection between each connection intermediary unit in the connection intermediary units and the bridging intermediary 101. In some embodiments, each of the connection intermediary units may include only one conductive pillar or more than two conductive pillars. Additionally, the top surface of the conductive pillar is exposed from the top surface of the intermediary substrate for electrical connection of additional electronic modules. It can be appreciated that the height of the conductive pillar may be less than the height of the corresponding intermediary substrate, which may leave a slot above the top surface of the conductive pillar. The slot may be used to accommodate the electrical connection structure or solder bumps of the additional electronic module. In some other embodiments, the connection intermediary unit may include a conductive pattern and / or conductive vias.

[0022] Still referring to Figure 1B , the plurality of connection intermediary units include a first connection intermediary unit 110-1 having a minimum height, a second connection intermediary unit 110-2 having a medium height, and a third connection intermediary unit 110-3 having a maximum height. The connection intermediary units are placed adjacent to each other according to gradually increasing heights, thereby having a stepped structure on one side of the stepped intermediary 110. In some embodiments, two adjacent connection intermediary units in a pair may have the same height difference or different height differences, which enables the heights of the plurality of connection intermediary units to form an arithmetic progression. Additionally, multiple pairs of two adjacent connection intermediary units have the same distance, whereby the plurality of connection intermediary units are evenly distributed on the bridging intermediary 101. In some other embodiments, the height differences between multiple pairs of two adjacent connection intermediary units may be different. There may also be different spacings between multiple pairs of two adjacent connection intermediary units. It can be appreciated that different numbers of the plurality of connection intermediary units may be attached to the package substrate 100.

[0023] In addition, as Figure 1B shown, each of the plurality of connection intermediary units has a cuboid shape, and each of the plurality of connection intermediary units has a stepped surface at the top of the connection intermediary unit and a rising surface at the side of the connection intermediary unit. Referring to Figure 1B, the first connection intermediate unit 110-1 has a first stepped surface 112-1 at the top of the first connection intermediate unit 110-1 and a first rising surface 112-2 extending between the first stepped surface 112-1 and the top surface of the bridging intermediate 101. The second connection intermediate unit 110-2 has a second stepped surface 113-1 at the top of the second connection intermediate unit 110-2 and a second rising surface 113-2 extending between the second stepped surface 113-1 and the first stepped surface 112-1. The third connection intermediate unit 110-3 has a third stepped surface 114-1 at the top of the third connection intermediate unit 110-3 and a third rising surface 114-2 extending between the third stepped surface 114-1 and the second stepped surface 113-1. The first stepped surface 112-1, the first rising surface 112-2, the second stepped surface 113-1, the second rising surface 113-2, the third stepped surface 114-1, and the third rising surface 114-2 together form the stepped structure of the stepped intermediate 110.

[0024] Next, the bottom semiconductor die 120-1 is mounted on the package substrate 100 through solder bumps 121-1, and the bottom semiconductor die 120-1 is adjacent to the first rising surface 112-2 of the first connection intermediate unit 110-1. In Figure 1B the illustrated embodiment, a plurality of conductive pads may be formed on the bottom surface of the bottom semiconductor die 120-1 for mounting the bottom semiconductor die 120-1 to the package substrate 100 through corresponding solder bumps 121-1. More specifically, the bottom semiconductor die 120-1 may be attached to the top surface of the top conductive pattern within the package substrate 100 and thus electrically connected to the redistribution structure. In some other embodiments, in addition to the solder bumps 111 for electrical connection, virtual bumps may also be formed under the bottom semiconductor die 120-1. The virtual bumps may only provide mechanical support for the elements thereon, rather than being electrically connected to the top conductive pattern within the package substrate 100. In some embodiments, the bottom semiconductor die 120-1 may include a high-bandwidth memory die. In some other embodiments, the bottom semiconductor die 120-1 may include a die with logic functions or a controller die, such as a microprocessor or a microcontroller unit.

[0025] After mounting the bottom semiconductor die 120-1, the height of the top surface of the bottom semiconductor die 120-1 relative to the front surface of the package substrate 100 may be substantially the same as the height of the first connection intermediate unit 110-1, which provides a relatively flat platform for mounting the upper semiconductor die in subsequent steps.

[0026] Next, as Figure 1CAs shown, the first upper semiconductor die 120-2 is mounted on the first stepped surface 112-1 of the first connection interposer unit 110-1 and the bottom semiconductor die 120-1 through solder bumps 121-2. A plurality of conductive pads may be formed on the bottom surface of the first upper semiconductor die 120-2 for mounting the first upper semiconductor die 120-2 to the first connection interposer unit 110-1 and the bottom semiconductor die 120-1 through solder bumps 121-2. In this embodiment, the solder bumps 121-2 may include connection bumps and dummy bumps. The connection bumps are used to attach the first upper semiconductor die 120-2 to the first stepped surface 112-1. More specifically, the connection bumps are attached to the top surface of the conductive posts within the first connection interposer unit 110-1. Thereby, the first upper semiconductor die 120-2 can be electrically coupled to the bridging interposer 101 through the first connection interposer unit 110-1. Meanwhile, the dummy bumps are attached to the top surface of the bottom semiconductor die 120-1, and the dummy bumps only provide mechanical support for the components thereon, rather than providing electrical connection.

[0027] As Figure 1C shown, after the first upper semiconductor die 120-2 is mounted, the height of the top surface of the first upper semiconductor die 120-2 relative to the front surface of the package substrate 100 may be substantially the same as the height of the second stepped surface 113-1, which provides a relatively flat platform for mounting additional upper semiconductor dies.

[0028] Next, as Figure 1D shown, the second upper semiconductor die 120-3 is mounted on the second stepped surface 113-1 of the second connection interposer unit 110-2 and the first upper semiconductor die 120-2 through solder bumps 121-3. Thereby, the second upper semiconductor die 120-3 can be electrically coupled to the bridging interposer 101 through the second connection interposer unit 110-2. After the second upper semiconductor die 120-3 is mounted, the height of the top surface of the second upper semiconductor die 120-3 relative to the front surface of the package substrate 100 may be substantially the same as the height of the third stepped surface 114-1. The details of the mounting steps of the second upper semiconductor die 120-3 may be similar to those of the first upper semiconductor die 120-2, and will not be described in detail here for simplicity.

[0029] Next, as Figure 1EAs shown, the third upper semiconductor die 120-4 is mounted on the third stepped surface 114-1 of the third connection interposer unit 110-3 and the second upper semiconductor die 120-3 by solder bumps 121-4. Thus, the third upper semiconductor die 120-4 can be electrically coupled to the bridging interposer 101 through the third connection interposer unit 110-3. Details of the installation steps of the third upper semiconductor die 120-4 may be similar to those of the first upper semiconductor die 120-2 and will not be described in detail here for simplicity.

[0030] It can be understood that the upper semiconductor die may include a high-bandwidth memory die. In some other embodiments, the upper semiconductor die may include a die with logic functions or a controller die. Additionally, in Figure 1E the embodiment shown, the bottom semiconductor die 120-1 and the plurality of upper semiconductor dies may have the same shape and size. In some other embodiments, the bottom semiconductor die 120-1 and the plurality of upper semiconductor dies may have different shapes or sizes. For example, the bottom semiconductor die 120-1 and the plurality of upper semiconductor dies may have different thicknesses. Thus, multiple pairs of adjacent connection interposer units may have different height differences. In other words, the plurality of connection interposer units may be specifically selected to have corresponding heights such that the top surface of the connection interposer unit and the top surface of the semiconductor die adjacent to the connection interposer unit and at the same level can form a relatively flat plane or platform for mounting additional upper semiconductor dies. Additionally, the bottom semiconductor die 120-1 and the plurality of upper semiconductor dies may have different widths. Thus, the plurality of connection interposer units may also have different widths to sufficiently accommodate the bottom semiconductor die 120-1 and the plurality of upper semiconductor dies. In this way, the connection interposer units can be more flexibly matched with the arrangement of the semiconductor dies.

[0031] In addition, in this embodiment, before mounting the bottom semiconductor die 120-1 onto the package substrate 100, the first connection interposer unit 110-1, the second connection interposer unit 110-2, and the third connection interposer unit 110-3 are attached to the top surface of the bridging interposer 101. In some other embodiments, the bottom semiconductor die 120-1 may be mounted onto the package substrate 100 after attaching the first connection interposer unit 110-1 to the top surface of the bridging interposer 101. Subsequently, the second connection interposer unit 110-2 may be mounted onto the top surface of the bridging interposer 101 before or after mounting the first upper semiconductor die 120-2. Subsequently, the third connection interposer unit 110-3 may be mounted onto the top surface of the bridging interposer 101 before or after mounting the second upper semiconductor die 120-3. In this way, the attachment of the plurality of connection interposer units can be more flexible, and the adjacent connection interposer units in pairs can have the same pitch or different pitches, which can be adjusted according to the size and shape of the attached semiconductor die. Additionally, the connection interposer unit may include conductive patterns and / or conductive vias to make the layout of the electrical connection between the upper semiconductor die and the bridging interposer 101 more flexible. In some other embodiments, one or more additional connection interposer units may be mounted on the bridging interposer 101, and one or more additional upper semiconductor dies may be partially mounted on the corresponding stepped surfaces of the one or more additional connection interposer units.

[0032] In some other embodiments, before attaching the connection interposer unit, the bottom semiconductor die 120-1, and the plurality of upper semiconductor dies to the top surface of the bridge interposer 101 and the front surface of the package substrate 100, a frame (not shown) may be attached to the top surface of the bridge interposer 101 and the front surface of the package substrate 100. The frame may include a plurality of vertical partitions or grid structures, with a portion of each vertical partition or grid structure corresponding to one or more of the semiconductor dies among the plurality of connection interposer units, thereby facilitating the attachment of the connection interposer units and the semiconductor dies. More specifically, during the step of attaching the connection interposer units, each of the plurality of connection interposer units may be attached to the top surface of the bridge interposer 101 by placing the left side surface against the side surface or wall of the corresponding vertical partition of the frame. Similarly, each of the plurality of semiconductor dies may be attached to the front surface of the package substrate 100 by placing the right side surface against the side surface or wall of the corresponding vertical partition of the frame. In this way, the frame may help to fix the connection interposer units and the semiconductor dies on the package substrate 100. Additionally, the vertical partitions may prevent potential tilting of the connection interposer units during the attachment process of attaching the plurality of connection interposer units to the bridge interposer 101. The number of vertical partitions included in the frame may vary depending on how the frame fixes the connection interposer units and / or the semiconductor dies. For example, the frame may include a plurality of vertical partitions, each corresponding to one of the plurality of connection interposer units, which may be similar to a comb structure inserted into the gaps between the plurality of connection interposer units. Alternatively, the frame may include only two partitions corresponding to the combination of the peripheral connection interposer units and semiconductor dies, which may be similar to a clamp structure.

[0033] In addition, after attaching a plurality of interconnection intermediary units and a plurality of semiconductor dies to the package substrate 100, a mold may be placed on the top surface of the third interconnection intermediary unit 110-3 and the top surface of the third upper semiconductor die 120-4. Subsequently, the plurality of interconnection intermediary units and the plurality of semiconductor dies are pressed toward the bridging intermediary 101 and the package substrate 100 using the mold, so as to re-form the solder bumps under the plurality of interconnection intermediary units and the plurality of semiconductor dies, which can keep the top surfaces of the interconnection intermediary units and the top surfaces of the semiconductor dies parallel to the front surface of the package substrate 100. Meanwhile, the pressing step can make the top surfaces of the interconnection intermediary units and the top surfaces of the corresponding semiconductor dies at the same level as the interconnection intermediary units flush, thereby improving the surface flatness of the stacked semiconductor dies. During the pressing step, the frame can also act as an obstruction, which restricts the tilting and displacement of the interconnection intermediary units and the semiconductor dies relative to the package substrate, thereby maintaining the alignment of the interconnection intermediary units, the semiconductor dies, and the conductive patterns or pads on the package substrate 100. It can be understood that the pressing step can be carried out before or during the reflow process of the solder bumps. In addition, the solder bumps can exhibit deformable characteristics, which can be re-formed by an external force. In some alternative embodiments, when successively attaching the interconnection intermediary units and the semiconductor dies at the same level, the pressing step can be carried out after attaching each pair of the interconnection intermediary units and the corresponding semiconductor dies at the same level.

[0034] In Figure 1F the embodiment shown in, an electronic component 130 is mounted on the top surface of the bridging intermediary 101. A plurality of conductive pads may be formed on the bottom surface of the electronic component 130 to mount the electronic component 130 to the bridging intermediary 101 through solder bumps 131. More specifically, at least a part of the solder bumps 131 may be attached to the second conductive pads of the conductive wires 103 included in the bridging intermediary 101 to electrically connect the electronic component 130 to the bridging intermediary 101. In this way, the electronic component 130 can be electrically coupled to each of the plurality of upper semiconductor dies through the bridging intermediary 101 and the stepped intermediary 110. In some embodiments, at least one of the solder bumps 131 may be electrically connected to the top conductive pattern in the package substrate 100, and the solder bump can electrically couple the electronic component 130 to the bottom semiconductor die 120-1 through the redistribution structure in the package substrate 100. In some other embodiments, the solder bumps 131 may further include dummy bumps, which only provide mechanical support for the attachment of the electronic component 130 on the package substrate 100.

[0035] In addition, in this embodiment, the electronic component 130 includes a system-on-chip (SOC) die. In some other embodiments, the electronic component 130 may include various types of electronic modules, such as semiconductor chips, resistors, capacitors, etc. In some other embodiments, one or more additional electronic components may be mounted on the bridging interposer 101. The bridging interposer 101 may include additional electrical connection structures to electrically couple one or more additional electronic components with the plurality of upper semiconductor dies.

[0036] In addition, in Figure 1F the embodiment of, the height of the top surface of the electronic component 130 may be higher than the height of the top surface of the third upper semiconductor die 120-4. In some other embodiments, the top surface of the electronic component 130 may have a height substantially the same as the height of the top surface of the third upper semiconductor die 120-4.

[0037] Next, a bonding process such as laser-assisted bonding or mass reflow may be performed to bond each of the semiconductor dies to the semiconductor die on the lower layer, thereby forming a semiconductor die stack. In this way, the semiconductor die stack may have better stability and may thus serve as a substrate for further attaching additional component layers and structures. Similarly, a bonding process may also be performed to internally or externally bond the electronic component 130 to additional components.

[0038] As Figure 1G shown, a mold cap 140 is formed on the package substrate 100 to encapsulate the bottom semiconductor die 120-1, the plurality of upper semiconductor dies 120-2, 120-3, 120-4, the stepped interposer 110, and the electronic component 130. The mold cap 140 may be formed using a package molding process such as an injection molding process, which covers the corresponding top and side surfaces of the structures and components on the package substrate 100. The mold cap material may include epoxy resin, polyester resin, etc. In some embodiments, the mold cap 140 may be formed using various other molding techniques including a transfer molding process, a compression molding process, or a film-assisted molding (FAM) process. Thereafter, optionally, a grinding process may be performed to remove the mold cap material on the top surface of the electronic component 130 to expose the top surface of the electronic component 130, thereby forming the electronic device 160. In some other embodiments as mentioned above, before attaching the stepped interposer and the semiconductor die, a frame is attached, and the frame may include a material the same as or similar to the material of the mold cap 140. After forming the mold cap 140, the frame and the mold cap 140 may be combined together to form an integral structure. In some alternative embodiments, the frame may include a material different from the mold cap 140, such as a metal material or a ceramic material. Optionally, the frame may be removed before forming the mold cap 140.

[0039] Next, still referring to Figure 1G, additional solder bumps 150 may be formed on the rear surface of the package substrate 100 for mounting the electronic device 160 onto an external electronic module. The solder bumps 150 may be electrically connected to the bridging interposer 101 and the redistribution structure in the package substrate 100, such that connections can be made to the semiconductor dies 120-1 to 120-4 and the electronic components 130 through the solder bumps 150.

[0040] Figures 1A to 1G The manufacturing process of the illustrated electronic device 160 has several advantages. First, since the height of each connection intermediate unit, the width of each connection intermediate unit, and the spacing between each pair of adjacent connection intermediate units can be easily adjusted according to the shapes and sizes of the bottom semiconductor die 120-1 and the multiple upper semiconductor dies, the attachment process of the multiple connection intermediate units onto the bridging interposer 101 can be more flexible, which is beneficial for forming an electronic device 160 with a complex electrical connection layout. The connection intermediate units may also include more complex electrical connection paths to electrically connect the multiple upper semiconductor dies to the electronic components 130. Second, the bottom semiconductor die 120-1 and the multiple upper semiconductor dies are stacked together in die units to form a chipset semiconductor structure, and the electronic components 130 and the chipset semiconductor structure can be encapsulated in the same package molding step, which greatly simplifies the packaging process, reduces costs, and ensures a fine bump pitch for high-performance devices. Since only one package molding step is implemented, the final electronic device 160 can be tested only once. Third, since the bottom semiconductor die 120-1 and the multiple upper semiconductor dies can form a chipset semiconductor structure instead of a pre-packaged semiconductor package, the manufacturing process can avoid a package-in-package encapsulation structure, thereby alleviating warping of the entire electronic device during subsequent heating processes such as a solder bump reflow process. Fourth, the bridging interposer 101 and the stepped interposer 110 can simplify the electrical connection between the electronic components 130 and the multiple upper semiconductor dies, which improves electrical stability and saves assembly space.

[0041] In some embodiments, the electronic device 160 can be applied to any semiconductor device that requires low cost and high performance, such as high-sensitivity sensors, precise integrated memories, etc.

[0042] In some other embodiments, the stepped interposer mounted on the top surface of the bridging interposer 101 may include an integrated stepped interposer instead of Figures 1A to 1G the multiple discrete connection intermediate units shown.

[0043] Figure 2 An electronic device 260 according to a second embodiment of the present application is shown.

[0044] As Figure 2As shown, a package substrate 200 is provided, and a bridging interposer 201 is formed within the package substrate 200. An integrated stepped interposer 210 is mounted on the top surface of the bridging interposer 201. The integrated stepped interposer 210 may include three interposer layers, namely, a first interposer layer, a second interposer layer on the first interposer layer, and a third interposer layer on the second interposer layer. The three interposer layers are integrated together as a single stepped interposer 210. The integrated stepped interposer 210 may be formed by removing a portion of a substrate, and the removal methods include grinding, drilling, pinching, etching, or a combination thereof.

[0045] Still referring to Figure 2 , the integrated stepped interposer 210 has a stepped structure on one side of the integrated stepped interposer 210. More specifically, the first interposer layer includes an exposed first stepped surface at the top of the first interposer layer, and a first rising surface extending between the first stepped surface and the top surface of the bridging interposer. The second interposer layer includes an exposed second stepped surface at the top of the second interposer layer, and a second rising surface extending between the second stepped surface and the first stepped surface. The third interposer layer includes an exposed third stepped surface at the top of the third interposer layer structure, and a third rising surface extending between the third stepped surface and the second stepped surface. The first stepped surface, the first rising surface, the second stepped surface, the second rising surface, the third stepped surface, and the third rising surface together constitute the stepped structure of the integrated stepped interposer 210. In addition, the integrated stepped interposer 210 may include a plurality of conductive pillars 210-1 and an interposer substrate 210-2 surrounding the conductive pillars 210-1. Each of the plurality of conductive pillars 210-1 extends from one of the stepped surfaces to the bottom surface of the interposer substrate 210-2. In some other embodiments, when the interposer substrate 210-2 is mainly made of glass, the integrated stepped interposer 210 may include Through Glass Vias (TGVs), where the plurality of conductive pillars 210-1 extend vertically through the entire stepped interposer 210.

[0046] A bottom semiconductor die 220-1 is mounted on the package substrate 200 and adjacent to the stepped interposer 210, and three upper semiconductor dies 220-2, 220-3, 220-4 may be partially mounted on the corresponding stepped surfaces of the interposer layers. In addition, an electronic component 230 is mounted on the top surface of the bridging interposer 201. A mold cover 240 is formed on the package substrate 200 to encapsulate the bottom semiconductor die 220-1, the plurality of upper semiconductor dies, the stepped interposer 210, and the electronic component 230. In some other embodiments, the integrated stepped interposer 210 may include more than three interposer layers, and one or more additional upper semiconductor dies may be partially mounted on the corresponding stepped surfaces of the additional interposer layers.

[0047] Further details of the electronic device 260 may be similar to Figures 1A to 1G the details shown in the embodiments therein, and will not be described in detail herein for simplicity.

[0048] For the formation of the electrical device 260, since the stepped interposer 210 is an integrated unit, the manufacturing and attachment of the stepped interposer 210 to the bridging interposer 101 can be greatly simplified. Additionally, multiple upper semiconductor dies can be stacked on the stepped structure of the stepped interposer 210 in a more stable manner.

[0049] In an alternative embodiment, the stepped interposer 210 may include two or more interposer layers on the top surface of the bridging interposer 201. The two or more separate interposer layers may be discrete pieces that can be successively attached to the top surface of the bridging interposer 201. A bonding process may be performed to bond each of the interposer layers to the lower interposer layer. In particular, each of the two or more interposer layers may have a top surface at least partially exposed as a stepped surface and a rising surface extending between two of the stepped surfaces or between the stepped surface and the top surface of the bridging interposer 201.

[0050] Figure 3 An electronic device 360 according to a third embodiment of the present application is shown.

[0051] As Figure 3As shown, a package substrate 300 is provided, and a bridging interposer 301 is formed within the package substrate 300. A stepped interposer 310 is mounted on the top surface of the bridging interposer 301 and has a stepped structure on one side of the stepped interposer 310. The stepped interposer 310 includes a connection interposer unit 310 having a stepped surface at the top of the connection interposer unit 310 and a rising surface extending from the top surface of the bridging interposer 301 to the stepped surface. A bottom semiconductor die 320-1 is mounted on the package substrate 300 and adjacent to the connection interposer unit 310. An upper semiconductor die 320-2 is mounted on the stepped surface of the connection interposer unit 310 and the bottom semiconductor die 320-1. In addition, an additional bridging interposer 302 is formed within the package substrate 300, and the top surface of the additional bridging interposer 302 is exposed from the package substrate 300. An additional stepped interposer 311 can be mounted on the top surface of the additional bridging interposer 302, and the additional stepped interposer 311 has a stepped structure on one side thereof. The additional stepped interposer 311 can include an additional connection interposer unit 311 similar to the connection interposer unit 310. An additional bottom semiconductor die 321-1 can be mounted on the package substrate 300 and adjacent to the additional stepped interposer 311, and an additional upper semiconductor die 321-2 can be mounted on the stepped surface of the additional bottom semiconductor die 321-1 and the additional connection interposer unit 311 to electrically couple the additional upper semiconductor die 321-2 to the additional bridging interposer 302 through the additional connection interposer unit 311. In addition, an electronic component 330 is mounted on the top surface of the bridging interposer 301 and the top surface of the additional bridging interposer 302 such that the electronic component 330 is electrically coupled to the upper semiconductor die through the bridging interposer 301 and the stepped interposer 310, and the electronic component 330 is also electrically coupled to the additional upper semiconductor die 321-2 through the additional bridging interposer 302 and the additional stepped interposer 311, thus becoming an electronic device 360. Since multiple semiconductor dies can be separated into two stacked chipset semiconductor structures, the height of each stack in the semiconductor die stack can be reduced, thereby increasing more space for accommodating additional electronic modules. The electronic device 360 can be applied to any semiconductor device that requires high integration and small size, such as mobile phones and tablet computers. In some other embodiments, the stepped interposer 310 and the additional stepped interposer 311 can be similar to any of the stepped interposers shown in Figures 1A to 1G and Figure 2 Therefore, the number of semiconductor dies included in one stack can be more than two. In addition, the structures of the stepped interposer 310 and the additional stepped interposer 311 can be different, and the number of semiconductor dies included in different semiconductor die stacks can be different.

[0052] Further details of the structure and formation steps of the electronic device 360 can be similar toFigures 1A to 1G The details shown in the embodiments in [reference] are not described in detail here for simplicity.

[0053] In Figure 3 the embodiment shown in [reference], the bridging intermediary 301 and the additional bridging intermediary 302 may be formed on two opposite sides of the electronic component 330. In some other embodiments, the bridging intermediary 301 and the additional bridging intermediary 302 may be formed at different positions on the same side of the electronic component 330. Additionally, in some other embodiments, the additional bridging intermediary may be formed on the package substrate 300 to serve as an additional platform for forming more semiconductor die stacks, which may further reduce the size of the electronic device 360.

[0054] Although the exemplary method for forming an electronic device of the present application is described in connection with the corresponding figures, those skilled in the art should understand that the method for forming an electronic device can be modified and adapted without departing from the scope of the present invention.

[0055] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader scope of the invention set forth in the appended claims, and additional embodiments can be implemented. Additionally, by considering the specification and practice of one or more embodiments of the invention disclosed herein, those skilled in the art will appreciate other embodiments. Therefore, it is intended that the present application and the examples herein be considered exemplary only, where the true scope and spirit of the invention are indicated by the recitation of the appended exemplary claims.

Claims

1. A method for forming an electronic device, characterized in that, The method includes: providing a packaging substrate; forming a bridging interposer within the packaging substrate and exposing a top surface of the bridging interposer from the packaging substrate; attaching a stepped interposer on the top surface of the bridging interposer, wherein the stepped interposer has a stepped structure on one side thereof; mounting a bottom semiconductor die on the packaging substrate, and the bottom semiconductor die being adjacent to the stepped interposer; mounting one or more upper semiconductor dies on the stepped structure of the bottom semiconductor die and the stepped interposer to electrically couple each of the one or more upper semiconductor dies to the bridging interposer through the stepped interposer; mounting an electronic component on the top surface of the bridging interposer to electrically couple the electronic component to the one or more upper semiconductor dies through the bridging interposer and the stepped interposer; and forming a mold cover on the packaging substrate to encapsulate the bottom semiconductor die, the one or more upper semiconductor dies, the stepped interposer, and the electronic component.

2. The method according to claim 1, wherein The electronic component includes a system-on-chip die.

3. The method according to claim 1, characterized in that, The bottom semiconductor die includes a high-bandwidth memory die, and the one or more upper semiconductor dies include one or more high-bandwidth memory dies.

4. The method according to claim 1, wherein The stepped interposer includes a connection interposer unit, and the stepped structure on one side of the stepped interposer includes: a stepped surface located at the top of the connection interposer unit, and a rising surface extending from the top surface of the bridging interposer to the stepped surface.

5. The method according to claim 4, characterized in that, The process of mounting one or more upper semiconductor dies on the stepped structure of the bottom semiconductor die and the stepped interposer includes: mounting an upper semiconductor die on the stepped surface of the connection interposer unit and the bottom semiconductor die.

6. The method according to claim 1, characterized in that, The process of attaching a stepped interposer on the top surface of the bridging interposer includes: placing a plurality of connection interposer units side by side on the top surface of the bridging interposer, the plurality of connection interposer units having continuously increasing heights and each of the plurality of connection interposer units having a stepped surface and a rising surface to form the stepped interposer, wherein the stepped structure includes two or more stepped surfaces and two or more rising surfaces, and each of the two or more rising surfaces extends between two of the plurality of stepped surfaces or between one of the stepped surfaces and the top surface of the bridging interposer.

7. The method according to claim 6, wherein Mounting one or more upper semiconductor dies on the stepped structure of the bottom semiconductor die and the stepped interposer includes: partially mounting two or more upper semiconductor dies on a plurality of corresponding stepped surfaces of the plurality of connection interposer units.

8. The method according to claim 1, characterized in that The process of attaching a stepped interposer on the top surface of the bridging interposer includes: Two or more interposer layers are continuously attached on the top surface of the bridging interposer, wherein each of the two or more interposer layers has at least a partially exposed top surface to serve as a step surface of the stepped structure, and a rising surface extending between two of the plurality of step surfaces or between one step surface and the top surface of the bridging interposer.

9. The method according to claim 1, wherein The process of attaching a stepped interposer on the top surface of the bridging interposer includes: Attaching an integrated stepped interposer on the top surface of the bridging interposer, wherein the integrated stepped interposer includes a plurality of interposer layers, and each of the plurality of interposer layers has an exposed step surface at the stepped structure, and a rising surface extending between two of the plurality of step surfaces or between one step surface and the top surface of the bridging interposer.

10. The method according to claim 8 or 9, characterized in that, The process of mounting one or more upper semiconductor dies on the stepped structure of the bottom semiconductor die and the stepped interposer includes: Partially mounting two or more upper semiconductor dies on the plurality of corresponding step surfaces of the plurality of interposer layers.

11. The method according to claim 1, characterized in that Before mounting an electronic component on the top surface of the bridging interposer, the method further includes: Forming an additional bridging interposer within the package substrate and exposing the top surface of the additional bridging interposer from the package substrate; Attaching an additional stepped interposer on the top surface of the additional bridging interposer, wherein the additional stepped interposer has a stepped structure on one of its sides; Mounting an additional bottom semiconductor die on the package substrate and the additional bottom semiconductor die is adjacent to the additional stepped interposer; and Mounting one or more additional upper semiconductor dies on the stepped structure of the additional bottom semiconductor die and the additional stepped interposer to electrically couple each of the additional upper semiconductor dies to the additional bridging interposer through the additional stepped interposer.

12. An electronic device, characterized in that, Comprising: A package substrate; A bridging interposer formed within the package substrate, wherein the bridging interposer includes a top surface exposed from the package substrate; A stepped interposer attached on the top surface of the bridging interposer, wherein the stepped interposer has a stepped structure on one of its sides; A bottom semiconductor die mounted on the package substrate and adjacent to the stepped interposer; One or more upper semiconductor dies mounted on the stepped structure of the bottom semiconductor die and the stepped interposer, wherein each of the upper semiconductor dies is electrically coupled to the bridging interposer through the stepped interposer; An electronic component mounted on the top surface of the bridging interposer, wherein the electronic component is electrically coupled to the one or more upper semiconductor dies through the bridging interposer and the stepped interposer; And A mold cover is formed on the encapsulation substrate and encapsulates the bottom semiconductor die, the one or more upper semiconductor dies, the stepped interposer, and the electronic components.

13. The electronic device according to claim 12, characterized in that, The stepped interposer includes a connection interposer unit, and the stepped structure on one side of the stepped interposer includes: A stepped surface located at the top of the connection interposer unit, and a rising surface extending from the top surface of the bridging interposer to the stepped surface.

14. The electronic device according to claim 13, characterized in that, One upper semiconductor die is mounted on the stepped surface of the connection interposer unit and the bottom semiconductor die.

15. The electronic device according to claim 12, characterized in that, The stepped interposer includes: A plurality of connection interposer units having successively increasing heights and placed side by side on the top surface of the bridging interposer, wherein each connection interposer unit of the plurality of connection interposer units includes a stepped surface and a rising surface to form the stepped interposer, and the stepped structure includes two or more stepped surfaces and two or more rising surfaces, and each of the two or more rising surfaces extends between two of the plurality of stepped surfaces or between one stepped surface and the top surface of the bridging interposer.

16. The electronic device according to claim 15, characterized in that, Two or more upper semiconductor dies are partially mounted on the plurality of corresponding stepped surfaces of the plurality of connection interposer units.

17. The electronic device according to claim 12, characterized in that, The stepped interposer includes: Two or more interposer layers successively attached to the top surface of the bridging interposer, wherein each of the two or more interposer layers has at least a partially exposed top surface as one stepped surface of the stepped structure, and a rising surface extending between two of the plurality of stepped surfaces or between one stepped surface and the top surface of the bridging interposer.

18. The electronic device according to claim 12, wherein The stepped interposer includes: An integrated stepped interposer attached to the top surface of the bridging interposer, wherein the integrated stepped interposer includes a plurality of interposer layers, and each of the plurality of interposer layers has an exposed stepped surface at the stepped structure and a rising surface extending between two of the plurality of stepped surfaces or between one stepped surface and the top surface of the bridging interposer.

19. The electronic device according to claim 17 or 18, characterized in that, Two or more upper semiconductor dies are partially mounted on the plurality of corresponding stepped surfaces of the plurality of interposer layers.

20. The electronic device according to claim 12, characterized in that, Further includes: An additional bridging interposer formed within the encapsulation substrate, wherein the additional bridging interposer includes a top surface exposed from the encapsulation substrate; An additional stepped interposer attached to the top surface of the bridging interposer, wherein the additional stepped interposer has a stepped structure on one side of the additional stepped interposer; An additional bottom semiconductor die mounted on the encapsulation substrate and adjacent to the additional stepped interposer; And One or more additional upper semiconductor dies, the one or more additional upper semiconductor dies being mounted on the stepped structure of the additional bottom semiconductor die and the additional stepped interposer, wherein each of the one or more additional upper semiconductor dies is electrically coupled to the additional bridging interposer through the additional stepped interposer.

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