Test structure and method of forming test structure
By designing a test structure of multiple active regions and isolation structures in the TFET device, the horizontal and vertical PN junction interface is formed, which solves the problem that traditional CMOS structures cannot monitor TFET tunneling junctions, and effectively monitors the electrical characteristics of tunneling junctions and evaluates the process.
Patent Information
- Application Number
- CN202410098860.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-07-25
AI Technical Summary
The prior art cannot effectively monitor the electrical characteristics of tunneling junction interfaces of tunneling field effect transistor (TFET) devices, and the traditional CMOS test structure is not applicable.
A test structure is designed, including a plurality of first active regions and isolation structures, to form a transverse and longitudinal PN junction interface by heavy doping at different parts of the active region, and to form contacts and leads on the heavily doping region, and to improve process compatibility and stability using strip auxiliary structures and side walls.
The electrical characteristics monitoring of the source tunneling junction of TFET devices are realized, the impurity deposition effect and ion implantation process are evaluated, the compatibility and availability of the test structure are improved, and the stable PN junction can be formed on the small-sized active region.
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Figure CN120376549A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the performance testing of semiconductor structures, and particularly to a structure for testing the electrical characteristics of a source / drain junction and a method for forming the same. Background Art
[0002] Figure 1 Shown is a planar TFET device conducting based on the tunneling principle. The applicant manufactures it by embedding a TFET-CMOS hybrid integration process flow on a planar MOSFET logic process platform, but an independent test structure needs to be provided for the newly introduced TFET device to monitor and test-characterize its related processes and device performance. The tunneling junction of the TFET is a key structure affecting device performance, and its process stability and electrical characteristics of the junction itself, such as resistance value, leakage current, etc., need to be focused on for testing and analysis. The tunneling current occurs at the junction boundary near the channel and is mainly provided by the lateral junction interface, that is Figure 1 interface B in
[0003] The structure for monitoring the PN junction in traditional CMOS is as shown in Figure 2A Taking the N+ heavily doped region and P-well junction as an example, after forming a shallow trench isolation (STI) 830 on the substrate 810, a P-well injection is then performed in the well region to form a P-well 820. The N+ heavily doped region 850 and P+ heavily doped region 860 are respectively carried out in the source / drain regions in a cycle. After further forming a silicide layer 840 and connecting wires such as contact holes (CT) metal, testing can be carried out.
[0004] As shown in the cross-section Figure 2B This test structure (testkey) can monitor a longitudinal PN junction. The N+ heavily doped region end is directly led out, and the P-well is led out by a pickup method. However, this structure is not suitable for a planar TFET (tunnel field effect transistor) device conducting based on the tunneling principle, and this structure cannot monitor the interface of the tunneling junction of the TFET. Therefore, a test structure suitable for TFET testing needs to be provided. Summary of the Invention
[0005] One object of this application is to design a new test structure so as to be able to monitor the electrical characteristics of the lateral PN junction on the wafer.
[0006] Some embodiments of the present application provide a test structure, which includes a plurality of first active regions located in a well region on a substrate, and two adjacent first active regions are separated by a first isolation structure; an auxiliary structure spanning each of the first active regions and its adjacent first isolation structure, each auxiliary structure being configured such that a first portion of the first active region is covered by the auxiliary structure, while a second portion of the first active region is not covered by the auxiliary structure; first heavily doped regions formed by heavily doping the second portions of each of the first active regions with a first conduction type different from the conduction type of the well region, respectively, to form a first PN junction interface at the lateral junction between each of the first heavily doped regions and the first active region where it is located, and a second PN junction interface at the longitudinal junction.
[0007] In some embodiments, the auxiliary structure is a strip-shaped auxiliary structure.
[0008] In some embodiments, it further includes a first contact formed on the first heavily doped region and a first lead wire led out from the first contact.
[0009] In some embodiments, a second active region is further included in the well region, the second active region is separated from the first active region by a second isolation structure, and the second active region includes a second heavily doped region different from the first heavily doped region; it further includes a second contact formed on the second heavily doped region and a second lead wire led out from the second contact.
[0010] In some embodiments, the auxiliary structure includes a main body portion and sidewalls on both sides of the main body portion.
[0011] In some embodiments, a set of test structures is included in which the widths of the first active regions are the same, while the widths of the first portions of the first active regions covered by the auxiliary structure are different, thereby forming first heavily doped regions with different widths.
[0012] In some embodiments, a set of test structures is included in which the widths of the first portions of the first active regions covered by the auxiliary structure are the same, while the overall widths of the first active regions are different, thereby forming first heavily doped regions with different widths.
[0013] In some embodiments, the test structure is used to test the source region / channel junction performance of a tunneling field effect transistor.
[0014] Some other embodiments of the present application provide a method for forming a test structure, which includes forming a plurality of strip-shaped first active regions on a well region of a substrate, and adjacent first active regions being separated by a first isolation structure; forming an auxiliary structure across each of the first active regions and its adjacent first isolation structure so that a first portion of the first active region is covered by the auxiliary structure, while a second portion of the first active region is not covered by the auxiliary structure; performing heavy doping of a first conduction type different from that of the well region on the second portion of each of the first active regions to respectively form first heavily doped regions, a first PN junction interface being formed at a lateral junction of each of the first heavily doped regions and the first active region where it is located, and a second PN junction interface being formed at a longitudinal junction.
[0015] In some embodiments, the auxiliary structure is formed in a strip shape.
[0016] In some embodiments, a first contact is formed on the first heavily doped region, and a first lead is led out from the first contact.
[0017] In some embodiments, a second isolation structure is formed, and together with the first active region, a second active region is formed. The second active region is spaced from the first active region by the second isolation structure. Heavy doping of a second conduction type different from the first conduction type is performed on the second active region to form a second heavily doped region; and a second contact is formed on the second heavily doped region, and a second lead is led out from the second contact.
[0018] In some embodiments, the first active regions are formed with the same width, while the widths of the first portions of the first active regions covered by the auxiliary structure are different, thereby forming a set of test structures with different widths of the first heavily doped regions, and the electrical properties of the first PN junction interface when the second portion of the first active region approaches zero are evaluated by extrapolation.
[0019] In some embodiments, a set of test structures are formed in which the widths of the first parts of the first active regions covered by the auxiliary structures are the same, while the overall widths of the first active regions are different, thereby forming first heavily doped regions with different widths. The electrical properties of the first PN junction interface when the second part of the first active region approaches zero are evaluated by extrapolation. The beneficial effects of the present application include: in some embodiments, a PN junction can be formed on a strip-shaped active region pattern with a small size by means of a strip-shaped auxiliary structure, without being affected by the minimum process size of the heavily doped region, such as the N+ heavily doped region; in some embodiments, the arrangement of the auxiliary structure enables the implantation of the heavily doped region to adopt a self-aligned process method, and the contour stability of the heavily doped region is higher; in some embodiments, the test structures have high process compatibility and strong usability. In some embodiments, the test structures provided by the present application can characterize electrical properties such as the junction leakage of the source tunneling junction of the TFET device in an MPW (multi-project wafer) for verifying the flow sheet of a new tunneling principle device, so as to further evaluate the impurity segregation effect and related ion implantation process conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is a schematic structural diagram of a pTFET in the prior art.
[0021] Figure 2A is a top view schematic diagram of a test structure for monitoring a PN junction by CMOS in the prior art.
[0022] Figure 2B is Figure 2A a cross-sectional schematic diagram of the test structure in
[0023] Figure 3A is a top view schematic diagram of a test structure according to an embodiment of the present application.
[0024] Figure 3B is Figure 3A a cross-sectional schematic diagram of the test structure in
[0025] Figure 4A is a schematic diagram of the dimensional relationship of a test structure according to an embodiment of the present application.
[0026] Figure 4B is a schematic diagram of the dimensional change of a test structure according to an embodiment of the present application DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0028] It should be noted that the test structure of the present application is particularly suitable for, but not limited to, PN junctions based on the tunneling principle or PN junctions with a single doping dose. However, for PN junctions that need to be monitored and are arranged parallel to the wafer surface direction, the test structure in the present application is applicable, and only the doping concentration and process need to be adjusted according to the process design.
[0029] Some embodiments of the present application provide a test structure for testing the electrical characteristics of a lateral tunneling junction, which is formed on a wafer or a substrate. The substrate is preferably composed of a silicon-containing material. The silicon-containing material includes, but is not limited to, Si, single-crystal Si, polycrystalline Si, SiGe, single-crystalline silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si, and their combinations and multi-layer materials. The substrate can also be composed of other semiconductor materials such as germanium and compound semiconductor substrates such as III / V semiconductor substrates like GaAs. Although the substrate is depicted as a bulk semiconductor substrate, the arrangement of a semiconductor on an insulator substrate, such as a silicon-on-insulator (SOI) substrate, is also applicable as the substrate 100.
[0030] As Figure 3A 、 Figure 3B shown, a plurality of spaced-apart strip-shaped isolation structures, such as shallow trench isolation structures, are formed on the substrate. Then, an injection mask is used to form a continuous P-well region in the area where the shallow trench isolation structures are located. The P-well region forms a plurality of active regions AA in a strip-shaped pattern structure between adjacent shallow trench isolation structures, and adjacent active regions are separated by the shallow trench isolation structures.
[0031] For convenience of description, a part of the plurality of active regions AA is called the first active region. After partially covering the first active region with a strip-shaped polysilicon auxiliary structure 400, N+ ion implantation is performed on the uncovered part of the first active region to form an N+ region, or an N+ heavily doped region 300, thereby forming a test PN junction. For ease of description, the isolation structure that separates the first active region is called the first isolation structure.
[0032] Specifically, a strip-shaped dummy poly 400 is provided for each first active region to shield a first part of the first active region from being implanted, so that after N+ ion implantation is performed on a second part of the unshielded first active region, a PN junction is formed at the edge of the N+ heavily doped region. In addition to meeting the requirements of the design rules, the dummy structure needs to span across a first active region and an adjacent shallow trench isolation structure 300 on one side thereof, especially across an active region and a shallow trench isolation structure 300.
[0033] It should be understood that although in the above embodiments, the formation of the PN junction interface of the test structure is described in the form of a P-well and N+ ion implantation structure, the test structure of the present application is also applicable to the formation of the lateral PN junction interface and the vertical PN junction interface by performing P+ ion implantation in an N-well.
[0034] It should be understood that in addition to polysilicon, the material of the dummy structure of the present application can also be other materials that can obtain the required work function, such as polycrystalline germanium, metals (such as aluminum, tungsten, tantalum, titanium, ruthenium, palladium, rhodium, rhenium, platinum) and their alloys, metal nitrides (such as TaN and TiN), metal silicon nitrides (such as TaSiN), conductive oxides (such as RuO2 and ReO3), fully silicided metals (FUSI) (such as CoSi2, NiSi and TiSi2), fully germinated metals (FUGE), tunneling metals with adjustable work functions, engineering materials.
[0035] With the help of the strip-shaped dummy structure, a PN junction can be formed on a strip-shaped active region pattern with a smaller size, without being affected by the minimum process size of the N+ heavily doped region; the dummy structure and its sidewall structure enable the implantation of the N+ heavily doped region to adopt a self-aligned process method, and the contour stability of the N+ heavily doped region is higher; the compatibility between the test structure and the process is high, and the usability is strong.
[0036] Each dummy structure 400 may include a main body portion and sidewalls respectively provided on both sidewalls of the main body portion, such as a first spacer 410 and a second sidewall 420. The thicknesses of the first sidewall and the second sidewall can be considered to be the same in regions with similar densities. For the convenience of description, the lateral thickness (width) dimensions of the first sidewall and the second sidewall are calculated in the width of the dummy structure. Forming sidewalls helps to integrate the process of the present application with MOS processes, especially CMOS processes. Therefore, in some embodiments of the present application, the sidewalls can be ignored. It should be understood that the material of the sidewalls in the embodiments of the present application can be a single layer or a composite layer, composed of high-temperature oxide (HTO) formed by hexachloroethyldisilane (Si2Cl6), silicon nitride, silicon oxide, or hydrogenated chemical vapor deposition silicon nitride (HCD-SiN).
[0037] In the above embodiments, additionally, the active region may include a second active region spaced from the first active region by a second isolation structure, such as a shallow trench isolation structure. The second active region is used to form a P+ region or a P+ heavily doped region after P+ ion implantation. It should be understood that for the embodiment of P+ ion implantation into the above N-well, the second active region is used to form an N+ region or an N+ heavily doped region after N+ ion implantation.
[0038] For some embodiments of the present application, a first contact may be formed on the first heavily doped region and a first lead drawn from the first contact, and a second contact may be formed on the second heavily doped region and a second lead drawn from the second contact. The contact material on the first heavily doped region and the second heavily doped region may be nickel silicide (NiSi) or other materials, especially other metal silicides.
[0039] Figure 4A , Figure 4B Specific embodiments are provided where the strip-shaped active region pattern size can be adjusted according to test requirements after meeting the design rule requirements;
[0040] As Figure 4A shown, the auxiliary structure 400 must straddle the strip-shaped first active region and the shallow trench isolation structure 300 while meeting the design rule requirements. The width of a first active region is a1, the width of the shallow trench isolation structure is a2, the width of the auxiliary structure 400 is p1, and the distance between the auxiliary structures 400 is p2. The width of the first part of the first active region blocked by the auxiliary structure 400 is p3. The width of the overlapping part of the auxiliary structure 400 and the shallow trench isolation structure is p4. Thus, the width of the second part of the first active region where N+ implantation can be performed is (a1 - p3).
[0041] Using the strip-shaped first active region, the auxiliary structure, and the shallow trench isolation structure makes the width n1 of the longitudinal PN junction interface, i.e., interface A, determined by a1 and p3, no longer limited by the design rule requirements of the N+ ion implantation process. The width n2 of the lateral PN junction interface, i.e., interface B, is determined by the implantation depth of the N+ ion implantation and is actually non-adjustable. Therefore, the size of n1 will be reduced to lower the proportion of interface A in the entire junction interface;
[0042] In practice, since the N+ ion implantation always has a width, the size of the longitudinal PN junction n1 will not be 0. Therefore, a comparative test structure with p3 set to 0 and the total area of n1 equal to the width of the strip-shaped active region can be used for evaluation.
[0043] In addition, a set of test structures with the same width a1 of the first active region and gradually increasing width p3 of the overlapping region between the auxiliary structure and the active region can be drawn and fabricated, i.e., as Figure 4Bas shown by increasing the size of the auxiliary structure in the L1 direction; or by drawing and fabricating the overlapping region of the auxiliary structure and the first active region, i.e., as Figure 4B shown, a set of test structures in which the width p3 of the first part of the first active region remains unchanged while the overall width a1 of the first active region gradually decreases in the L2 direction, and the electrical properties of the lateral PN junction interface, i.e., interface B, are evaluated by extrapolation when the width n1 of the N+ implantation region approaches 0.
[0044] The test structure provided by the embodiment of the present application can monitor the laterally arranged PN junction on the wafer, so that the test structure can characterize the electrical properties such as the junction leakage of the source tunneling junction of the TFET device in the MPW of the tunneling new principle device verification wafer, so as to further evaluate the impurity segregation effect and related ion implantation process conditions.
[0045] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A test structure, characterized in that: Comprising a plurality of first active regions located in a well region on a substrate and two adjacent first active regions separated by a strip-shaped first isolation structure; auxiliary structures across each of the first active regions and their adjacent first isolation structures, each auxiliary structure configured such that a first portion of the first active region is covered by the auxiliary structure while a second portion of the first active region is not covered by the auxiliary structure; first heavily doped regions respectively formed by heavily doping the second portions of each of the first active regions with a first conductivity type different from the conductivity type of the well region, with a first PN junction interface formed at the lateral junction between each first heavily doped region and the first active region where it is located, and a second PN junction interface formed at the longitudinal junction.
2. The test structure according to claim 1, wherein: The auxiliary structure is a strip-shaped auxiliary structure.
3. The test structure according to claim 1, wherein: Also included is a first contact formed on the first heavily doped region and a first lead led out from the first contact.
4. The test structure according to claim 1, characterized in that: In the well region, a second active region is further included, the second active region separated from the first active region by a second isolation structure, the second active region including a second heavily doped region different from the first heavily doped region; also included are a second contact formed on the second heavily doped region and a second lead led out from the second contact.
5. The test structure according to claim 1, wherein: The auxiliary structure includes a main body portion and sidewalls on both sides of the main body portion.
6. The test structure according to claim 1, wherein: A set of test structures including that the widths of the first active regions are the same, while the widths of the first portions of the first active regions covered by the auxiliary structure are different, thereby forming first heavily doped regions with different widths.
7. The test structure according to claim 1, wherein: A set of test structures including that the widths of the first portions of the first active regions covered by the auxiliary structure are the same, while the overall widths of the first active regions are different, thereby forming first heavily doped regions with different widths.
8. The test structure according to claim 1, wherein: The test structures are used to test the source region / channel junction performance of a tunneling field effect transistor.
9. A method for forming a test structure, characterized in that: Comprising forming strip-shaped a plurality of first active regions on a well region of a substrate, adjacent first active regions separated by a strip-shaped first isolation structure; forming auxiliary structures across each of the first active regions and their adjacent first isolation structures such that a first portion of the first active region is covered by the auxiliary structure while a second portion of the first active region is not covered by the auxiliary structure; heavily doping the second portions of each of the first active regions with a first conductivity type different from the conductivity type of the well region to respectively form first heavily doped regions, with a first PN junction interface formed at the lateral junction between each first heavily doped region and the first active region where it is located, and a second PN junction interface formed at the longitudinal junction.
10. The method for forming a test structure according to claim 9, wherein: Forming strip-shaped a plurality of first active regions on a well region of a substrate includes: forming a plurality of spaced-apart first isolation structures on the substrate; using an implantation mask to form a continuous well region in the area where the first isolation structures are located, and defining the first active regions between adjacent first isolation structures within the well region.
11. The method for forming a test structure according to claim 9, wherein: Forming the strip-shaped auxiliary structure.
12. The method for forming a test structure according to claim 9, wherein: Forming a first contact on the first heavily doped region and leading out a first lead from the first contact.
13. The method for forming a test structure according to claim 9, wherein: Form a second isolation structure to form a second active region together with the first active region. The second active region is spaced from the first active region by the second isolation structure, and the second active region is heavily doped with a second conductivity type different from the first conductivity type to form a second heavily doped region; And form a second contact on the second heavily doped region and lead out a second lead from the second contact.
14. The method for forming a test structure according to claim 9, wherein: A group of test structures with the same width of the first active region formed, while the widths of the first parts of the first active region covered by the auxiliary structure are different, thereby forming the first heavily doped regions with different widths, and use the extrapolation method to evaluate the electrical properties of the first PN junction interface when the second part of the first active region approaches zero.
15. The method for forming a test structure according to claim 9, wherein: A group of test structures with the same width of the first parts of the first active region covered by the auxiliary structure, while the overall widths of the first active region are different, thereby forming the first heavily doped regions with different widths, and use the extrapolation method to evaluate the electrical properties of the first PN junction interface when the second part of the first active region approaches zero.