Impedance matching current sharing circuit suitable for phase-shifted full-bridge topology primary-parallel and secondary-parallel

Abstract

The invention discloses an impedance matching current-sharing circuit suitable for phase-shifted full-bridge topology primary parallel-secondary parallel-connection, and relates to a topological structure in a power supply, an RC driving time-delay circuit is added between a control chip and each driving chip, the RC driving time-delay circuit comprises four groups or eight groups of RC networks, and each group of RC network comprises a first resistor, a capacitor and a second resistor; one end of the first resistor is connected with a PWM signal pin of the control chip, and the other end of the first resistor is connected with a signal input end of the driving chip, one end of the capacitor and one end of the second resistor; the capacitor is connected with the second resistor in parallel, and after the capacitor is connected with the second resistor in parallel, one end is connected with the signal input end of the driving chip, and the other end is connected with the ground; according to the invention, through the impedance matching RC network, the current sharing effect of multi-path phase-shifted full-bridge main power topology parallel connection is realized.

Description

Technical Field

[0001] The present invention relates to the series - parallel connection of the internal topology of a power supply, and particularly to an impedance - matching current - sharing circuit applicable to the primary - parallel and secondary - parallel of a phase - shifted full - bridge topology. Background Art

[0002] With the continuous development of power electronics technology, high - frequency high - power power supplies have gradually penetrated into fields such as communication, computers, medical treatment, and military industry. At the same time, with the continuous development of equipment, in high - power application scenarios, higher requirements are put forward for the current and power levels of converters, and the power level of a single power supply device is continuously improved.

[0003] The series - parallel connection of the internal topology of a power supply is an effective means to improve the power level of a single power supply device. For the topology inside the power supply, IPOP (primary - parallel and secondary - parallel), IPOS (primary - parallel and secondary - series), and ISOP (primary - series and secondary - parallel) are common series - parallel methods for improving the power level. However, for application scenarios with relatively large primary and secondary side currents, the IPOP topology parallel method is generally selected. For the IPOP topology parallel method, there are various topology current - sharing control methods. The literature "Research on Two - stage Interleaved Parallel DC / DC Topology Based on Phase - shifted Full - Bridge" uses the interleaved parallel method to realize the parallel connection of two full - bridge topologies. Implementing current - sharing of the internal topology of the power supply using interleaved parallel technology is relatively complex in terms of the control circuit. Other similar power - supply - to - power - supply parallel current - sharing methods all require relatively complex control methods. Summary of the Invention

[0004] In view of the above problems, the object of the present invention is to provide an impedance - matching current - sharing technology applicable to the primary - parallel and secondary - parallel of a phase - shifted full - bridge topology, which directly matches the impedance of the power - supply parallel topology through an RC network, and then realizes the current - sharing operation of the parallel topology.

[0005] To achieve the above object, the technical solution adopted by the present invention is: an impedance - matching current - sharing circuit applicable to the primary - parallel and secondary - parallel of a phase - shifted full - bridge topology, characterized in that: an RC drive delay circuit is added between the control chip and each drive chip, and the RC drive delay circuit includes four or eight groups of RC networks, and each group of RC networks includes a first resistor, a capacitor, and a second resistor; one end of the first resistor is connected to the PWM signal pin of the control chip, and the other end is connected to the signal input terminal of the drive chip, one end of the capacitor, and one end of the second resistor; the capacitor is in parallel with the second resistor, and after the capacitor and the second resistor are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground.

[0006] When the RC drive delay circuit includes four groups of RC networks, the four groups of RC networks respectively include: resistor R1, capacitor C1, and resistor R11; resistor R2, capacitor C2, and resistor R12; resistor R3, capacitor C3, and resistor R13; resistor R4, capacitor C4, and resistor R14; One end of resistor R1 is connected to the C pin of the control chip's PWM signal, and the other end of resistor R1 is connected to the signal input terminal of the drive chip, one end of capacitor C1, and one end of resistor R11; Capacitor C1 is in parallel with resistor R11. After capacitor C1 and resistor R11 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R2 is connected to the D pin of the control chip's PWM signal, and the other end of resistor R2 is connected to the signal input terminal of the drive chip, one end of capacitor C2, and one end of resistor R12; Capacitor C2 is in parallel with resistor R12. After capacitor C2 and resistor R12 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R3 is connected to the A pin of the control chip's PWM signal, and the other end of resistor R3 is connected to the signal input terminal of the drive chip, one end of capacitor C3, and one end of resistor R13; Capacitor C3 is in parallel with resistor R13. After capacitor C3 and resistor R13 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R4 is connected to the B pin of the control chip's PWM signal, and the other end of resistor R4 is connected to the signal input terminal of the drive chip, one end of capacitor C4, and one end of resistor R14; Capacitor C4 is in parallel with resistor R14. After capacitor C4 and resistor R14 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground.

[0007] When the RC drive delay circuit includes eight groups of RC networks, the other four groups of RC networks respectively include: resistor R5, capacitor C5 and resistor R15; resistor R6, capacitor C6 and resistor R16; resistor R7, capacitor C7 and resistor R17; resistor R8, capacitor C8 and resistor R18; One end of resistor R5 is connected to the C pin of the control chip's PWM signal, and the other end of resistor R5 is connected to the signal input terminal of the drive chip, one end of capacitor C5, and one end of resistor R15; Capacitor C5 is in parallel with resistor R15. After capacitor C5 and resistor R15 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R6 is connected to the D pin of the control chip's PWM signal, and the other end of resistor R6 is connected to the signal input terminal of the drive chip, one end of capacitor C6, and one end of resistor R16; Capacitor C6 is in parallel with resistor R16. After capacitor C6 and resistor R16 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R7 is connected to the A pin of the control chip's PWM signal, and the other end of resistor R7 is connected to the signal input terminal of the drive chip, one end of capacitor C7, and one end of resistor R17; Capacitor C7 is in parallel with resistor R17. After capacitor C7 and resistor R17 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to ground; One end of resistor R8 is connected to the B pin of the control chip's PWM signal, and the other end of resistor R8 is connected to the signal input terminal of the driver chip, one end of capacitor C8, and one end of resistor R18; capacitor C8 is in parallel with resistor R18. After capacitor C8 and resistor R18 are in parallel, one end is connected to the signal input terminal of the driver chip, and the other end is connected to ground.

[0008] Among them, the fifth group of RC networks is in parallel with the first group of RC networks; the sixth group of RC networks is in parallel with the second group of RC networks; the seventh group of RC networks is in parallel with the third group of RC networks; the eighth group of RC networks is in parallel with the fourth group of RC networks.

[0009] The working principle of the impedance matching current sharing method in the present invention is: by fine-tuning the duty cycle parameter through the RC network, the change of the main power impedance is realized, and further the impedance matching and the current sharing of the multi-path parallel circuit are realized.

[0010] Implementation method: For the parallel main power topology, add an RC impedance matching network to the driving signal of the leading arm of the main power topology where the output current is small in order to improve the output current capacity of that path.

[0011] Compared with the prior art, the technical solution adopted by the present invention has the following beneficial effects: (1) The present invention realizes the current sharing effect of the multi-path phase-shifted full-bridge main power topology in parallel through the impedance matching RC network.

[0012] (2) The present invention overcomes the disadvantages of complex implementation of control methods such as interleaved parallel connection and current sharing closed loop through the impedance matching RC network.

[0013] (3) The implementation method of the present invention is simple and low-cost. Only by setting multiple RC networks on the drive circuit and adjusting the parameters can the multi-path current sharing effect be realized. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of an impedance matching current sharing circuit topology applicable to the original parallel and secondary parallel of the phase-shifted full-bridge topology provided in this embodiment.

[0015] Figure 2 It is a schematic diagram of the parallel connection of two-phase-shifted full-bridge main power topologies provided in this embodiment.

[0016] Figure 3 It is a driving waveform diagram of the parallel connection of two-phase-shifted full-bridge main power topologies provided in this embodiment.

[0017] Figure 4 It is a schematic diagram of the function of the RC impedance matching network provided in this embodiment. Detailed Embodiment

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Any modification made on the basis of the technical solutions according to the technical idea proposed by the present invention belongs to the protection scope of the present invention.

[0019] As Figure 1 shown, an impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of a phase-shifted full-bridge topology provided in this embodiment adds an RC drive delay circuit between the control chip and each drive chip. According to requirements, the RC drive delay circuit can include four groups or eight groups of RC networks. This embodiment provides an eight-group RC network structure, and each group of RC networks includes a first resistor, a capacitor, and a second resistor; one end of the first resistor is connected to the PWM signal pin of the control chip, and the other end is connected to the signal input end of the drive chip, one end of the capacitor, and one end of the second resistor; the capacitor is connected in parallel with the second resistor, and after the capacitor is connected in parallel with the second resistor, one end is connected to the signal input end of the drive chip, and the other end is connected to the ground.

[0020] One end of resistor R1 is connected to the PWM signal pin of the control chip, and the other end of resistor R1 is connected to the signal input end of the drive chip, one end of capacitor C1, and one end of resistor R11. Capacitor C1 is connected in parallel with resistor R11, and after capacitor C1 is connected in parallel with resistor R11, one end is connected to the signal input end of the drive chip, and the other end is connected to the ground.

[0021] One end of resistor R2 is connected to the PWM signal D pin of the control chip, and the other end of resistor R2 is connected to the signal input end of the drive chip, one end of capacitor C2, and one end of resistor R12; capacitor C2 is connected in parallel with resistor R12, and after capacitor C2 is connected in parallel with resistor R12, one end is connected to the signal input end of the drive chip, and the other end is connected to the ground; One end of resistor R3 is connected to the PWM signal A pin of the control chip, and the other end of resistor R3 is connected to the signal input end of the drive chip, one end of capacitor C3, and one end of resistor R13; capacitor C3 is connected in parallel with resistor R13, and after capacitor C3 is connected in parallel with resistor R13, one end is connected to the signal input end of the drive chip, and the other end is connected to the ground; One end of resistor R4 is connected to the PWM signal B pin of the control chip, and the other end of resistor R4 is connected to the signal input end of the drive chip, one end of capacitor C4, and one end of resistor R14; capacitor C4 is connected in parallel with resistor R14, and after capacitor C4 is connected in parallel with resistor R14, one end is connected to the signal input end of the drive chip, and the other end is connected to the ground.

[0022] One end of resistor R5 is connected to the C pin of the PWM signal of the control chip, and the other end of resistor R5 is connected to the signal input terminal of the driver chip, one end of capacitor C5, and one end of resistor R15; capacitor C5 is in parallel with resistor R15. After capacitor C5 and resistor R15 are in parallel, one end is connected to the signal input terminal of the driver chip, and the other end is connected to ground; One end of resistor R6 is connected to the D pin of the PWM signal of the control chip, and the other end of resistor R6 is connected to the signal input terminal of the driver chip, one end of capacitor C6, and one end of resistor R16; capacitor C6 is in parallel with resistor R16. After capacitor C6 and resistor R16 are in parallel, one end is connected to the signal input terminal of the driver chip, and the other end is connected to ground; One end of resistor R7 is connected to the A pin of the PWM signal of the control chip, and the other end of resistor R7 is connected to the signal input terminal of the driver chip, one end of capacitor C7, and one end of resistor R17; capacitor C7 is in parallel with resistor R17. After capacitor C7 and resistor R17 are in parallel, one end is connected to the signal input terminal of the driver chip, and the other end is connected to ground; One end of resistor R8 is connected to the B pin of the PWM signal of the control chip, and the other end of resistor R8 is connected to the signal input terminal of the driver chip, one end of capacitor C8, and one end of resistor R18; capacitor C8 is in parallel with resistor R18. After capacitor C8 and resistor R18 are in parallel, one end is connected to the signal input terminal of the driver chip, and the other end is connected to ground.

[0023] Taking the parallel connection of two-phase phase-shifted full-bridge main power topologies as an example, R1 and R11, R2 and R12, R3 and R13, R4 and R14, R5 and R15, R6 and R16, R7 and R17, R8 and R18 form a voltage-dividing network. The drive signals PWMA, PWMB, PWMC, and PWMD output by UCC3895 are 12V. The backend driver chip selects IXDN614SI. When meeting the requirements of the input signals of the backend driver chip, the voltage-dividing resistors can be selected in a ratio of 1:10. For example, R1, R2, R3, R4, R5, R6, R7, and R8 select 1kΩ resistors, and R11, R12, R13, R14, R15, R16, R17, and R18 select 10kΩ. C1, C2, C3, C4, C5, C6, C7, and C8 are not installed during the circuit board assembly. When the output current of path A is small, install 100pF capacitors on C1 and C2, and debug whether the two paths are current-sharing. If the current of path A increases and exceeds that of path B, weaken the impedance matching network effect by reducing the resistances of R1 and R2 until the two paths are current-sharing. Generally, installing 100pF capacitors is sufficient to ensure the current-sharing adjustment of the two paths.

[0024] The working principle of the impedance matching current-sharing method: The core of the impedance matching current-sharing method is to fine-tune the duty cycle parameter through the RC network, thereby realizing the change of the main power impedance, further realizing the impedance matching and the current-sharing of the multi-path parallel circuit.

[0025] Implementation method: For the parallel main power topology, add an RC impedance matching network to the driving signal of the leading leg of the main power topology with a smaller output current in order to improve the output current capacity of that path.

[0026] Taking the parallel connection of two-phase-shifted full-bridge topologies as an example, the main power circuit is as Figure 2 shown. The driving signals of the two main power topologies come from the same UCC3895 control chip. When the impedance matching RC network is not in effect, the driving signals of the two main power topologies are the same, as Figure 3 shown. G1, G2, G3, and G4 drive the main power topology of path A, and G5, G6, G7, and G8 drive the main power topology of path B. The two signals are the same, where G1, G2 and G5, G6 are the driving signals of the leading legs. When connected in parallel, since the main power parameters of the two paths are not exactly the same, assuming that the output current of the main power circuit of path A is smaller, the parameters of R1, C1, R11, R2, C2, and R12 need to be configured to make the driving signal of the leading leg of path A lag, as Figure 4 shown. Since the driving signal of the leading leg has lagged, the duty cycle of path A has changed. As can be seen through Figure 4 this, the RC impedance matching network changes the duty cycle from t1 to t2, and the duty cycle increases. Therefore, the output current of the main power topology of path A increases, and the currents of the two main power topologies are equalized.

[0027] Although the present invention has been disclosed above with preferred embodiments, the embodiments and drawings are not used to limit the present invention. Any person familiar with this art can make various changes or modifications without departing from the spirit and scope of the present invention, but they are still within the protection scope of the present invention. Therefore, the protection scope of the present invention should be defined by the protection scope of the claims of this application.

Claims

1. An impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology, characterized in that: An RC drive delay circuit is added between the control chip and each drive chip. The RC drive delay circuit includes four or eight groups of RC networks, and each group of RC networks includes a first resistor, a capacitor, and a second resistor. One end of the first resistor is connected to the PWM signal pin of the control chip, and the other end is connected to the signal input terminal of the drive chip, one end of the capacitor, and one end of the second resistor. The capacitor is connected in parallel with the second resistor. After the capacitor and the second resistor are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground.

2. The impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology according to claim 1, wherein: When the RC drive delay circuit includes four groups of RC networks, the four groups of RC networks respectively include: resistor R1, capacitor C1, and resistor R11; resistor R2, capacitor C2, and resistor R12; resistor R3, capacitor C3, and resistor R13; resistor R4, capacitor C4, and resistor R14; One end of resistor R1 is connected to the PWM signal C pin of the control chip, and the other end of resistor R1 is connected to the signal input terminal of the drive chip, one end of capacitor C1, and one end of resistor R11. Capacitor C1 is connected in parallel with resistor R11. After capacitor C1 and resistor R11 are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground. One end of resistor R2 is connected to the PWM signal D pin of the control chip, and the other end of resistor R2 is connected to the signal input terminal of the drive chip, one end of capacitor C2, and one end of resistor R12. Capacitor C2 is connected in parallel with resistor R12. After capacitor C2 and resistor R12 are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground. One end of resistor R3 is connected to the PWM signal A pin of the control chip, and the other end of resistor R3 is connected to the signal input terminal of the drive chip, one end of capacitor C3, and one end of resistor R13. Capacitor C3 is connected in parallel with resistor R13. After capacitor C3 and resistor R13 are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground. One end of resistor R4 is connected to the PWM signal B pin of the control chip, and the other end of resistor R4 is connected to the signal input terminal of the drive chip, one end of capacitor C4, and one end of resistor R14. Capacitor C4 is connected in parallel with resistor R14. After capacitor C4 and resistor R14 are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground.

3. The impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology according to claim 2, wherein: When the RC drive delay circuit includes eight groups of RC networks, the other four groups of RC networks respectively include: resistor R5, capacitor C5, and resistor R15; resistor R6, capacitor C6, and resistor R16; resistor R7, capacitor C7, and resistor R17; resistor R8, capacitor C8, and resistor R18; One end of resistor R5 is connected to the PWM signal C pin of the control chip, and the other end of resistor R5 is connected to the signal input terminal of the drive chip, one end of capacitor C5, and one end of resistor R15. Capacitor C5 is connected in parallel with resistor R15. After capacitor C5 and resistor R15 are connected in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground. One end of resistor R6 is connected to the D pin of the PWM signal of the control chip, and the other end of resistor R6 is connected to the signal input terminal of the drive chip, one end of capacitor C6, and one end of resistor R16; Capacitor C6 is in parallel with resistor R16. After capacitor C6 and resistor R16 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground; One end of resistor R7 is connected to the A pin of the PWM signal of the control chip, and the other end of resistor R7 is connected to the signal input terminal of the drive chip, one end of capacitor C7, and one end of resistor R17; Capacitor C7 is in parallel with resistor R17. After capacitor C7 and resistor R17 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground; One end of resistor R8 is connected to the B pin of the PWM signal of the control chip, and the other end of resistor R8 is connected to the signal input terminal of the drive chip, one end of capacitor C8, and one end of resistor R18; Capacitor C8 is in parallel with resistor R18. After capacitor C8 and resistor R18 are in parallel, one end is connected to the signal input terminal of the drive chip, and the other end is connected to the ground.

4. A impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology according to claim 3, characterized in that: The fifth group of RC networks is in parallel with the first group of RC networks; The sixth group of RC networks is in parallel with the second group of RC networks; The seventh group of RC networks is in parallel with the third group of RC networks; The eighth group of RC networks is in parallel with the fourth group of RC networks.

5. A impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology according to any one of claims 1-4, characterized in that: The control chip uses UCC3895; The drive chip selects IXDN614SI.

6. A impedance matching current sharing circuit applicable to the primary parallel and secondary parallel of the phase-shifted full-bridge topology according to any one of claims 1-4, characterized in that: In each group of RC networks, the ratio of the first resistor to the second resistor is 1:10.

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