Frequency jittering circuit

Abstract

The invention discloses a frequency jittering circuit, an oscillation stage of the frequency jittering circuit is provided with a comparator COMP1 and an inverter INV1, and is matched with the variation of reference voltage VREF formed by a voltage source to realize the function of a hysteresis comparator, and a reference voltage control stage of the frequency jittering circuit comprises a fourth NMOS (N-channel Metal Oxide Semiconductor) tube NM4, a fifth PMOS (P-channel Metal Oxide Semiconductor) tube PM5, a fourth NMOS tube NM4, a fifth PMOS tube PM5, a fourth NMOS tube NM4, a fifth PMOS tube PM5 and a fourth NMOS tube NM5; a folded input stage of the transconductance amplifier composed of PMOS tubes is connected with other circuit voltages VM and comparison voltage VCAP, a fourteenth PMOS tube PM14, a third resistor R3 and a second capacitor C2 to form a reference voltage circuit used for generating oscillator reference voltage VOSCREF, the oscillator reference voltage VOSCREF is input into a cascode stage to convert the current difference of the folded input stage, and the current difference of the folded input stage is converted into the reference voltage VCAP. And almost linear transconductance amplification is realized. The frequency jittering function is realized, the noise of the switching power supply is reduced, electromagnetic compatibility is easier to realize, and the labor of a power supply designer is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and more specifically relates to the field of switching power supplies, particularly a frequency dithering circuit. Background Art

[0002] Generally, when a switching power supply is operating, it is prone to generating a large amount of electromagnetic interference noise. If not suppressed, it is likely to interfere with the normal operation of some devices and circuits.

[0003] When the switching power supply operates at a fixed frequency, the amplitude of its noise is high, and it is more difficult to suppress the noise. Even in special cases, it may be impossible to suppress it within the required range, greatly increasing the design cost. The frequency dithering technology can disperse the originally concentrated noise energy over a larger frequency spectrum range, thereby reducing the amplitude of the noise and making it easier to achieve electromagnetic compatibility design. Summary of the Invention

[0004] The object of the present invention is a frequency dithering circuit, which solves the defects of the prior art, is simple and reliable, applicable to the CMOS process, and at the same time, the capacitors in the circuit are small, facilitating integration and reducing the layout area.

[0005] To achieve the above technical object, the present invention provides a frequency dithering circuit, which includes an oscillation stage as the first-stage circuit STAGE1 and a reference voltage control stage as the second-stage circuit STAGE2, wherein: the oscillation stage includes: a comparator COMP1 and an inverter INV1, which cooperate with the variation of the reference voltage VREF formed by the high voltage VH and the low voltage VL of the voltage source to realize the function of a hysteresis comparator. The first and second PMOS transistors PM1 and PM2 form a current mirror for proportionally replicating the current of the current source I1. The second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror. The first and second NMOS transistors NM1 and NM2 form a current mirror. The fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into the comparison voltage VCAP node of the comparator COMP1. The third NMOS transistor NM3 is used to control whether the current of the comparison voltage VCAP node can flow into the second NMOS transistor NM2. The reference voltage control stage includes: the fifth PMOS transistor PM5 is a reference current source. The fourth NMOS transistor NM4 receives the current of the fifth PMOS transistor PM5 to generate a new bias voltage. The folded input stage of the transconductance amplifier composed of PMOS transistors is respectively connected to other circuit voltages VM and the comparison voltage VCAP. The fourteenth PMOS transistor PM14, the third resistor R3, and the second capacitor C2 form a reference voltage circuit for generating the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is input to the cascode stage to convert the current difference of the folded input stage, realizing almost linear transconductance amplification.

[0006] The present invention provides a frequency-dithering circuit, which provides an oscillation stage of a first-stage circuit STAGE1 and a reference voltage control stage of a second-stage circuit STAGE2. The frequency-dithering function can be realized through a simple circuit, so that the noise of the switching power supply is reduced, electromagnetic compatibility is more easily achieved, and the labor of power supply designers is reduced.

[0007] As a further improvement, the high voltage VH and the low voltage VL respectively pass through a first transmission gate TG1 and a second transmission gate TG2, and the input voltage VA and the output voltage VB of the inverter INV1 control the reference voltage VREF.

[0008] As a further improvement, the voltage of the high voltage VH is higher than the voltage of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high, the output voltage VB is low, the first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH; when the comparison voltage VCAP drops from high, the input voltage VA is low, the output voltage VB is high, the second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

[0009] As a further improvement, the ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2. The first, second, and third PMOS transistors PM1, PM2, and PM3 share a common source connected to the power supply VDD and a common gate connected to the current source I1. The first and second NMOS transistors NM1 and NM2 share a common source grounded and a common gate connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1. The drain of the first PMOS transistor PM1 is connected to the current source I1.

[0010] As a further improvement, the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3. The third NMOS transistor NM3 and the fourth PMOS transistor PM4 share a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB. The source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3. The comparison voltage VCAP is grounded through a first capacitor C1.

[0011] As a further improvement, the fifth and fourteenth PMOS transistors PM5 and PM14 have their common source connected to the power supply VDD and their gates are biased and connected. The drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded through the third resistor R3. The second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded. The common drain of the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5, and the gate of the fourth NMOS transistor NM4 is connected to its drain and its source is grounded.

[0012] As a further improvement, the sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and the resistor R form the folded input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6 and PM7 are common source and common gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective aspect ratio of 1:1, controlling the bias current of the folded input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective aspect ratio of 1:1. The two ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

[0013] As a further improvement, the fifth and sixth NMOS transistors NM5 and NM6 are common gate and connected to the bias node voltage VBN. The seventh and eighth NMOS transistors NM7 and NM8 are common gate and connected to the drain of the fifth PMOS transistor PM5 and their sources are grounded. The sources and drains of the fifth and seventh NMOS transistors NM5 and NM7 are connected and connected to the drain of the eighth PMOS transistor PM8. The sources and drains of the sixth and eighth NMOS transistors NM6 and NM8 are connected and connected to the drain of the ninth PMOS transistor PM9. The tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10, PM11, PM12, and PM13 are common source with the fifth PMOS transistor PM5. The tenth and thirteenth PMOS transistors PM10 and PM13 are common gate and connected to the drains of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5. The eleventh and twelfth PMOS transistors PM11 and PM12 are common gate and connected to the drains of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference of the tenth and eleventh PMOS transistors PM10 and PM11.

[0014] As a further improvement, the ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference of the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a common gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 shares a common drain with the tenth NMOS transistor NM10 and is connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a common gate and are connected to the current source I1.

[0015] As a further improvement, the gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 to be directly biased by the first-stage circuit STAGE1. The ratio of the effective width-to-length ratios of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the ratio of the effective width-to-length ratios of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 are a 1:1 current mirror. The resistor R is composed of a series of first and second resistors R1 and R2, and the resistance value of the resistor R is equal to the sum of the resistance values of the first and second resistors R1 and R2. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the circuit principle of the present invention; Figure 2 is a simulation schematic diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0018] As Figures 1 to 2 shown, the present invention provides a frequency jitter circuit, which provides embodiments with relative set NMOS and PMOS transistors, and can be correspondingly transformed according to common knowledge in the art under the technical solutions and effects disclosed in the present invention.

[0019] The present invention provides a frequency hopping circuit, which includes an oscillation stage as the first-stage circuit STAGE1 and a reference voltage control stage as the second-stage circuit STAGE2, wherein: The oscillation stage includes: a comparator COMP1 and an inverter INV1, which cooperate with the variation of the reference voltage VREF formed by the high voltage VH and the low voltage VL of the voltage source to realize the function of a hysteresis comparator. The first and second PMOS transistors PM1 and PM2 form a current mirror for proportionally replicating the current of the current source I1. The second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror. The first and second NMOS transistors NM1 and NM2 form a current mirror. The fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into the comparison voltage VCAP node of the comparator COMP1. The third NMOS transistor NM3 is used to control whether the current of the comparison voltage VCAP node can flow into the second NMOS transistor NM2. The reference voltage control stage includes: the fifth PMOS transistor PM5 is a reference current source. The fourth NMOS transistor NM4 receives the current of the fifth PMOS transistor PM5 to generate a new bias voltage. The folded input stage of a transconductance amplifier composed of PMOS transistors is respectively connected to other circuit voltages VM and the comparison voltage VCAP. The fourteenth PMOS transistor PM14, the third resistor R3, and the second capacitor C2 form a reference voltage circuit for generating the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is input to a cascode stage to convert the current difference of the folded input stage, realizing almost linear transconductance amplification.

[0020] The present invention provides a frequency hopping circuit, which provides an oscillation stage of the first-stage circuit STAGE1 and a reference voltage control stage of the second-stage circuit STAGE2, and can realize the frequency hopping function with a simple circuit, reduce the noise of the switching power supply, make it easier to achieve electromagnetic compatibility, and reduce the labor of power supply designers.

[0021] As a further improvement, the high voltage VH and the low voltage VL respectively pass through the first transmission gate TG1 and the second transmission gate TG2, and the input voltage VA and the output voltage VB of the inverter INV1 control the reference voltage VREF.

[0022] As a further improvement, the voltage of the high voltage VH is higher than the voltage of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high and the output voltage VB is low, and the first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH. When the comparison voltage VCAP drops from high, the input voltage VA is low and the output voltage VB is high, and the second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

[0023] As a further improvement, the ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2. The first, second, and third PMOS transistors PM1, PM2, and PM3 share a common source connected to the power supply VDD and a common gate connected to the current source I1. The first and second NMOS transistors NM1 and NM2 share a common source connected to the ground and a common gate connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1. The drain of the first PMOS transistor PM1 is connected to the current source I1.

[0024] As a further improvement, the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3. The third NMOS transistor NM3 and the fourth PMOS transistor PM4 share a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB. The source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3. The comparison voltage VCAP is grounded through the first capacitor C1.

[0025] As a further improvement, the fifth and fourteenth PMOS transistors PM5 and PM14 share a common source connected to the power supply VDD and their gates are biased. The drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded through the third resistor R3. The second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded. The common drain of the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5. The gate and drain of the fourth NMOS transistor NM4 are connected and its source is grounded.

[0026] As a further improvement, the sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and the first and second resistors R1 and R2 form the folded input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6 and PM7 share a common source and a common gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective width-to-length ratio of 1:1, controlling the bias current of the folded input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective width-to-length ratio of 1:1. The two ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

[0027] As a further improvement, the fifth and sixth NMOS transistors NM5 and NM6 share a common gate and are connected to the bias node voltage VBN. The seventh and eighth NMOS transistors NM7 and NM8 share a common gate and are connected to the drain of the fifth PMOS transistor PM5 with their sources grounded. The sources and drains of the fifth and seventh NMOS transistors NM5 and NM7 are connected together and are connected to the drain of the eighth PMOS transistor PM8. The sources and drains of the sixth and eighth NMOS transistors NM6 and NM8 are connected together and are connected to the drain of the ninth PMOS transistor PM9. The tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10, PM11, PM12, and PM13 share a common source with the fifth PMOS transistor PM5. The tenth and thirteenth PMOS transistors PM10 and PM13 share a common gate and are connected to the drains of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5. The eleventh and twelfth PMOS transistors PM11 and PM12 share a common gate and are connected to the drains of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference between the tenth and eleventh PMOS transistors PM10 and PM11.

[0028] As a further improvement, the ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference between the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a common gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 and the tenth NMOS transistor NM10 share a common drain and are connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a common gate and are connected to the current source I1. It should be noted that the gates (GATE terminals) of these two transistors, PM5 and PM14, can be biased using other parts as needed. That is to say, PM5 and PM14 can have multiple specific embodiments. According to requirements, they can be biased by connecting to other places, adopting the same or similar technical means to achieve the same technical effects and purposes.

[0029] As a further improvement, the gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 to be directly biased by the first-stage circuit STAGE1. The ratio of the effective width-to-length ratios of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the ratio of the effective width-to-length ratios of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 form a current mirror with a ratio of 1:1. The resistor R is composed of a first resistor R1 and a second resistor R2 connected in series, and the resistance value of the resistor R is equal to the sum of the resistance values of the first and second resistors R1 and R2. Preferably, the resistance values of the first and second resistors are equal.

[0030] The following specifically describes the circuit principle of the present invention in conjunction with the preferred embodiment of the present invention shown in Figure 1 and Figure 2 shown.

[0031] STAGE1: This stage is an oscillation stage.

[0032] VH and VL are voltage sources provided by other parts. The voltage of VREF is controlled by transmission gates TG1 and TG2 controlled by VA and VB. Among them, the voltage of VH is higher than that of VL. When VCAP rises from low, VA is high and VB is low, and TG1 is turned on, VREF = VH; when VCAP drops from high, VA is low and VB is high, and TG2 is turned on, VREF = VL. COMP1 is a comparator, and INV1 is an inverter. In cooperation with the change of VREF, this part realizes the function of a hysteresis comparator, and the hysteresis range is between VL and VH.

[0033] I1 is a current source. PM1 and PM2 form a current mirror for proportionally replicating the current of I1. For the convenience of description, the ratio (or effective width-to-length ratio) of PM1 and PM2 here is 1:1, but it can be adjusted according to the actual situation in actual use.

[0034] Similarly, PM3 and PM2 form a current mirror, and NM1 and NM2 form a current mirror. The main feature of the current mirror here is that if the ratio of the effective width-to-length ratio of PM2 to the effective width-to-length ratio of PM3 is K1, then the ratio of the effective width-to-length ratio of NM1 to the effective width-to-length ratio of NM2 is also K1. At the same time, the value of K1 is generally much greater than 1 to achieve small currents for PM3 and NM2. Through such a design, the current when the PM3 transistor operates in the saturation region can be the same as the current when the NM2 transistor operates in the saturation region, that is: IPM3 = INM2 PM4 is used to control whether the current of PM3 can flow into the VCAP node; NM3 is used to control whether the current of the VCAP node can flow into NM2. When VB is at a high level, NM3 conducts and PM4 does not conduct, and the capacitor C1 discharges through the current INM2 of NM2; when VB is at a low level, NM3 does not conduct and PM4 conducts, and the capacitor C1 is charged through the current IPM3 of PM3. The cycle of the dither frequency can be controlled through the charge and discharge cycle of C1. If the highest level of the VCAP capacitor is VH and the lowest level is VL, then the cycle of the dither frequency is:

[0035] The working principle of this oscillator can be described as follows: when VCAP is lower than VL, VB is at a low level, and PM3 charges the C1 capacitor through PM4, and the VCAP voltage rises at a fixed slope. At this time, VREF = VH; when it rises above VH, the comparator flips, VB is at a high level, and NM2 discharges the C1 capacitor through NM3, and the VCAP voltage drops at a fixed slope. At this time, VREF = VL. After VCAP drops to VL, the next cycle is carried out.

[0036] STAGE2: This is the reference voltage control stage.

[0037] PM5 is a reference current source. For convenience, the GATE terminal of PM5 here is directly biased by STAGE1 (in actual applications, this current source can be taken from a reference current source elsewhere).

[0038] NM4 receives the current of PM5 and generates a new bias voltage for the voltage bias of other parts of this stage. PM6, PM7, PM8, PM9 and R1, R2 form the folded input stage of a transconductance amplifier (the part between PM6 and PM13 in the figure, including the transconductance amplifier composed of PM6 and PM13). Among them, PM6 and PM7 are current sources with an effective aspect ratio of 1:1, which control the bias current of the folded input stage. PM8 and PM9 form a differential pair with an effective aspect ratio of 1:1, and make its transconductance: gm = gm8 = gm9 R1 and R2 are used to limit the effective transconductance Gm of this stage. At the same time, it can make this stage have a very wide linear range, so that the output VOSCREF voltage of this stage changes almost linearly within a certain range. Here, R1 = R2 = R. In this way, the effective transconductance of the folded input stage can be calculated as:

[0039] It can be seen from the above formula that if R is large enough, the nonlinear problem of gm can be ignored, and the effective Gm of this stage is almost only affected by R. Further, the difference between the current IPM8 of PM8 and the current IPM9 of PM9 can be written as:

[0040] Where VM is generated by other circuits, and its value is greater than VL and less than VH. Usually, VM can be configured as: VM = (VL + VH) / 2 PM10, PM11, NM5, NM6, NM7, and NM8 are cascode stages, which are used to convert the current difference of the folded input stage into the current difference between PM10 and PM11. Among them, NM7 and NM8 are 1:1 cascode current mirrors, which are used to set the bias current. NM5 and NM6 are common-gate stages, which are mainly used to isolate the voltages at the drains of PM8 and PM9 without affecting their currents, and at the same time can reduce the OFFSET of the differential pair PM8 and PM9. VBN is used to bias NM5 and NM6. For simplicity, the specific bias circuit of VBN is not given here.

[0041] Since the currents of NM7 and NM8 are equal, the current difference between PM9 and PM8 will be directly reflected in PM10 and PM11. PM10 and PM11 use the diode connection method (the gate is connected to the drain). It can be known that:

[0042] PM12, PM13, NM9, and NM10 are used to process the above-mentioned current difference. Among them, PM10 and PM13 form a current mirror, and the ratio of their effective width-to-length ratios is K2; at the same time, PM11 and PM12 form a current mirror, and the ratio of their effective width-to-length ratios is also K2. NM9 and NM10 are 1:1 current mirrors. NM9 receives the current of PM12 to make the current of NM10 equal to that of PM12. Therefore, finally, the voltage difference between PM9 and PM8 is converted into the current difference between PM13 and NM10, thereby realizing almost linear transconductance amplification. The current difference between PM13 and NM10 can be written as:

[0043] PM14, R3, and C2 form a reference voltage circuit, which is used to generate VOSCREF. This voltage is used to supply power to the linear voltage-controlled oscillator to achieve the function of frequency jitter. The linear voltage-controlled oscillator is not discussed here. The gate (GATE terminal) of PM14 can be biased elsewhere. Preferably, PM14 is a reference current source, which is generated by using the BANDGAP technology here and has a low temperature coefficient. R3 and the BANDGAP use the same type of resistor, and the two can cancel the temperature coefficient, so that VOSCREF can also have a low temperature coefficient. C2 is used to filter out system noise to make VOSCREF have better stability. From the figure, it is easy to obtain the expression of VOSCREF:

[0044] In normal applications, the maximum value of the second term in the parentheses of the above formula is less than 10% of the first term, and the typical value is about 3%. It is also easy to see from the above formula that VOSCREF is generated by two parts of current flowing through the resistor, which can be understood as including a DC term and an AC term. Among them, the former part IPM14 is the DC term, and the latter part is the AC term.

[0045] To better understand the circuit principle, reference can be made to Figure 2 the simulation image.

[0046] The first row shows the levels of VL / VM / VH, where VL is about 0.4V, VM is about 1.2V, and VH is about 2.0V. At 2.1ms in the figure for VL, a narrow pulse can be seen, which is caused by the transmission gate during state switching and does not affect the actual working condition.

[0047] The second row shows the voltage value of node B, and the third row shows the VCAP voltage, which is the voltage of capacitor C1. When the voltage of capacitor C1 rises from low, node B is at a low level. At this time, PM3 charges capacitor C1 through PM4, and the charging current of PM3 is constant, so the VCAP voltage rises at a fixed slope; when the VCAP voltage rises above VH, the voltage of node B flips, PM4 disconnects, NM3 conducts, and NM2 discharges capacitor C1 through NM3. Since the discharge current is a constant current discharge and the magnitude of the discharge current is equal to the charging current, during this process, the VCAP voltage drops at a fixed slope, and the absolute value of the dropping slope is equal to the rising slope.

[0048] The fourth row shows the VOSCREF voltage. The center value of the VOSCREF voltage is about 1.2V, the highest voltage is about 1.235V, and the lowest voltage is about 1.165V. Among them, the center value of 1.2V is determined by the DC term of the VOSCREF expression. It can be seen that when VCAP changes linearly, the VOSCREF voltage also changes linearly basically, and at the same time, VOSCREF is in phase with VCAP. The fluctuation of the VOSCREF voltage is about 1.2V + / - 3%.

[0049] The fifth row shows the OSC voltage, but due to the too high frequency of OSC, the specific frequency cannot be clearly seen from the figure. To solve this problem, the sixth row visualizes the OSC frequency value in the fifth row. It can be seen that the center level of OSC is about 375KHz, the highest frequency is about 385KHz, and the lowest frequency is about 365KHz. The frequency fluctuation of OSC is about 375KHz + / - 2.7%, which is basically the same as the fluctuation ratio of VOSCREF.

[0050] It should be understood that the scope to be protected by the present invention is not limited to the non-restrictive embodiments, and it should be understood that the non-restrictive embodiments are only illustrative examples. The substantial scope of protection required by this application is more reflected in the scope provided by the independent claims and their dependent claims.

Claims

1. A frequency-dithering circuit, which includes an oscillation stage as the first-stage circuit STAGE1 and a reference voltage control stage as the second-stage circuit STAGE2, and is characterized in that: The oscillation stage includes: a comparator COMP1 and an inverter INV1, which cooperate with the variation of the reference voltage VREF formed by the high voltage VH and the low voltage VL of the voltage source to realize the function of a hysteresis comparator. The first and second PMOS transistors PM1 and PM2 form a current mirror for proportionally replicating the current of the current source I1. The second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror. The first and second NMOS transistors NM1 and NM2 form a current mirror. The fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into the comparison voltage VCAP node of the comparator COMP1. The third NMOS transistor NM3 is used to control whether the current of the comparison voltage VCAP node can flow into the second NMOS transistor NM2. The reference voltage control stage includes: the fifth PMOS transistor PM5 is a reference current source. The fourth NMOS transistor NM4 receives the current of the fifth PMOS transistor PM5 to generate a new bias voltage. The folded input stage of the transconductance amplifier composed of PMOS transistors is respectively connected to other circuit voltages VM and the comparison voltage VCAP. The fourteenth PMOS transistor PM14, the third resistor R3, and the second capacitor C2 form a reference voltage circuit for generating the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is input to the cascode stage to convert the current difference of the folded input stage, realizing almost linear transconductance amplification.

2. The dither frequency circuit according to claim 1, wherein: The high voltage VH and the low voltage VL respectively pass through the first transmission gate TG1 and the second transmission gate TG2, and the input voltage VA and the output voltage VB of the inverter INV1 control the reference voltage VREF.

3. The dither frequency circuit according to claim 2, wherein: The voltage of the high voltage VH is higher than the voltage of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high and the output voltage VB is low. The first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH. When the comparison voltage VCAP drops from high, the input voltage VA is low and the output voltage VB is high. The second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

4. A dithering frequency circuit according to claim 3, characterized in that: The ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2. The first, second, and third PMOS transistors PM1, PM2, and PM3 have a common source connected to the power supply VDD and a common gate connected to the current source I1. The first and second NMOS transistors NM1 and NM2 have a common source grounded and a common gate connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1. The drain of the first PMOS transistor PM1 is connected to the current source I1.

5. A dither frequency circuit according to claim 4, wherein: The drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3. The third NMOS transistor NM3 and the fourth PMOS transistor PM4 share a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB. The source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3. The comparison voltage VCAP is grounded through the first capacitor C1.

6. A dither frequency circuit according to claim 1, characterized in that: The fifth and fourteenth PMOS transistors PM5 and PM14 share a common source connected to the power supply VDD and their gates are biased. The drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded through the third resistor R3. The second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded. The common drain of the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5. The gate and drain of the fourth NMOS transistor NM4 are connected and its source is grounded.

7. A dithering frequency circuit according to claim 6, wherein: The sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and the resistor R form the folded input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6 and PM7 share a common source and a common gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective aspect ratio of 1:1, controlling the bias current of the folded input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective aspect ratio of 1:

1. The two ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

8. A dithering frequency circuit according to claim 7, characterized in that: The fifth and sixth NMOS transistors NM5 and NM6 share a common gate and are connected to the bias node voltage VBN. The seventh and eighth NMOS transistors NM7 and NM8 share a common gate and are connected to the drain of the fifth PMOS transistor PM5 and their sources are grounded. The sources and drains of the fifth and seventh NMOS transistors NM5 and NM7 are connected and are connected to the drain of the eighth PMOS transistor PM8. The sources and drains of the sixth and eighth NMOS transistors NM6 and NM8 are connected and are connected to the drain of the ninth PMOS transistor PM9. The tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10, PM11, PM12, and PM13 share a common source with the fifth PMOS transistor PM5. The tenth and thirteenth PMOS transistors PM10 and PM13 share a common gate and are connected to the drain of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5. The eleventh and twelfth PMOS transistors PM11 and PM12 share a common gate and are connected to the drain of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference of the tenth and eleventh PMOS transistors PM10 and PM11.

9. The dither frequency circuit according to claim 8, wherein: The ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference of the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a common gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 shares a common drain with the tenth NMOS transistor NM10 and is connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a common gate and are connected to the current source I1.

10. A dither frequency circuit according to claim 9, characterized in that: The gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 to be directly biased by the first-stage circuit STAGE1. The ratio of the effective width-to-length ratios of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the ratio of the effective width-to-length ratios of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 form a 1:1 current mirror. The resistor R is composed of a series connection of a first resistor R1 and a second resistor R2. The resistance value of the resistor R is equal to the sum of the resistance values of the first and second resistors R1 and R2.

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