System-on-chip of hybrid architecture

Abstract

The invention provides an on-chip system with a hybrid architecture. The on-chip system is provided with a main power supply, a digital low-dropout voltage stabilizer, a charge pump low-dropout voltage stabilizer and a circuit module, wherein the main power supply is connected with the digital low-dropout voltage stabilizer and supplies power to the digital low-dropout voltage stabilizer; and the digital low dropout regulator is respectively connected with the charge pump low dropout regulator and the circuit module. Compared with the prior art, the digital low-dropout voltage stabilizer has the advantages that the voltage regulation speed is high, the power-on speed of the system-on-chip can be greatly increased, the output ripple of the digital low-dropout voltage stabilizer is reduced by the charge pump voltage stabilizer, power supply fluctuation is suppressed, and stable power supply voltage is provided for an analog circuit module in the system-on-chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a system on chip with a hybrid architecture. Background Art

[0002] In large-scale systems on chip, there are generally analog circuit modules and digital circuit modules. Among them, the digital circuit modules consume a large amount of power and have a slow power-on time. Circuits such as voltage-controlled oscillators and low-noise amplifiers in the analog circuit modules are sensitive to fluctuations in the power supply voltage, and may exhibit abnormal operating states when integrated with digital circuits under the same power supply.

[0003] Currently, the scale of systems on chip is getting larger, resulting in a large power consumption requirement and a long power-on process. In addition, large-scale systems on chip have various analog functional units in addition to a large number of digital modules. These circuits are sensitive to power supply noise and will be greatly interfered when integrated with digital modules in the same power supply network.

[0004] Therefore, it is an urgent problem for those skilled in the art to provide a system on chip with a hybrid architecture to solve the above problems. Summary of the Invention

[0005] The purpose of the present invention is to provide a system on chip with a hybrid architecture, which has a simple structure, is safe, effective, reliable and easy to operate, can improve the power-on speed of large-scale systems on chip, and provide a stable voltage close to the power supply voltage for the analog circuit modules in the system on chip.

[0006] Based on the above purpose, the technical solution provided by the present invention is as follows: A system on chip with a hybrid architecture, comprising: a main power supply, a digital low-dropout regulator, a charge pump low-dropout regulator, and a circuit module; The main power supply is connected to the digital low-dropout regulator; The digital low-dropout regulator is respectively connected to the charge pump low-dropout regulator and the circuit module.

[0007] Preferably, the circuit module includes: a digital circuit module and an analog circuit module; The digital low-dropout regulator is connected to the digital circuit module; The charge pump low-dropout regulator is respectively connected to the analog circuit module and the digital low-dropout regulator.

[0008] Preferably, the charge pump low-dropout regulator includes: a driving module, an error amplifier, a reference voltage circuit, a power transistor, and a feedback resistor; The driving module is connected to the error amplifier; The reference voltage circuit is connected to the non-inverting input terminal of the error amplifier; The error amplifier, the power transistor, and the feedback resistor form a closed-loop feedback network.

[0009] Preferably, the feedback resistor includes: a first resistor and a second resistor connected in series; The drain of the power transistor is connected to the voltage input terminal; The gate of the power transistor is connected to the output terminal of the error amplifier; The source of the power transistor is respectively connected to the voltage output terminal and the first end of the first resistor; The second end of the first resistor is connected to the first end of the second resistor; The second end of the second resistor is grounded.

[0010] Preferably, the driving module includes: a ring oscillator, a charge pump, and a level converter; The input terminal of the charge pump is connected to the ring oscillator; The output terminal of the charge pump is connected to the level converter.

[0011] Preferably, the digital low-dropout regulator includes: a comparator, a coarse adjustment logic unit, and a fine adjustment logic unit; The coarse adjustment logic unit includes: a coarse adjustment power transistor array; The fine adjustment logic unit includes: a fine adjustment power transistor array; The comparator is configured to output a voltage fluctuation signal when the load changes; The coarse adjustment logic unit is configured to control the number of turned-on coarse adjustment power transistors in the coarse adjustment power transistor array to match the magnitude of the current load according to the voltage fluctuation signal; The fine adjustment logic unit is configured to control the number of turned-on fine adjustment power transistors in the fine adjustment power transistor array according to the voltage fluctuation signal so that the current output voltage is restored to the initial output voltage before the load change.

[0012] Preferably, the coarse adjustment logic unit further includes: a first-stage adjustment controller, a coarse adjustment pulse generator, and a coarse adjustment control register; The coarse adjustment pulse generator is respectively connected to the first-stage adjustment controller and the coarse adjustment control register; The coarse adjustment control register is connected to the coarse adjustment power transistor array; The first-stage adjustment controller is configured to generate a first-stage adjustment signal according to the voltage fluctuation signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is configured to generate a first coarse adjustment pulse according to the first-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is configured to set the register value to all 0s or all 1s according to the first coarse adjustment pulse; The coarse adjustment power transistor array is configured to turn on the corresponding number of coarse adjustment power transistors according to the register value.

[0013] Preferably, the coarse adjustment logic unit further includes: a coarse adjustment code temporary storage module; The coarse adjustment code temporary storage module is connected to the coarse adjustment control register; The coarse adjustment control register is further configured to generate a first-stage coarse adjustment code according to the state before the register value is set; The coarse adjustment code temporary storage module is configured to temporarily store the first-stage coarse adjustment code.

[0014] Preferably, the coarse adjustment logic unit further includes: a multi-phase comparator array; The multi-phase comparator array is configured to, after the comparator outputs the voltage fluctuation signal, each multi-phase comparator compares the reference voltage and the output voltage, outputs a plurality of voltage comparison results, and outputs a comparison end signal after all multi-phase comparators have completed the comparison.

[0015] Preferably, the coarse adjustment logic unit further includes: a stage conversion module; The stage conversion module is respectively connected to the first-stage adjustment controller and the multi-phase comparator array; The stage conversion module is configured to respectively receive the first-stage adjustment signal and the comparison end signal; The stage conversion module is further configured to determine whether both the first-stage adjustment signal and the comparison end signal are valid. If so, it outputs a stage conversion signal.

[0016] Preferably, the coarse adjustment logic unit further includes: a second-stage adjustment controller; The second-stage adjustment controller is respectively connected to the stage conversion module, the multi-phase comparator array, and the coarse adjustment pulse generator; The second-stage adjustment controller is connected to the coarse adjustment code temporary storage module; The second-stage adjustment controller is configured to respectively receive a plurality of the voltage comparison results and the first-stage coarse adjustment code according to the stage conversion signal, generate a second-stage adjustment signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is further configured to generate a second coarse adjustment pulse according to the second-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is further configured to perform a corresponding callback on the register value according to the second pulse signal; The coarse adjustment power transistor array is further configured to turn on a corresponding number of coarse adjustment power transistors according to the callback register value, so that the number of turned-on coarse adjustment power transistors matches the magnitude of the current load.

[0017] Preferably, the fine adjustment logic unit further includes: a clock frequency adjustment module; The clock frequency adjustment module is respectively connected to the coarse adjustment code buffer module and the multi-phase comparator array; The clock frequency adjustment module is configured to divide a preset clock signal according to the one-stage coarse adjustment code after determining the current load change condition according to multiple voltage comparison results, so as to obtain a fine adjustment clock signal.

[0018] Preferably, the fine adjustment logic unit further includes: a shift register; The shift register is respectively connected to the comparator, the first-stage adjustment controller, the second-stage adjustment controller, and the fine adjustment power transistor array; The first-stage adjustment controller is further configured to generate a fine adjustment lock signal after generating a first-stage adjustment signal to lock the shift register; The second-stage adjustment controller is further configured to generate a fine adjustment unlock signal after generating a second-stage adjustment signal to unlock the shift register; The shift register is configured to perform a shift operation according to the voltage fluctuation signal after being unlocked to obtain a shift register value and generate a fine adjustment signal; The fine adjustment power transistor array is further configured to turn on a corresponding number of fine adjustment power transistors according to the shift register value, so that the current output voltage is restored to the initial output voltage before the load change.

[0019] Preferably, the fine adjustment logic unit further includes: a fine adjustment end module; The fine adjustment end module is respectively connected to the clock frequency adjustment module and the shift register; The fine adjustment end module is configured to record the shift register value in each clock cycle according to the fine adjustment clock signal; The fine adjustment end module is further configured to determine whether the shift register values in two adjacent clock cycles are equal, and if so, output a fine adjustment end signal; The comparator, the first-stage adjustment controller, and the second-stage adjustment controller are all further configured to perform a reset operation according to the fine adjustment end signal.

[0020] The on-chip system with a hybrid architecture provided by the present invention is provided with a main power supply, a digital low-dropout regulator, a charge pump low-dropout regulator, and a circuit module. Among them, the main power supply is connected to the digital low-dropout regulator to provide power for the digital low-dropout regulator. The digital low-dropout regulator is respectively connected to the charge pump low-dropout regulator and the circuit module.

[0021] Compared with the prior art, the digital low-dropout regulator has a faster voltage regulation speed, can greatly improve the power-on speed of the on-chip system, and uses the charge pump regulator to reduce the output ripple of the digital low-dropout regulator, so as to suppress power fluctuations and provide a stable power supply voltage for the analog circuit module in the on-chip system. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of an on-chip system with a hybrid architecture provided by an embodiment of the present invention; Figure 2 It is a schematic structural diagram of a charge pump low-dropout regulator provided by an embodiment of the present invention; Figure 3 It is a schematic structural diagram of a digital low-dropout regulator provided by an embodiment of the present invention. Detailed Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0025] The embodiments of the present invention are written in a progressive manner.

[0026] The embodiments of the present invention provide an on-chip system with a hybrid architecture. It mainly solves the technical problems in the prior art that the digital circuit module will generate relatively large power consumption and has a slow power-on time, the analog circuit module is sensitive to power supply voltage fluctuations, and abnormal working states may occur when integrated with the digital circuit under the same power supply.

[0027] Such as Figure 1As shown in the figure, a system on chip with a hybrid architecture includes: a main power supply, a digital low dropout regulator, a charge pump low dropout regulator, and a circuit module; The main power supply is connected to the digital low dropout regulator; The digital low dropout regulator is respectively connected to the charge pump low dropout regulator and the circuit module.

[0028] In the actual application process, a main power supply, a digital low dropout regulator, a charge pump low dropout regulator, and a circuit module are provided in the system on chip with a hybrid architecture; among them, the main power supply is connected to the digital low dropout regulator to provide power for the digital low dropout regulator; the digital low dropout regulator is respectively connected to the charge pump low dropout regulator and the circuit module; the digital low dropout regulator has an extremely fast adjustment speed and is responsible for accelerating the power-on process of the system on chip during the power-on stage of the system on chip, so that the system on chip can quickly obtain a stable power supply voltage, and the charge pump low dropout regulator will utilize its high power supply rejection performance to improve the power supply stability of the analog circuit module. Based on the above structure, the system on chip will obtain a faster power-on speed on the premise of ensuring the normal operation of each circuit module, and reduce the time required for the system on chip to switch from the low-power state to the normal operation state; It should be noted that the low dropout regulator (LDO), also known as the low-dropout linear regulator and low-dropout voltage regulator, is a type of linear DC voltage regulator, and its purpose is the same as to provide a stable DC voltage power supply. Compared with general linear DC voltage regulators, the low dropout regulator can work under a smaller output-input voltage difference.

[0029] Preferably, the circuit module includes: a digital circuit module and an analog circuit module; The digital low dropout regulator is connected to the digital circuit module; The charge pump low dropout regulator is respectively connected to the analog circuit module and the digital low dropout regulator.

[0030] In the actual application process, a digital circuit module and an analog circuit module are provided in the circuit module, and the charge pump low dropout regulator is respectively connected to the digital low dropout regulator and the analog circuit module.

[0031] In this embodiment, the power supply is connected to the input voltage terminal of the digital LDO, and the output terminal of the digital LDO is connected to the voltage input terminal of the charge pump LDO and the power supply of the digital circuit module, and the overall power-on speed of the system on chip is greatly improved by using the high-speed adjustment characteristic of the digital LDO; the voltage output terminal of the charge pump LDO is connected to the power supply of the analog circuit module, and a higher and more stable power supply voltage is provided for the analog circuit module by using the high power supply rejection performance and smaller output ripple of the charge pump LDO.

[0032] Such as Figure 2As shown, preferably, the charge pump low dropout regulator includes: a driving module, an error amplifier, a reference voltage circuit, a power transistor, and a feedback resistor; The driving module is connected to the error amplifier; The reference voltage circuit is connected to the positive input terminal of the error amplifier; The error amplifier, the power transistor, and the feedback resistor form a closed-loop feedback network.

[0033] Preferably, the feedback resistor includes: a first resistor and a second resistor connected in series; The drain of the power transistor is connected to the voltage input terminal; The gate of the power transistor is connected to the output terminal of the error amplifier; The source of the power transistor is respectively connected to the voltage output terminal and the first end of the first resistor; The second end of the first resistor is connected to the first end of the second resistor; The second end of the second resistor is grounded.

[0034] In the actual application process, the design of the system-on-chip generally adopts advanced semiconductor processes, which generally use lower power supply voltages. Under such conditions, the charge pump LDO has more advantages compared to other structures of analog LDOs. This is because the charge pump LDO uses a charge pump to boost the power supply voltage of the error amplifier, enabling the error amplifier in the charge pump LDO to obtain a higher power supply voltage under lower process voltage conditions, thereby enhancing the gain of the error amplifier and the magnitude of the output voltage. Furthermore, the charge pump LDO has high power supply rejection performance and low output ripple, and finally can provide a higher and more stable power supply voltage for the load circuit module; In this embodiment, a driving module, an error amplifier, a reference voltage circuit, a power transistor, and a feedback resistor are provided in the charge pump LDO low dropout regulator. The error amplifier, the power transistor, and the feedback resistor form a closed-loop feedback network. When the output voltage of the LDO rises, the feedback voltage generated by the feedback network also rises, that is, the input voltage of the negative input terminal of the error amplifier rises. By comparing with the reference voltage circuit at the positive input terminal, the output voltage of the error amplifier is adjusted, so that the current passing through the P-type power transistor decreases, and thus the output voltage of the LDO is reduced, and vice versa. The output voltage of the charge pump LDO is made accurate and stable.

[0035] Preferably, the driving module includes: a ring oscillator, a charge pump, and a level shifter; The input terminal of the charge pump is connected to the ring oscillator; The output terminal of the charge pump is connected to the level shifter.

[0036] In the actual application process, a ring oscillator, a charge pump, and a level shifter are provided in the driving module; the input end of the charge pump is connected to the ring oscillator, and the output end of the charge pump is connected to the level shifter.

[0037] It should be noted that a ring oscillator is a ring circuit composed of an odd number of NOT gates. The output of the circuit is two levels generated by oscillation. An even number of inverters cannot form a ring oscillator. This is because the output situation is the same as the input; A level shifter is an electronic device whose main function is to convert the level of a signal from one logic or voltage level to another logic or voltage level. This converter enables signal compatibility and interconnection between different circuits, allowing devices with different levels to communicate and interact with each other. Level shifters are widely used in fields such as digital circuits, communication interfaces, and sensor interfaces, providing effective solutions for signal transmission between different levels.

[0038] In this embodiment, the driving module is implemented by a ring oscillator, a charge pump, and a level shifter. The high voltage output by the charge pump and the level shifter are used to increase the voltage value of the digital signal, ultimately increasing the gate voltage of the power transistor in the digital LDO.

[0039] As Figure 3 shown, preferably, the digital low-dropout regulator includes: a comparator, a coarse-tuning logic unit, and a fine-tuning logic unit; The coarse-tuning logic unit includes: a coarse-tuning power transistor array; The fine-tuning logic unit includes: a fine-tuning power transistor array; The comparator is used to output a voltage fluctuation signal when the load changes; The coarse-tuning logic unit is used to control the number of turned-on coarse-tuning power transistors in the coarse-tuning power transistor array to match the magnitude of the current load according to the voltage fluctuation signal; The fine-tuning logic unit is used to control the number of turned-on fine-tuning power transistors in the fine-tuning power transistor array according to the voltage fluctuation signal so that the current output voltage is restored to the initial output voltage before the load change.

[0040] In the actual application process, the comparator is respectively connected to the coarse-tuning logic unit and the fine-tuning logic unit. When the load changes, the voltage fluctuation signal is respectively sent to the coarse-tuning logic unit and the fine-tuning logic unit. The coarse-tuning logic unit controls the number of turned-on transistors to match the magnitude of the current load according to the voltage fluctuation signal. After the coarse-tuning is completed, the fine-tuning logic unit controls the number of turned-on transistors according to the voltage fluctuation signal to restore the current output voltage to the initial output voltage before the load change.

[0041] In this embodiment, when the comparator is operating normally, the output voltage (i.e., the initial output voltage) is equal in magnitude to the reference voltage. When the load changes, the output voltage also changes accordingly, deviating from the magnitude of the reference voltage. Correspondingly, the comparator outputs a voltage fluctuation signal: the os or us signal. These two signals represent that the output voltage has fluctuated upward (os) or downward (us).

[0042] Preferably, the coarse adjustment logic unit further includes: a first-stage adjustment controller, a coarse adjustment pulse generator, and a coarse adjustment control register; The coarse adjustment pulse generator is respectively connected to the first-stage adjustment controller and the coarse adjustment control register; The coarse adjustment control register is connected to the coarse adjustment power transistor array; The first-stage adjustment controller is configured to generate a first-stage adjustment signal according to the voltage fluctuation signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is configured to generate a first coarse adjustment pulse according to the first-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is configured to set the register value to all 0s or all 1s according to the first coarse adjustment pulse; The coarse adjustment power transistor array is configured to turn on the corresponding number of coarse adjustment power transistors according to the register value.

[0043] In the actual application process, a first-stage adjustment controller, a coarse adjustment pulse generator, and a coarse adjustment control register are provided in the coarse adjustment logic unit; the coarse adjustment pulse generator is respectively connected to the first-stage adjustment controller and the coarse adjustment control register, and the coarse adjustment control register is connected to the coarse adjustment power transistor array; In this embodiment, when the first-stage adjustment controller receives the voltage fluctuation signal: the os or us signal, it generates a first-stage adjustment signal. The coarse adjustment pulse generator receives the first-stage adjustment signal and generates a first coarse adjustment pulse, and sends it to the coarse adjustment control register; after receiving the first coarse adjustment pulse, the coarse adjustment control register sets its register value to all 0s or all 1s. The coarse adjustment power transistor array turns on the corresponding number of coarse adjustment power transistors according to the register value. Specifically, when the coarse adjustment control register receives the os signal, it sets its register value to all 1s, and all the corresponding coarse adjustment power transistors are turned off; when the coarse adjustment control register receives the us signal, it sets its register value to all 0s, and all the corresponding coarse adjustment power transistors are turned on.

[0044] Preferably, the coarse adjustment logic unit further includes: a coarse adjustment code temporary storage module; The coarse adjustment code temporary storage module is connected to the coarse adjustment control register; The coarse adjustment control register is further configured to generate a first-stage coarse adjustment code according to the state before the register value is set; The coarse - tuning code temporary storage module is used to temporarily store the first - stage coarse - tuning code.

[0045] During the actual operation process, the coarse - tuning logic unit is also provided with a coarse - tuning code temporary storage module; before the coarse - tuning control register sets its register value to all 0s or all 1s, the current register value state is correspondingly generated into a first - stage coarse - tuning code, and the first - stage coarse - tuning code is sent to the coarse - tuning code temporary storage module for temporary storage.

[0046] Preferably, the coarse - tuning logic unit further includes: a multi - phase comparator array; The multi - phase comparator array is used to compare the magnitudes of the reference voltage and the output voltage after the comparator outputs a voltage fluctuation signal, output multiple voltage comparison results, and output a comparison end signal after all the multi - phase comparators have completed the comparison.

[0047] During the actual operation process, a multi - phase comparator array is also provided in the coarse - tuning logic unit. After the comparator generates an os or us signal, the multi - phase comparator array starts to work simultaneously. Each multi - phase comparator compares the magnitudes of the reference voltage and the output voltage and outputs multiple voltage comparison results. When all the multi - phase comparators in the comparator array have completed the comparison, a comparison end signal will be output to the stage conversion module.

[0048] In this embodiment, the structure of the multi - phase comparator array is similar to that of a time - to - digital converter. A delay chain composed of buffers is used to convert the input trigger signal into multiple comparison phases, so as to control the detection time difference between each comparator at the picosecond level, thereby greatly shortening the time required between each comparison and significantly reducing the time required for the entire adjustment process. The specific working process is as follows: 1. A rising edge input is obtained at the trig signal. The rising edge is disassembled into multiple rising edges with different phases through the delay chain; 2. The rising edges with different phases are used as trigger signals and input to the clock terminals of the comparators. The comparators in the figure will be triggered sequentially from left to right and compare the input voltage VFB with VREF. If the difference between the two voltages is greater than the trigger threshold of the comparator, the comparator will output a high level; 3. After each comparator completes the comparison, the comparator will output an n - bit comparison result. The n - bit comparison result is generally composed of consecutive 1s and 0s, such as 11110000. Different combinations of 1s and 0s represent different input voltage change speeds. Thus, the multi - phase comparator array can complete the rapid detection of the input voltage.

[0049] Preferably, the coarse - tuning logic unit further includes: a stage conversion module; The stage conversion module is respectively connected to the first - stage adjustment controller and the multi - phase comparator array; The stage conversion module is used to receive the first - stage adjustment signal and the comparison end signal respectively; The phase conversion module is further configured to determine whether both the first-stage adjustment signal and the comparison end signal are valid. If so, it outputs a phase conversion signal.

[0050] In the actual application process, the phase conversion module is respectively connected to the first-stage adjustment controller and the multi-phase comparator array. After the first-stage adjustment controller generates the first-stage adjustment signal, it also sends a copy of the first-stage adjustment signal to the phase conversion module. The multi-phase comparator array outputs a comparison end signal to the phase conversion module after all its multi-phase comparators complete the comparison. After receiving the above two signals, the phase conversion module determines whether both of the above two signals are valid. If so, it outputs a phase conversion signal.

[0051] Preferably, the coarse adjustment logic unit further includes: a second-stage adjustment controller; The second-stage adjustment controller is respectively connected to the phase conversion module, the multi-phase comparator array, and the coarse adjustment pulse generator; The second-stage adjustment controller is connected to the coarse adjustment code temporary storage module; The second-stage adjustment controller is configured to receive a plurality of voltage comparison results and a first-stage coarse adjustment code respectively according to the phase conversion signal, generate a second-stage adjustment signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is further configured to generate a second coarse adjustment pulse according to the second-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is further configured to perform a corresponding callback on the register value according to the second pulse signal; The coarse adjustment power transistor array is further configured to turn on a corresponding number of coarse adjustment power transistors according to the callback register value, so that the number of turned-on coarse adjustment power transistors matches the magnitude of the current load.

[0052] In the actual application process, the coarse adjustment logic unit is further provided with a second-stage adjustment controller. The second-stage adjustment controller is respectively connected to the phase conversion module, the multi-phase comparator array, and the coarse adjustment pulse generator. The second-stage adjustment controller is also connected to the coarse adjustment code temporary storage module. After the second-stage adjustment controller receives the phase conversion signal, it receives a plurality of voltage comparison results generated by the multi-phase comparator array and a first-stage coarse adjustment code sent by the coarse adjustment code temporary storage module, generates a second-stage adjustment signal and sends it to the coarse adjustment pulse generator. The coarse adjustment pulse generator generates a second coarse adjustment pulse after receiving the second-stage adjustment signal and sends it to the coarse adjustment control register. The coarse adjustment control register performs a corresponding callback on the register value according to the second pulse signal, and the coarse adjustment power transistor array turns on a corresponding number of transistors according to the callback register value, so that the number of turned-on transistors matches the magnitude of the current load.

[0053] In this embodiment, the second-stage adjustment controller first receives multiple output results of the comparator array. The output results of the comparator array will increase or decrease correspondingly as the load current changes. Combining with the coarse adjustment code stored in the coarse adjustment code storage unit, the value of the coarse adjustment control register is correspondingly adjusted back. If the first-stage adjustment controller previously set the value of the coarse adjustment control register to all 0s, the second-stage adjustment controller will increase the value of the coarse adjustment control register from 0 by a certain amount. If the first-stage adjustment controller previously set the value of the coarse adjustment control register to all 1s, the second-stage adjustment controller will decrease the value of the coarse adjustment control register from all 1s by a certain amount. After the above process, the number of turned-on coarse adjustment power transistors will match the current load current magnitude.

[0054] Preferably, the fine adjustment logic unit further includes: a clock frequency adjustment module; The clock frequency adjustment module is respectively connected to the coarse adjustment code storage module and the multi-phase comparator array; The clock frequency adjustment module is used to divide the preset clock signal according to the coarse adjustment code after determining the current load change situation based on multiple voltage comparison results, so as to obtain a fine adjustment clock signal.

[0055] In the actual operation process, a clock frequency adjustment module is set in the fine adjustment logic unit. The clock frequency adjustment module is respectively connected to the coarse adjustment code storage module and the multi-phase comparator array. The clock frequency adjustment module determines the current load change situation according to multiple voltage comparison results, divides the preset clock CLK signal according to the coarse adjustment code sent by the coarse adjustment code storage module to obtain a fine adjustment clock signal, and then provides a suitable operating frequency for the fine adjustment logic unit, so that the entire fine adjustment process will not oscillate, and the output voltage can accurately return to the situation before the load change.

[0056] Preferably, the fine adjustment logic unit further includes: a shift register; The shift register is respectively connected to the comparator, the first-stage adjustment controller, the second-stage adjustment controller, and the fine adjustment power transistor array; The first-stage adjustment controller is further used to generate a fine adjustment lock signal after generating the first-stage adjustment signal to lock the shift register; The second-stage adjustment controller is further used to generate a fine adjustment unlock signal after generating the second-stage adjustment signal to unlock the shift register; The shift register is used to perform a shift operation according to the voltage fluctuation signal after unlocking to obtain a shift register value and generate a fine adjustment signal; The fine adjustment power transistor array is further used to turn on the number of fine adjustment power transistors corresponding to the shift register value, so that the current output voltage is restored to the initial output voltage before the load change.

[0057] During the actual operation process, a shift register is provided in the fine-tuning logic unit; the shift register is respectively connected to a comparator, a first-stage adjustment controller, a second-stage adjustment controller, and a fine-tuning power transistor array. During the operation process, after generating the first-stage adjustment signal, the first-stage adjustment controller generates a fine-tuning lock signal to lock the shift register; after generating the second-stage adjustment signal, the second-stage adjustment controller generates a fine-tuning unlock signal to unlock the shift register; after being unlocked, the shift register performs a shift operation according to the voltage fluctuation signal to obtain the corresponding register value, and generates a fine-tuning signal; the fine-tuning power transistor array turns on the corresponding number of fine-tuning power transistors according to the shift register value, so that the current output voltage is restored to the initial output voltage before the load changes.

[0058] In this embodiment, while controlling the change of the coarse-tuning control register, the first-stage adjustment controller generates a fine-tuning lock signal to lock the 64-bit shift register in the fine-tuning logic, making it unable to perform shift operations; after the second-stage adjustment controller finishes working, it will output a fine-tuning unlock signal to enable the 64-bit shift register in the fine-tuning logic to start working. The function of the 64-bit shift register is to control the number of fine-tuning power transistors turned on in the fine-tuning power transistor array according to the output result of the comparator, so that the output voltage can be accurately restored to the size before the load current changes.

[0059] Preferably, the fine-tuning logic unit further includes: a fine-tuning end module; The fine-tuning end module is respectively connected to the clock frequency adjustment module and the shift register; The fine-tuning end module is used to record the shift register value in each clock cycle according to the fine-tuning clock signal; The fine-tuning end module is further used to judge whether the shift register values in two adjacent clock cycles are equal. If so, it outputs a fine-tuning end signal; The comparator, the first-stage adjustment controller, and the second-stage adjustment controller are also all used to perform a reset operation according to the fine-tuning end signal.

[0060] During the actual operation process, a fine-tuning end module is also provided in the fine-tuning logic unit. The fine-tuning end module is connected to the clock frequency adjustment module and the shift register; the fine-tuning end module records the shift register value once in each clock cycle according to the fine-tuning clock signal; when the fine-tuning end module judges that the shift register values in two adjacent clock cycles are equal, it outputs a fine-tuning end signal to the comparator, the first-stage adjustment controller, and the second-stage adjustment controller, and performs a corresponding reset operation according to the fine-tuning end signal.

[0061] In the embodiments provided in this application, it should be understood that the disclosed system can be implemented in other ways. The system embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0062] In addition, in each embodiment of the present invention, each functional module can be all integrated in a processor, or each module can be separately used as a device alone, or two or more modules can be integrated in a device; each functional module in each embodiment of the present invention can be implemented in the form of hardware, or can be implemented in the form of a combination of hardware and software functional units.

[0063] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by program instructions and related hardware. The foregoing program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, they execute the steps including the above method embodiments; and the foregoing storage media include: various media such as removable storage devices, read-only memory (ROM), magnetic disks, or optical discs that can store program codes.

[0064] It should be understood that in this application, if the terms "system", "device", "unit" and / or "module" are used, they are only a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the term can be replaced by other expressions.

[0065] As shown in this application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. An element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, commodity or device including the element.

[0066] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0067] The above has introduced in detail a system-on-chip with a hybrid architecture provided by the present invention. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system on chip with a hybrid architecture, characterized in that, Including: A main power supply, a digital low dropout regulator, a charge pump low dropout regulator, and a circuit module; The main power supply is connected to the digital low dropout regulator; The digital low dropout regulator is respectively connected to the charge pump low dropout regulator and the circuit module.

2. The system-on-chip with a hybrid architecture according to claim 1, characterized in that The circuit module includes: a digital circuit module and an analog circuit module; The digital low dropout regulator is connected to the digital circuit module; The charge pump low dropout regulator is respectively connected to the analog circuit module and the digital low dropout regulator.

3. The system on chip with a hybrid architecture according to claim 1, wherein The charge pump low dropout regulator includes: a driving module, an error amplifier, a reference voltage circuit, a power transistor, and a feedback resistor; The driving module is connected to the error amplifier; The reference voltage circuit is connected to the positive input terminal of the error amplifier; The error amplifier, the power transistor, and the feedback resistor form a closed-loop feedback network.

4. The system on chip with a hybrid architecture according to claim 3, wherein The feedback resistor includes: a first resistor and a second resistor connected in series; The drain of the power transistor is connected to the voltage input terminal; The gate of the power transistor is connected to the output terminal of the error amplifier; The source of the power transistor is respectively connected to the voltage output terminal and the first end of the first resistor; The second end of the first resistor is connected to the first end of the second resistor; The second end of the second resistor is grounded.

5. The system-on-chip with a hybrid architecture according to claim 3, wherein The driving module includes: a ring oscillator, a charge pump, and a level converter; The input terminal of the charge pump is connected to the ring oscillator; The output terminal of the charge pump is connected to the level converter.

6. The system on chip with a hybrid architecture according to claim 1, wherein, The digital low dropout regulator includes: a comparator, a coarse adjustment logic unit, and a fine adjustment logic unit; The coarse adjustment logic unit includes: a coarse adjustment power transistor array; The fine adjustment logic unit includes: a fine adjustment power transistor array; The comparator is used to output a voltage fluctuation signal when the load changes; The coarse adjustment logic unit is used to control the number of turned-on coarse adjustment power transistors in the coarse adjustment power transistor array to match the magnitude of the current load according to the voltage fluctuation signal; The fine adjustment logic unit is used to control the number of turned-on fine adjustment power transistors in the fine adjustment power transistor array according to the voltage fluctuation signal so that the current output voltage is restored to the initial output voltage before the load change.

7. The system on chip with a hybrid architecture according to claim 6, characterized in that, The coarse adjustment logic unit further includes: a first-stage adjustment controller, a coarse adjustment pulse generator, and a coarse adjustment control register; The coarse adjustment pulse generator is respectively connected to the first-stage adjustment controller and the coarse adjustment control register; The coarse adjustment control register is connected to the coarse adjustment power transistor array; The first-stage adjustment controller is used to generate a first-stage adjustment signal according to the voltage fluctuation signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is used to generate a first coarse adjustment pulse according to the first-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is used to set the register value to all 0s or all 1s according to the first coarse adjustment pulse; The coarse adjustment power transistor array is used to turn on the number of coarse adjustment power transistors corresponding to the register value.

8. The system-on-chip with a hybrid architecture according to claim 7, wherein The coarse adjustment logic unit further includes: a coarse adjustment code temporary storage module; The coarse adjustment code temporary storage module is connected to the coarse adjustment control register; The coarse adjustment control register is further configured to generate a first-stage coarse adjustment code according to the state before the register value is set; The coarse adjustment code temporary storage module is used to temporarily store the first-stage coarse adjustment code.

9. The system on chip with a hybrid architecture according to claim 8, wherein The coarse adjustment logic unit further includes: a multi-phase comparator array; The multi-phase comparator array is configured to, after the comparator outputs the voltage fluctuation signal, each multi-phase comparator compares the magnitudes of the reference voltage and the output voltage, outputs a plurality of voltage comparison results, and outputs a comparison end signal after all multi-phase comparators have completed the comparison.

10. The system-on-chip with a hybrid architecture according to claim 9, wherein, The coarse adjustment logic unit further includes: a stage conversion module; The stage conversion module is respectively connected to the first-stage adjustment controller and the multi-phase comparator array; The stage conversion module is configured to respectively receive the first-stage adjustment signal and the comparison end signal; The stage conversion module is further configured to determine whether both the first-stage adjustment signal and the comparison end signal are valid. If so, it outputs a stage conversion signal.

11. The system on chip with a hybrid architecture according to claim 10, wherein The coarse adjustment logic unit further includes: a second-stage adjustment controller; The second-stage adjustment controller is respectively connected to the stage conversion module, the multi-phase comparator array, and the coarse adjustment pulse generator; The second-stage adjustment controller is connected to the coarse adjustment code temporary storage module; The second-stage adjustment controller is configured to respectively receive a plurality of the voltage comparison results and the first-stage coarse adjustment code according to the stage conversion signal, generate a second-stage adjustment signal and send it to the coarse adjustment pulse generator; The coarse adjustment pulse generator is further configured to generate a second coarse adjustment pulse according to the second-stage adjustment signal and send it to the coarse adjustment control register; The coarse adjustment control register is further configured to perform a corresponding callback on the register value according to the second pulse signal; The coarse adjustment power transistor array is further configured to turn on a number of coarse adjustment power transistors corresponding to the callback register value, so that the number of turned-on coarse adjustment power transistors matches the magnitude of the current load current.

12. The system on chip with a hybrid architecture according to claim 11, wherein The fine adjustment logic unit further includes: a clock frequency adjustment module; The clock frequency adjustment module is respectively connected to the coarse adjustment code temporary storage module and the multi-phase comparator array; The clock frequency adjustment module is configured to determine the current load change situation according to a plurality of the voltage comparison results, and then frequency-divide a preset clock signal according to the first-stage coarse adjustment code to obtain a fine adjustment clock signal.

13. The system-on-chip with a hybrid architecture according to claim 12, characterized in that, The fine adjustment logic unit further includes: a shift register; The shift register is respectively connected to the comparator, the first-stage adjustment controller, the second-stage adjustment controller, and the fine adjustment power transistor array; The first-stage adjustment controller is further configured to generate a fine adjustment lock signal after generating the first-stage adjustment signal to lock the shift register; The second-stage adjustment controller is further configured to generate a fine adjustment unlock signal after generating the second-stage adjustment signal to unlock the shift register; The shift register is configured to, after being unlocked, perform a shift operation according to the voltage fluctuation signal to obtain a shift register value and generate a fine adjustment signal; The fine-tuning power transistor array is also used to turn on the number of fine-tuning power transistors corresponding to the shift register value, so that the current output voltage is restored to the initial output voltage before the load change.

14. The system on chip with a hybrid architecture according to claim 13, wherein The fine-tuning logic unit further includes: a fine-tuning end module; The fine-tuning end module is respectively connected to the clock frequency adjustment module and the shift register; The fine-tuning end module is used to record the shift register value in each clock cycle according to the fine-tuning clock signal; The fine-tuning end module is also used to judge whether the shift register values in two adjacent clock cycles are equal. If so, it outputs a fine-tuning end signal; The comparator, the first-stage adjustment controller and the second-stage adjustment controller are also used to perform a reset operation according to the fine-tuning end signal.

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