Control system, method and device of CLLC circuit

Abstract

The invention discloses a control system, method and device of a CLLC circuit, and belongs to the technical field of circuits. The method comprises the following steps: acquiring a first detection value of a primary side current of a resonant cavity and a second detection value corresponding to a secondary side current; and comparing the first detection value with a reference value to obtain a first signal, and comparing the second detection value with the reference value to obtain a second signal. And generating a first initial driving signal and a second initial driving signal, obtaining a first driving signal according to the first signal and the first initial driving signal, and obtaining a second driving signal according to the second signal and the second initial driving signal. And controlling a switching device in the CLLC circuit based on the first driving signal and the second driving signal. Synchronous rectification of the CLLC circuit can be realized.

Description

Technical Field

[0001] This application relates to the field of circuit technologies, and particularly to a control system, method, and device for a CLLC circuit. Background Art

[0002] OBC (On-Board Charger) usually adopts a CLLC (Current-in, Voltage-out, resonant converter) circuit. The CLLC circuit includes a primary bridge circuit, a secondary bridge circuit, and a resonant cavity. The input end of the primary bridge circuit is connected to a charging pile, and the output end of the secondary bridge circuit is connected to a battery. The voltage of the charging pile is rectified to charge the battery. Currently, diodes are mostly used for passive rectification in the CLLC circuit. However, at high voltages, the power consumption of the diodes is too high. Therefore, synchronous rectification needs to be sampled in the CLLC on a high-voltage platform. Then, how to control the switching devices in the bridge circuit of the CLLC circuit is an urgent problem to be solved. Summary of the Invention

[0003] Embodiments of this application provide a control system, method, and device for a CLLC circuit, which can realize the control of switching devices in the CLLC circuit. The technical solutions are as follows:

[0004] In a first aspect, a control system for a CLLC circuit is provided, characterized in that the CLLC circuit includes a primary bridge circuit, a secondary bridge circuit, and a resonant cavity, and the control system includes a processor, a first current sampling device, a second current sampling device, a comparison circuit, a first tri-state gate, a second tri-state gate, and a selection circuit, where:

[0005] The first current sampling device is configured to collect a first current on the primary side of the resonant cavity and output a first detection value corresponding to the first current. The second current sampling device is configured to collect a second current on the secondary side of the resonant cavity and output a second detection value corresponding to the second current;

[0006] The comparison circuit is configured to compare the first detection value with a reference value to obtain a first signal and input the first signal to the control end of the first tri-state gate; compare the second detection value with the reference value to obtain a second signal and input the second signal to the control end of the second tri-state gate;

[0007] The processor is configured to generate a first initial driving signal and a second initial driving signal, input the first initial driving signal to the data end of the first tri-state gate and the selection circuit, and input the second initial driving signal to the data end of the second tri-state gate and the selection circuit;

[0008] The first tri-state gate is configured to obtain a first driving signal according to the first signal and the first initial driving signal, and input the first driving signal to the selection circuit;

[0009] The second tri-state gate is configured to obtain a second driving signal according to the second signal and the second initial driving signal, and input the second driving signal to the selection circuit;

[0010] The selection circuit is configured to, when the CLLC circuit is charging forward, use the first initial driving signal as the driving signal of the switching device in the primary side bridge circuit, and use the second driving signal as the driving signal of the switching device in the secondary side bridge circuit; when the CLLC circuit is discharging reversely, use the first driving signal as the driving signal of the switching device in the primary side bridge circuit, and use the second initial driving signal as the driving signal of the switching device in the secondary side bridge circuit.

[0011] In a possible implementation, the comparison circuit includes a first comparator and a second comparator, where:

[0012] The first comparator is configured to compare the first detected value with a reference value to obtain a first signal, and input the first signal to the control terminal of the first tri-state gate;

[0013] The second comparator is configured to compare the second detected value with a reference value to obtain a second signal, and input the second signal to the control terminal of the second tri-state gate.

[0014] In a possible implementation, the selection circuit includes a first data selector and a second data selector, where:

[0015] The first data selector is configured to, when the CLLC circuit is charging forward, use the first initial driving signal as the driving signal of the switching device in the primary side bridge circuit, and when the CLLC circuit is discharging reversely, use the first driving signal as the driving signal of the switching device in the primary side bridge circuit;

[0016] The second data selector is configured to, when the CLLC circuit is charging forward, use the second driving signal as the driving signal of the switching device in the secondary side bridge circuit, and when the CLLC circuit is discharging reversely, use the second initial driving signal as the driving signal of the switching device in the secondary side bridge circuit.

[0017] In a possible implementation, the first current sampling device is a Hall current sensor.

[0018] In a possible implementation, the second current sampling device is a Hall current sensor.

[0019] In a second aspect, an OBC is provided, and the OBC includes the control system and the CLLC circuit as described in the first aspect above.

[0020] In a third aspect, a vehicle is provided, and the vehicle includes the OBC and the battery as described in the first aspect above.

[0021] In a fourth aspect, a control method for a CLLC circuit is provided. The CLLC circuit includes a primary side bridge circuit, a secondary side bridge circuit, and a resonant cavity. The method is applied to a processor and includes:

[0022] Obtaining a first detection value corresponding to a first current on the primary side of the resonant cavity and a second detection value corresponding to a second current on the secondary side of the resonant cavity;

[0023] Comparing the first detection value with a reference value to obtain a first signal, and comparing the second detection value with the reference value to obtain a second signal;

[0024] Generating a first initial driving signal and a second initial driving signal, obtaining a first driving signal according to the first signal and the first initial driving signal, and obtaining a second driving signal according to the second signal and the second initial driving signal;

[0025] When the CLLC circuit is charging forward, using the first initial driving signal as the driving signal for the switching device in the primary side bridge circuit and using the second driving signal as the driving signal for the switching device in the secondary side bridge circuit; when the CLLC circuit is discharging backward, using the first driving signal as the driving signal for the switching device in the primary side bridge circuit and using the second initial driving signal as the driving signal for the switching device in the secondary side bridge circuit.

[0026] In a possible implementation, the obtaining the first driving signal according to the first signal and the first initial driving signal includes:

[0027] If the first signal is 0, the first driving signal is 0; if the first signal is 1, using the first initial driving signal as the first driving signal;

[0028] The obtaining the second driving signal according to the second signal and the second initial driving signal includes:

[0029] If the second signal is 0, the second driving signal is 0; if the second signal is 1, using the second initial driving signal as the second driving signal.

[0030] In a fifth aspect, a control device for a CLLC circuit is provided. The CLLC circuit includes a primary side bridge circuit, a secondary side bridge circuit, and a resonant cavity. The device includes:

[0031] An acquisition module, configured to acquire a first detection value corresponding to a first current on the primary side of the resonant cavity and a second detection value corresponding to a second current on the secondary side of the resonant cavity;

[0032] A driving module, configured to compare the first detection value with a reference value to obtain a first signal, compare the second detection value with the reference value to obtain a second signal; generate a first initial driving signal and a second initial driving signal, and obtain a first driving signal according to the first signal and the first initial driving signal, and obtain a second driving signal according to the second signal and the second initial driving signal; in the case of forward charging of the CLLC circuit, use the first initial driving signal as the driving signal for the switching device in the primary side bridge circuit, and use the second driving signal as the driving signal for the switching device in the secondary side bridge circuit; in the case of reverse discharging of the CLLC circuit, use the first driving signal as the driving signal for the switching device in the primary side bridge circuit, and use the second initial driving signal as the driving signal for the switching device in the secondary side bridge circuit.

[0033] In a possible implementation, the driving module is configured to:

[0034] If the first signal is 0, the first driving signal is 0; if the first signal is 1, use the first initial driving signal as the first driving signal;

[0035] If the second signal is 0, the second driving signal is 0; if the second signal is 1, use the second initial driving signal as the second driving signal.

[0036] In a sixth aspect, a processor is provided. The processor includes a processing circuit and a storage circuit. At least one instruction is stored in the storage circuit, and the instruction is loaded and executed by the processing circuit to implement the operations performed by the control method of the CLLC circuit as described in the fourth aspect above.

[0037] In a seventh aspect, a computer-readable storage medium is provided. At least one instruction is stored in the storage medium, and the instruction is loaded and executed by a processor to implement the operations performed by the control method of the CLLC circuit as described in the fourth aspect.

[0038] In an eighth aspect, a computer program product is provided. At least one instruction is included in the computer program product, and the instruction is loaded and executed by a processor to implement the operations performed by the control method of the CLLC circuit as described in the fourth aspect above.

[0039] The beneficial effects brought by the technical solution provided by this application are as follows:

[0040] In the technical solution provided by this application, a switching device is used instead of a diode in the CLLC circuit, and a drive signal is generated by a processor to drive the on / off of the switching device in the CLLC circuit, thereby realizing synchronous rectification of the CLLC circuit. Brief Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 It is a schematic structural diagram of a control system for a CLLC circuit provided by an embodiment of this application;

[0043] Figure 2 It is a schematic structural diagram of a control system for a CLLC circuit provided by an embodiment of this application;

[0044] Figure 3 It is a schematic structural diagram of a control system for a CLLC circuit provided by an embodiment of this application;

[0045] Figure 4 It is a schematic structural diagram of a control system for a CLLC circuit provided by an embodiment of this application;

[0046] Figure 5 It is a flowchart of a control method for a CLLC circuit provided by an embodiment of this application. Detailed Embodiments

[0047] For the convenience of understanding the embodiments of this application, some terms related to the embodiments of this application will be explained below.

[0048] I. Passive Rectification

[0049] Passive rectification is a traditional rectification method that uses passive devices such as diodes to achieve the rectification function. In a CLLC circuit, passive rectification is usually in the output rectification stage, where the AC voltage of the secondary winding of the transformer is converted into a DC voltage through a diode rectifier bridge.

[0050] Working principle: When the voltage of the secondary winding of the transformer is positive, the diode conducts and the current flows to the load; when the winding voltage is negative, the diode is cut off to prevent reverse current flow. In this way, the AC voltage is converted into a DC voltage.

[0051] Passive rectification does not require an additional control circuit, has a simple circuit structure, high reliability, and low cost. However, the diode has a forward voltage drop, resulting in relatively large conduction losses. Especially in low-voltage and high-current applications, the efficiency loss is obvious. In addition, the conduction and cut-off of the diode are determined by the voltage polarity, and the rectification process cannot be optimized through control strategies. It is not applicable in CLLC with a high-voltage platform, such as an 800V platform.

[0052] II. Synchronous rectification

[0053] Synchronous rectification is an active rectification method that realizes the rectification function by using switching devices, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), instead of traditional diodes. In the CLLC circuit, the specific implementation of synchronous rectification is usually in the output rectification stage, where the conduction and cut-off of the switching device are controlled by a drive signal to achieve rectification.

[0054] Working principle: When the voltage of the secondary winding of the transformer is positive, the control switching device is turned on, and the current flows through the MOSFET to the load; when the winding voltage is negative, the control switching device is turned off to prevent the reverse current from flowing. In this way, the AC voltage is converted into a DC voltage.

[0055] The on-resistance of the switching device is relatively low. Compared with the forward voltage drop of the diode, the conduction loss is smaller. Especially in low-voltage and high-current applications, the efficiency advantage is obvious. The on and off of the switching device can be accurately controlled through drive signals, such as PWM (Pulse Width Modulation) signals, to achieve more flexible control strategies, such as frequency modulation, phase control, etc. It is applicable in CLLC with a high-voltage platform, such as an 800V platform.

[0056] III. Hall current sensor

[0057] The Hall current sensor is based on the magnetic balance Hall principle. According to the Hall effect principle, a current is passed through the control current terminal of the Hall element, and a magnetic field is applied in the normal direction of the plane of the Hall element. Then, a potential difference, called the Hall potential difference, will be generated in the direction perpendicular to the current and the magnetic field, which is used as the detected value corresponding to the current, and its magnitude is proportional to the control current.

[0058] The embodiment of the present application provides a control system for a CLLC circuit capable of realizing synchronous rectification, such as Figure 1As shown, the CLLC circuit includes a primary bridge circuit, a secondary bridge circuit, and a resonant cavity. The primary bridge circuit includes four switching devices, namely Q1, Q2, Q3, and Q4, and the secondary bridge circuit includes four switching devices, namely Q5, Q6, Q7, and Q8.

[0059] The control system includes a processor 10, a first current sampling device 11, a second current sampling device 12, a comparison circuit 13, a first tri-state gate 14, a second tri-state gate 15, and a selection circuit 16, where:

[0060] The first current sampling device 11 is used to collect the first current on the primary side of the resonant cavity and output a first detection value corresponding to the first current. The second current sampling device 12 is used to collect the second current on the secondary side of the resonant cavity and output a second detection value corresponding to the second current. The comparison circuit 13 is used to compare the first detection value with a reference value to obtain a first signal and input the first signal to the control terminal of the first tri-state gate 14. The comparison circuit 13 is also used to compare the second detection value with the reference value to obtain a second signal and input the second signal to the control terminal of the second tri-state gate 15. The first signal and the second signal are described as follows:

[0061] When the first detection value is greater than the reference value, the first signal is at a high level, that is, 1. When the first detection value is less than the reference value, the first signal is at a low level, that is, 0. Among them, the reference value can be a value close to 0 volts, such as 0.1 volts, or it can be 0 volts.

[0062] When the second detection value is greater than the reference value, the second signal is at a high level, that is, 1. When the second detection value is less than the reference value, the second signal is at a low level, that is, 0. Among them, the reference value can be a value close to 0 volts, such as 0.1 volts, or it can be 0 volts.

[0063] The processor 10 is used to generate a first initial drive signal and a second initial drive signal, input the first initial drive signal to the data terminal of the first tri-state gate 14 and the selection circuit 16, and input the second initial drive signal to the data terminal of the second tri-state gate 15 and the selection circuit 16. The generation methods of the first initial drive signal and the second initial drive signal are described as follows. The first initial drive signal and the second initial drive signal are the same. Taking the generation of the first initial drive signal as an example:

[0064] The first initial drive signal is generated using a double closed-loop control strategy. The double closed-loop includes a voltage outer loop and a current inner loop.

[0065] In the case of forward charging of the CLLC circuit, the given value of the voltage outer loop is the charging voltage limit, and the feedback quantity is the real-time output voltage of the secondary bridge circuit (i.e., the real-time charging voltage of the battery). The error of the voltage outer loop (the difference between the given value and the feedback quantity) is input into a PI (Proportional-Integral) controller. The output of the PI controller serves as the given value of the current inner loop. The feedback quantity of the current inner loop is the real-time output current of the secondary bridge circuit (i.e., the real-time charging current of the battery). The error of the current inner loop (the difference between the given value and the feedback quantity) is input into a PI controller. The PI controller outputs a modulation wave, and the modulation wave is input into a comparator together with the built-in carrier of the processor 10 for comparison, and a first initial drive signal is output.

[0066] In the case of reverse discharging of the CLLC circuit, taking the CLLC circuit applied to an 800V high-voltage platform as an example, the given value of the voltage outer loop is 800V, and the feedback quantity is the PFC bus voltage. The error of the voltage outer loop (the difference between the given value and the feedback quantity) is input into a PI controller. The output of the PI controller serves as the given value of the current inner loop. The feedback quantity of the current inner loop is the real-time discharging current of the battery. The error of the current inner loop (the difference between the given value and the feedback quantity) is input into a PI controller. The PI controller outputs a modulation wave, and the modulation wave is input into a comparator together with the built-in carrier of the processor 10 for comparison, and a first initial drive signal is output.

[0067] Among them, the first initial drive signal includes four initial drive signals, denoted as initial drive signal 1, initial drive signal 2, initial drive signal 3, and initial drive signal 4, corresponding to Q1, Q2, Q3, and Q4 in the primary bridge circuit respectively. The second initial drive signal includes four initial drive signals, denoted as initial drive signal 5, initial drive signal 6, initial drive signal 7, and initial drive signal 8, corresponding to Q5, Q6, Q7, and Q8 in the secondary bridge circuit respectively.

[0068] The first tri-state gate 14 is used to obtain a first drive signal according to the first signal and the first initial drive signal, and input the first drive signal to the selection circuit 16.

[0069] When the first signal is at a low level (0), the first drive signal is at a low level (0). When the first signal is at a high level (1), the first drive signal is the first initial drive signal.

[0070] The first drive signal is also four signals, also four drive signals, denoted as drive signal 1, drive signal 2, drive signal 3, and drive signal 4, corresponding to Q1, Q2, Q3, and Q4 in the primary bridge circuit respectively.

[0071] The second tri-state gate 15 is used to obtain a second drive signal according to the second signal and the second initial drive signal, and input the second drive signal to the selection circuit 16.

[0072] When the second signal is at a low level, the second driving signal is at a low level. When the second signal is at a high level, the second driving signal is the second initial driving signal.

[0073] The second driving signal is also a four-way signal and a four-way driving signal, denoted as driving signal 5, driving signal 6, driving signal 7, and driving signal 8, corresponding to Q5, Q6, Q7, and Q8 in the secondary side bridge circuit respectively.

[0074] The selection circuit 16 is used to, when the CLLC circuit is charging forward, use the first initial driving signal as the driving signal of the switching device in the primary side bridge circuit and use the second driving signal as the driving signal of the switching device in the secondary side bridge circuit. When the CLLC circuit is discharging reversely, use the first driving signal as the driving signal of the switching device in the primary side bridge circuit and use the second initial driving signal as the driving signal of the switching device in the secondary side bridge circuit.

[0075] The above-mentioned driving signal 1, driving signal 2, driving signal 3, and driving signal 4 are respectively input to the control terminals of Q1, Q2, Q3, and Q4 in the primary side bridge circuit.

[0076] The above-mentioned driving signal 5, driving signal 6, driving signal 7, and driving signal 8 are respectively input to the control terminals of Q5, Q6, Q7, and Q8 in the primary side bridge circuit.

[0077] In a possible implementation, as Figure 2 shown, the comparison circuit 13 includes a first comparator 131 and a second comparator 132, where:

[0078] The first comparator 131 is used to compare the first detected value with a reference value to obtain a first signal and input the first signal to the control terminal of the first tri-state gate 14. The second comparator 132 is used to compare the second detected value with the reference value to obtain a second signal and input the second signal to the control terminal of the second tri-state gate 15.

[0079] In a possible implementation, as Figure 3 shown, the selection circuit 16 includes a first data selector 161 and a second data selector 162, where:

[0080] The first data selector 161 is used to take the first initial drive signal as the drive signal for the switching device in the primary side bridge circuit when the CLLC circuit is charging forward, and take the first drive signal as the drive signal for the switching device in the primary side bridge circuit when the CLLC circuit is discharging backward. The second data selector 162 is used to take the second drive signal as the drive signal for the switching device in the secondary side bridge circuit when the CLLC circuit is charging forward, and take the second initial drive signal as the drive signal for the switching device in the secondary side bridge circuit when the CLLC circuit is discharging backward.

[0081] The processor 10 inputs a first selection signal to the first data selector 161 and a second selection signal to the second data selector 162. Among them, when the CLLC circuit is charging forward, the first selection signal is at a low level and the second selection signal is at a high level; when the CLLC circuit is discharging backward, the first selection signal is at a high level and the second selection signal is at a low level.

[0082] Correspondingly, the first data selector 161 is used to take the first initial drive signal as the drive signal for the switching device in the primary side bridge circuit when the received first selection signal is at a low level, and take the first drive signal as the drive signal for the switching device in the primary side bridge circuit when the received first selection signal is at a high level. The second data selector 162 is used to take the second drive signal as the drive signal for the switching device in the secondary side bridge circuit when the received second selection signal is at a low level, and take the second initial drive signal as the drive signal for the switching device in the secondary side bridge circuit when the received second selection signal is at a high level.

[0083] In another possible implementation, as Figure 4 shown, the control system further includes an inverter 17. The processor 10 inputs the first selection signal to the inputs of the first data selector 161 and the inverter 17 respectively. The inverter 17 inverts the first selection signal to obtain the second selection signal and inputs it to the second data selector 162. Among them, when the CLLC circuit is charging forward, the first selection signal is at a low level and the second selection signal is at a high level; when the CLLC circuit is discharging backward, the first selection signal is at a high level and the second selection signal is at a low level.

[0084] In one possible implementation, the first current sampling device 11 is a Hall current sensor. Correspondingly, the detected value of the current is the Hall electromotive force.

[0085] In one possible implementation, the second current sampling device 12 is a Hall current sensor. Correspondingly, the detected value of the current is the Hall electromotive force.

[0086] In a possible implementation, the processor 10 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor 10 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 10 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 10 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some examples, the processor 10 may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0087] The embodiment of the present application also provides a control method for a CLLC circuit. This method can be implemented by a processor, as Figure 5 shown. The method may include the following steps:

[0088] Step 101: Obtain a first detection value corresponding to a first current on the primary side of the resonant cavity and a second detection value corresponding to a second current on the secondary side of the resonant cavity.

[0089] Step 102: Compare the first detection value with a reference value to obtain a first signal, and compare the second detection value with the reference value to obtain a second signal.

[0090] Step 103: Generate a first initial drive signal and a second initial drive signal. According to the first signal and the first initial drive signal, obtain a first drive signal. According to the second signal and the second initial drive signal, obtain a second drive signal.

[0091] Step 104: In the case of forward charging of the CLLC circuit, use the first initial drive signal as the drive signal for the switching device in the primary side bridge circuit, and use the second drive signal as the drive signal for the switching device in the secondary side bridge circuit. In the case of reverse discharging of the CLLC circuit, use the first drive signal as the drive signal for the switching device in the primary side bridge circuit, and use the second initial drive signal as the drive signal for the switching device in the secondary side bridge circuit.

[0092] In this control method, a processor is used to implement the functions of all the devices in the above control system except the current sampling device.

[0093] In the description of the embodiments of the application, the descriptions referring to the terms "certain embodiments", "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0094] It can be understood that "a plurality of" in the present application means two or more, and other quantifiers are similar thereto. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The singular forms of "a", "the", and "said" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0095] Furthermore, it can be understood that the terms "first", "second", etc. are used to describe various information, but this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other, and do not represent a specific order or degree of importance. In fact, the expressions such as "first" and "second" can be used interchangeably. For example, without departing from the scope of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information.

[0096] Furthermore, it can be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "front", "rear", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this embodiment and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation.

[0097] It can be further understood that, unless otherwise clearly specified and defined, terms such as "installation", "connection", "linkage", "fixation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral molding; it can be a mechanical connection, an electrical connection or a connection that allows mutual communication; it can be a direct connection without other components between two elements, or an indirect connection through an intermediate medium, and it can be the internal communication between two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0098] It can be further understood that although the operations are described in a specific order in the drawings in the embodiments of the present application, it should not be understood as requiring these operations to be performed in the specific order shown or in a serial order, or requiring all the operations shown to obtain the desired result. In a specific environment, multitasking and parallel processing may be advantageous.

[0099] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the solutions disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the scope of the claims.

[0100] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

[0101] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals (including but not limited to signals transmitted between user terminals and other devices) involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the current signals, DC component signals, AC component signals, etc. involved in the present application are all obtained under full authorization.

[0102] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A control system for a CLLC circuit, characterized in that, The CLLC circuit includes a primary side bridge circuit, a secondary side bridge circuit, and a resonant cavity. The control system includes a processor (10), a first current sampling device (11), a second current sampling device (12), a comparison circuit (13), a first tri-state gate (14), a second tri-state gate (15), and a selection circuit (16), where: The first current sampling device (11) is configured to collect a first current on the primary side of the resonant cavity and output a first detection value corresponding to the first current. The second current sampling device (12) is configured to collect a second current on the secondary side of the resonant cavity and output a second detection value corresponding to the second current. The comparison circuit (13) is configured to compare the first detection value with a reference value to obtain a first signal and input the first signal to the control terminal of the first tri-state gate (14); compare the second detection value with the reference value to obtain a second signal and input the second signal to the control terminal of the second tri-state gate (15). The processor (10) is configured to generate a first initial drive signal and a second initial drive signal, input the first initial drive signal to the data terminal of the first tri-state gate (14) and the selection circuit (16), and input the second initial drive signal to the data terminal of the second tri-state gate (15) and the selection circuit (16). The first tri-state gate (14) is configured to obtain a first drive signal based on the first signal and the first initial drive signal and input the first drive signal to the selection circuit (16). The second tri-state gate (15) is configured to obtain a second drive signal based on the second signal and the second initial drive signal and input the second drive signal to the selection circuit (16). The selection circuit (16) is configured to use the first initial drive signal as the drive signal for the switching device in the primary side bridge circuit and use the second drive signal as the drive signal for the switching device in the secondary side bridge circuit when the CLLC circuit is charging forward; use the first drive signal as the drive signal for the switching device in the primary side bridge circuit and use the second initial drive signal as the drive signal for the switching device in the secondary side bridge circuit when the CLLC circuit is discharging backward.

2. The control system according to claim 1, wherein The comparison circuit (13) includes a first comparator (131) and a second comparator (132), where: The first comparator (131) is configured to compare the first detection value with the reference value to obtain a first signal and input the first signal to the control terminal of the first tri-state gate (14). The second comparator (132) is configured to compare the second detection value with the reference value to obtain a second signal and input the second signal to the control terminal of the second tri-state gate (15).

3. The control system according to claim 1, characterized in that, The selection circuit (16) includes a first data selector (161) and a second data selector (162), where: The first data selector (161) is configured to use the first initial drive signal as the drive signal for the switching device in the primary bridge circuit when the CLLC circuit is charging forward, and use the first drive signal as the drive signal for the switching device in the primary bridge circuit when the CLLC circuit is discharging reversely; The second data selector (162) is configured to use the second drive signal as the drive signal for the switching device in the secondary bridge circuit when the CLLC circuit is charging forward, and use the second initial drive signal as the drive signal for the switching device in the secondary bridge circuit when the CLLC circuit is discharging reversely.

4. The control system according to claim 1, wherein The first current sampling device (11) is a Hall current sensor.

5. The control system according to claim 1, characterized in that, The second current sampling device (12) is a Hall current sensor.

6. An OBC, characterized in that, The OBC includes the control system and the CLLC circuit according to any one of claims 1-5.

7. A vehicle, characterized in that, The vehicle includes the OBC according to claim 6 and a battery.

8. A control method for a CLLC circuit, characterized in that, The CLLC circuit includes a primary bridge circuit, a secondary bridge circuit and a resonant cavity. The method is applied to a processor, and the method includes: Obtaining a first detection value corresponding to a first current on the primary side of the resonant cavity and a second detection value corresponding to a second current on the secondary side of the resonant cavity; Comparing the first detection value with a reference value to obtain a first signal, and comparing the second detection value with the reference value to obtain a second signal; Generating a first initial drive signal and a second initial drive signal, obtaining a first drive signal according to the first signal and the first initial drive signal, and obtaining a second drive signal according to the second signal and the second initial drive signal; When the CLLC circuit is charging forward, using the first initial drive signal as the drive signal for the switching device in the primary bridge circuit and using the second drive signal as the drive signal for the switching device in the secondary bridge circuit; when the CLLC circuit is discharging reversely, using the first drive signal as the drive signal for the switching device in the primary bridge circuit and using the second initial drive signal as the drive signal for the switching device in the secondary bridge circuit.

9. The method according to claim 8, characterized in that The obtaining the first drive signal according to the first signal and the first initial drive signal includes: If the first signal is 0, the first drive signal is 0; if the first signal is 1, using the first initial drive signal as the first drive signal; The obtaining the second drive signal according to the second signal and the second initial drive signal includes: If the second signal is 0, the second drive signal is 0; if the second signal is 1, using the second initial drive signal as the second drive signal.

10. A control device for a CLLC circuit, characterized in that, The CLLC circuit includes a primary bridge circuit, a secondary bridge circuit and a resonant cavity. The device includes: An obtaining module, configured to obtain a first detection value corresponding to a first current on the primary side of the resonant cavity and a second detection value corresponding to a second current on the secondary side of the resonant cavity; A driving module, configured to compare the first detection value with a reference value to obtain a first signal, and compare the second detection value with the reference value to obtain a second signal; generate a first initial driving signal and a second initial driving signal, and obtain a first driving signal according to the first signal and the first initial driving signal, and obtain a second driving signal according to the second signal and the second initial driving signal; in the case of forward charging of the CLLC circuit, use the first initial driving signal as the driving signal for the switching device in the primary side bridge circuit, and use the second driving signal as the driving signal for the switching device in the secondary side bridge circuit; in the case of reverse discharging of the CLLC circuit, use the first driving signal as the driving signal for the switching device in the primary side bridge circuit, and use the second initial driving signal as the driving signal for the switching device in the secondary side bridge circuit.

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