Frequency multiplier, chip, and electronic device

Abstract

The embodiment of the invention provides a frequency multiplier, a chip and electronic equipment, and the frequency multiplier part comprises a frequency dividing circuit which is used for adjusting the duty ratio of an input signal and generating a frequency dividing signal of the input signal, and the frequency dividing signal has a 50% duty ratio; the injection locking oscillator is used for generating a plurality of phase shift signals of the frequency division signal, and preset phase differences are sequentially formed among the plurality of phase shift signals; and the logic circuit is used for combining the plurality of phase shift signals to output a frequency multiplication signal of the input signal. The frequency multiplier provided by the invention does not depend on the duty ratio of the input signal, and the output signal is high in precision and less in stray.

Description

Technical Field

[0001] This application relates to the technical field of frequency multipliers, and particularly to a frequency multiplier, a chip, and an electronic device. Background Art

[0002] With the development of modern communication technologies, a large number of frequency signals are required in both digital and analog circuits, usually various required frequencies obtained by frequency division or multiplication based on a reference signal. A frequency multiplier multiplies an input signal Fin by a multiple N to obtain an output signal FOUT, whose frequency is equal to N*Fin. Traditional frequency multiplication can be generated by a Phase-Locked Loop (PLL), but the circuit structure of the PLL is complex, with high power consumption and large area. Among them, the frequency doubler with N = 2 is the most widely used. For example, if the PLL hopes to have a high-frequency signal as the reference frequency, it can improve the bandwidth of the PLL while reducing the quantization noise in the frequency divider and the noise brought by the phase detector and charge pump. At this time, the frequency of the reference crystal oscillator can be doubled and then used as the reference frequency of the PLL. Another example is that in a transceiver, to reduce problems such as injection pulling and at the same time reduce the power consumption of the local oscillator, a lower local oscillator frequency can be selected and then doubled and provided to the mixer for use. The traditional frequency doubler is implemented by a delay module and an exclusive-OR gate, but this structure requires the duty cycle of the input signal to be exactly 50%, otherwise the generated output 2-fold frequency error is large and there are many spurs. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a frequency multiplier, a chip, and an electronic device to solve the above technical problems.

[0004] In a first aspect, an embodiment of this application provides a frequency multiplier, including: a frequency division circuit for adjusting the duty cycle of an input signal and generating a frequency division signal of the input signal, the frequency division signal having a 50% duty cycle; an injection-locked oscillator for generating a plurality of phase-shifted signals of the frequency division signal, with a predetermined phase difference between the plurality of phase-shifted signals in sequence; and a logic circuit for combining the plurality of phase-shifted signals to output a frequency-doubled signal of the input signal.

[0005] In some embodiments, the frequency division circuit includes: a flip-flop configured to flip its state whenever a falling edge or a rising edge of the input signal arrives, to obtain a frequency division signal with a 50% duty cycle.

[0006] In some embodiments, the flip-flop includes: a D flip-flop, where the inverted output terminal of the D flip-flop is connected to the data input terminal, the clock input terminal of the D flip-flop receives the input signal, and the output terminal of the D flip-flop outputs the frequency division signal; or a JK flip-flop, where the J terminal and the K terminal of the JK flip-flop are both connected to a high level, the clock input terminal of the JK flip-flop receives the input signal, and the Q terminal of the JK flip-flop outputs the frequency division signal.

[0007] In some embodiments, the logic circuit includes: a plurality of exclusive-OR units, each exclusive-OR unit configured to perform an exclusive-OR operation on a set of the phase-shifted signals, where each set of phase-shifted signals includes two phase-shifted signals having the predetermined phase difference; and an OR unit configured to perform an OR operation on the outputs of the plurality of exclusive-OR units to output a frequency-doubled signal.

[0008] In some embodiments, the plurality of exclusive-OR units includes: a first exclusive-OR unit configured to perform an exclusive-OR operation on a first phase-shifted signal and a second phase-shifted signal to output a first intermediate signal; and a second exclusive-OR unit configured to perform an exclusive-OR operation on a third phase-shifted signal and a fourth phase-shifted signal to output a second intermediate signal; wherein the phase differences between the first phase-shifted signal, the second phase-shifted signal, the third phase-shifted signal, and the fourth phase-shifted signal are 45° in sequence.

[0009] In some embodiments, the injection-locked oscillator includes a plurality of phase stages connected in a loop, where adjacent two phase stages in the plurality of phase stages generate the predetermined phase difference, and the frequency-divided signal is injected into the loop. The free oscillation frequency of the oscillator is set near the injection frequency (i.e., FIN / 2) to ensure that the oscillator can resonate with the injection frequency and finally synchronize with the FIN / 2 signal.

[0010] In some embodiments, the plurality of phase stages includes: a first differential amplifier, whose input terminal receives the frequency-divided signal; a second differential amplifier, whose positive input terminal is connected to the positive output terminal of the first differential amplifier, and whose negative input terminal is connected to the negative output terminal of the first differential amplifier; a third differential amplifier, whose positive input terminal is connected to the positive output terminal of the second differential amplifier, and whose negative input terminal is connected to the negative output terminal of the second differential amplifier; a fourth differential amplifier, whose positive input terminal is connected to the negative output terminal of the third differential amplifier, and whose negative input terminal is connected to the positive output terminal of the third differential amplifier, and whose positive output terminal is connected to the positive input terminal of the first differential amplifier, and whose negative output terminal is connected to the negative input terminal of the first differential amplifier.

[0011] In some embodiments, the injection-locked oscillator further includes a buffer connected between the frequency-dividing circuit and the first differential amplifier for maintaining the edge shape of the frequency-divided signal.

[0012] In some embodiments, the frequency doubler is a two-frequency doubler, and the plurality of phase-shifted signals includes a first phase-shifted signal, a second phase-shifted signal, a third phase-shifted signal, and a fourth phase-shifted signal with phase differences of 45° in sequence.

[0013] In a second aspect, an embodiment of the present application further provides a chip including the above-mentioned frequency doubler.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device including the above-mentioned chip or frequency doubler.

[0015] The frequency multiplier provided by the embodiment of the present application is independent of the duty cycle of the input signal, and the output signal has high accuracy and few spurs.

[0016] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. Brief Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 The structural schematic diagram of the frequency multiplier provided by the embodiment of the present application is shown.

[0019] Figure 2 The structural schematic diagram of the frequency doubler provided by the embodiment of the present application is shown.

[0020] Figure 3 The signal timing diagram of the frequency doubler provided by the embodiment of the present application is shown. Detailed Description of the Embodiments

[0021] The following will describe in detail the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as a limitation of the present application.

[0022] In order to enable those skilled in the art to better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0023] In the embodiments of the present application, it should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0024] Moreover, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus that comprises a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus that comprises the element.

[0025] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations or descriptions. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0026] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and there is no limitation on which ones are included. For example, including at least one of A, B, and C, then what can be included is A, B, C, A and B, A and C, B and C, or A, B, and C.

[0027] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.

[0028] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0029] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actually existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0030] The embodiments of the present application provide a frequency multiplier, such as Figure 1As shown, the frequency doubler 100 includes a frequency division circuit 10, an injection-locked oscillator 20, and a logic circuit 30. The frequency division circuit 10 is configured to adjust the duty cycle of an input signal and generate a frequency-divided signal of the input signal, and the frequency-divided signal has a 50% duty cycle. The injection-locked oscillator 20 is configured to generate a plurality of phase-shifted signals of the frequency-divided signal, and there is a predetermined phase difference between the plurality of phase-shifted signals in sequence. The logic circuit 30 is configured to combine the plurality of phase-shifted signals to output a frequency-doubled signal of the input signal.

[0031] In some embodiments, the frequency division circuit 10 may employ a flip-flop, which is configured to flip its state whenever a falling edge or a rising edge of the input signal arrives. By using the flip-flop, the input signal can be divided by two and the frequency-divided signal can have a 50% duty cycle, without relying on the duty cycle of the input signal. In some specific implementations, the frequency division circuit 10 employs a D flip-flop, whose inverted output terminal is connected to the data input terminal, the clock input terminal of the D flip-flop receives the input signal, and the output terminal of the D flip-flop outputs the frequency-divided signal. In some other specific implementations, the frequency division circuit may employ a JK flip-flop, whose J terminal and K terminal are both connected to a high level, the clock input terminal of the JK flip-flop receives the input signal, and the Q terminal of the JK flip-flop outputs the frequency-divided signal. The D flip-flop and the JK flip-flop have a low circuit complexity, can automatically achieve a 50% duty cycle without an additional duty cycle correction circuit, and have a high duty cycle stability. Using edge triggering can avoid glitches.

[0032] The injection-locked oscillator 20 can synchronize the oscillation signal of an internal oscillator with respect to an injection signal injected from an external source, and can accurately adjust the phase difference with respect to the injection signal by removing the skew component of the injection signal with respect to the synchronized oscillation signal. In the embodiments of the present application, the frequency-divided signal generated by the frequency division circuit 10 serves as the injection signal of the injection-locked oscillator 20, and the injection-locked oscillator 20 achieves frequency synchronization, that is, the output frequency of the injection-locked oscillator 20 is equal to the frequency of the frequency-divided signal. The injection-locked oscillator 20 is capable of generating a plurality of phase-shifted signals of the frequency-divided signal, the frequencies of the plurality of phase-shifted signals are synchronized with the frequency-divided signal, and there is a predetermined phase difference between the plurality of phase-shifted signals in sequence. In the embodiments of the present application, the injection-locked oscillator 20 receives the frequency-divided signal and generates a plurality of phase-shifted versions of the frequency-divided signal, that is, a plurality of phase-shifted signals. The free oscillation frequency of an internal ring oscillator is preset to be near the injection frequency (FIN / 2). At this time, the injection frequency is injected into the ring oscillator through a buffer. Since the frequencies are close, the ring oscillator will resonate with the injection frequency and finally synchronize with the injection frequency. At this time, four signals with a 45-degree difference in their output signals can be selected from the ring oscillator.

[0033] The injection-locked oscillator 20 can be implemented as a ring oscillator (referred to as an injection-locked ring oscillator). In a specific implementation, the injection-locked oscillator 20 includes a plurality of phase stages connected in a loop, and a predetermined phase difference is generated between two adjacent phase stages among the plurality of phase stages, and the divided-frequency signal is injected into the loop. Optionally, each phase stage can be implemented as a differential amplifier.

[0034] In a specific implementation, the logic circuit 30 may include a plurality of exclusive-OR units and OR units. Each exclusive-OR unit is used to perform an exclusive-OR operation on a set of phase-shifted signals, and each set of phase-shifted signals includes two phase-shifted signals having the predetermined phase difference. The OR unit is used to perform an OR operation on the outputs of the plurality of exclusive-OR units to output a frequency-doubled signal. There is a predetermined phase difference between each set of phase-shifted signals, and each exclusive-OR unit can generate a pulse signal for each set of phase-shifted signals. The plurality of exclusive-OR units perform exclusive-OR operations on multiple sets of phase shifts to generate multiple pulse signals. The output signal of the OR unit is the multiple pulse signals.

[0035] Based on the predetermined phase difference generated by the injection-locked oscillator 20, various frequency doublings can be achieved. The frequency doubler in the embodiments of the present application is typically implemented as a frequency doubler. As Figure 2 shown, a typical frequency doubler 200 includes a frequency divider 210, an injection-locked oscillator 220, and a logic circuit 230. In the embodiments of the present application, the frequency divider 210 divides the input signal FIN by two and adjusts the duty cycle. Specifically, the frequency divider 210 can be implemented as a D flip-flop, and the inverted output terminal of the D flip-flop is connected to the data input terminal D. The clock input terminal of the D flip-flop receives the input signal FIN, and the output terminal Q of the D flip-flop outputs the divided-frequency signal FIL. As Figure 3 shown, the divided-frequency signal FIL has a 50% duty cycle and a frequency that is 1 / 2 of the input signal FIN. The injection-locked oscillator 220 receives the divided-frequency signal FIL generated by the frequency divider 210 and generates a first phase-shifted signal CK_IN<0>, a second phase-shifted signal CK_IN<1>, a third phase-shifted signal CK_IN<2>, and a fourth phase-shifted signal CK_IN<3> with phase differences of 45° in sequence. Specifically, as Figure 3As shown, the phase difference between the first phase shift signal CK_IN<0> and the frequency division signal FIL is 0°, the phase difference between the second phase shift signal CK_IN<1> and the frequency division signal FIL is 45°, the phase difference between the third phase shift signal CK_IN<2> and the frequency division signal FIL is 90°, and the phase difference between the fourth phase shift signal CK_IN<3> and the frequency division signal FIL is 135°. That is, the phase difference between the second phase shift signal CK_IN<1> and the first phase shift signal CK_IN<0> is 45°, the phase difference between the third phase shift signal CK_IN<2> and the second phase shift signal CK_IN<1> is 45°, and the phase difference between the fourth phase shift signal CK_IN<3> and the third phase shift signal CK_IN<2> is 45°.

[0036] In some embodiments, as Figure 2 shown, the injection-locked oscillator 220 is implemented as a ring oscillator (referred to as an injection-locked ring oscillator). In a specific implementation, the injection-locked oscillator 220 includes 4 phase stages connected in a loop, and a 45° phase difference is generated between two adjacent phase stages in the 4 phase stages. The frequency division signal FIL is injected into the loop. Specifically, as Figure 2 shown, the 4 phase stages include: a first differential amplifier amp1, whose input terminal receives the frequency division signal FIL, and whose positive output terminal op generates the second phase shift signal CK_IN<1>; a second differential amplifier amp2, whose positive input terminal ip is connected to the positive output terminal op of the first differential amplifier amp1, and whose negative input terminal in is connected to the negative output terminal on of the first differential amplifier amp1, and whose positive output terminal op generates the third phase shift signal CK_IN<2>; a third differential amplifier amp3, whose positive input terminal ip is connected to the positive output terminal op of the second differential amplifier amp2, and whose negative input terminal in is connected to the negative output terminal on of the second differential amplifier amp2, and whose positive output terminal op generates the fourth phase shift signal CK_IN<3>; a fourth differential amplifier amp0, whose positive input terminal ip is connected to the negative output terminal on of the third differential amplifier amp3, and whose negative input terminal in is connected to the positive output terminal op of the third differential amplifier amp3, and whose positive output terminal op is connected to the positive input terminal ip of the first differential amplifier amp1, and whose negative output terminal on is connected to the negative input terminal in of the first differential amplifier amp1. The positive output terminal op of the fourth differential amplifier amp0 generates the first phase shift signal CK_IN<0>.

[0037] In some embodiments, as Figure 2 shown. The injection-locked oscillator 220 may further include a buffer buffer, which is connected between the input terminal of the frequency divider 210 and the first differential amplifier amp1, and is used to maintain the edge shape of the frequency division signal FIL and set the DC bias point.

[0038] In some embodiments, as Figure 2As shown, the logic circuit 230 includes a first exclusive-OR unit 231, a second exclusive-OR unit 232, and an OR unit 233. The first exclusive-OR unit 231 is configured to perform an exclusive-OR operation on a first phase-shifted signal CK_IN<0> and a second phase-shifted signal CK_IN<1> to output a first intermediate signal A. The second exclusive-OR unit 232 is configured to perform an exclusive-OR operation on a third phase-shifted signal CK_IN<2> and a fourth phase-shifted signal CK_IN<3> to output a second intermediate signal B. The OR unit 233 performs an OR operation on the first intermediate signal A and the second intermediate signal B and outputs a frequency-doubled signal FOUT. As Figure 3 shown, the frequency of the frequency-doubled signal FOUT is twice that of the input signal FIN. In a specific implementation, the first exclusive-OR unit 231 and the second exclusive-OR unit 232 can be implemented as exclusive-OR gates, and the OR unit 233 can be implemented as an OR gate.

[0039] Reference Figure 2 and Figure 3 shown, the input signal FIN first enters a frequency divider 210, which generates a frequency-divided signal FIL with a duty cycle of 50% and a halved frequency. The frequency-divided signal FIL is output to an injection-locked oscillator 220, where a plurality of frequency-divided signals FIL with different phases are generated correspondingly. Four signals CK_IN<0>, CK_IN<1>, CK_IN<2>, and CK_IN<3> with a phase difference of 45° (a delay time of T / 8, where T is the period of the frequency-divided signal FIL) are selected and enter the logic circuit 230. The logic circuit 230 performs a logical algorithm on these four signals to obtain a frequency-doubled signal FOUT with a required duty cycle of 50% and a frequency twice that of the input signal FIN. Specifically, an exclusive-OR gate performs an exclusive-OR logic on CK_IN<0> and CK_IN<1> to obtain signal A, another exclusive-OR gate performs an exclusive-OR logic on CK_IN<2> and CK_IN<3> to obtain signal B, and then an OR logic is performed on A and B to obtain the frequency-doubled signal FOUT.

[0040] As Figure 2 shown in the frequency doubler, a stable 50% duty cycle and frequency division by two are automatically achieved through edge-triggered flip-flops, which are independent of the duty cycle of the input signal, with high precision and few spurs in the output signal. There is no need for a duty cycle correction circuit, greatly reducing the introduction of noise and being less affected by various circuit mismatches. There is no need to add passive devices such as resistors, capacitors, and inductors, the circuit occupies a small area, has a wide applicable frequency range, and strong versatility.

[0041] The embodiment of the present application further provides a chip, which includes the above-mentioned frequency multiplier. A chip is also called an integrated circuit (IC), and this chip can be but is not limited to an SOC (System on Chip) chip, an SIP (system in package) chip.

[0042] The embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned chip disposed inside the device body. The electronic device can be but is not limited to a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, a car center console screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, a cervical massager. The mobile terminal includes but is not limited to a smart phone, a laptop, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart floor sweeper, a smart light.

[0043] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A frequency multiplier, characterized in that, Comprising: A frequency division circuit for adjusting the duty cycle of an input signal and generating a frequency division signal of the input signal, the frequency division signal having a 50% duty cycle; An injection-locked oscillator for generating a plurality of phase-shifted signals of the frequency division signal, the plurality of phase-shifted signals having a predetermined phase difference in sequence; A logic circuit for combining the plurality of phase-shifted signals to output a frequency-doubled signal of the input signal.

2. The frequency doubler according to claim 1, characterized in that, The frequency division circuit includes: a flip-flop configured to flip its state whenever a falling edge or a rising edge of the input signal arrives, to obtain the frequency division signal having a 50% duty cycle.

3. The frequency doubler according to claim 2, characterized in that, The flip-flop includes: A D flip-flop, wherein the inverted output terminal of the D flip-flop is connected to the data input terminal, the clock input terminal of the D flip-flop receives the input signal, and the output terminal of the D flip-flop outputs the frequency division signal; or A JK flip-flop, wherein the J terminal and the K terminal of the JK flip-flop are both connected to a high level, the clock input terminal of the JK flip-flop receives the input signal, and the Q terminal of the JK flip-flop outputs the frequency division signal.

4. The frequency doubler according to claim 1, characterized in that, The logic circuit includes: A plurality of exclusive-OR units, each exclusive-OR unit for performing an exclusive-OR operation on a set of the phase-shifted signals, each set of the phase-shifted signals including two of the phase-shifted signals having the predetermined phase difference; An OR unit for performing an OR operation on the outputs of the plurality of exclusive-OR units to output the frequency-doubled signal.

5. The frequency doubler according to claim 4, wherein The plurality of exclusive-OR units includes: A first exclusive-OR unit for performing an exclusive-OR operation on a first phase-shifted signal and a second phase-shifted signal to output a first intermediate signal; A second exclusive-OR unit for performing an exclusive-OR operation on a third phase-shifted signal and a fourth phase-shifted signal to output a second intermediate signal; Wherein, the phase difference between the first phase-shifted signal, the second phase-shifted signal, the third phase-shifted signal, and the fourth phase-shifted signal is 45° in sequence.

6. The frequency doubler according to claim 1, characterized in that, The injection-locked oscillator includes a plurality of phase stages connected in a loop, a predetermined phase difference is generated between two adjacent phase stages among the plurality of phase stages, and the frequency division signal is injected into the loop.

7. The frequency doubler according to claim 6, wherein The plurality of phase stages includes: A first differential amplifier, whose input terminal receives the frequency division signal; A second differential amplifier, whose positive input terminal is connected to the positive output terminal of the first differential amplifier, and whose negative input terminal is connected to the negative output terminal of the first differential amplifier; A third differential amplifier, whose positive input terminal is connected to the positive output terminal of the second differential amplifier, and whose negative input terminal is connected to the negative output terminal of the second differential amplifier; A fourth differential amplifier, whose positive input terminal is connected to the negative output terminal of the third differential amplifier, whose negative input terminal is connected to the positive output terminal of the third differential amplifier, whose positive output terminal is connected to the positive input terminal of the first differential amplifier, and whose negative output terminal is connected to the negative input terminal of the first differential amplifier.

8. The frequency multiplier according to claim 7, characterized in that, The injection-locked oscillator further includes a buffer connected between the frequency division circuit and the first differential amplifier for maintaining the edge shape of the frequency division signal and setting its DC operating point.

9. The frequency multiplier according to any one of claims 1 to 8, characterized in that The frequency doubler is a frequency doubler, and the plurality of phase-shifted signals include a first phase-shifted signal, a second phase-shifted signal, a third phase-shifted signal, and a fourth phase-shifted signal having a phase difference of 45° in sequence.

10. A chip, characterized in that, Including the frequency doubler according to any one of claims 1 to 9 above.

11. An electronic device, characterized in that, Including a device main body and a chip as described in claim 10 above provided on the device main body.

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