Dead-zone-free high-gain time amplifier, calibration circuit, chip and electronic equipment

Abstract

The invention discloses a dead-zone-free high-gain time amplifier, a calibration circuit, a chip and electronic equipment, the high-gain time amplifier comprises two delay modules and two sub-module time amplifiers, and each sub-module time amplifier comprises a control circuit and an amplification circuit. In the top design, a time delay module is used, so that a working area of a sub-module time amplifier moves from a dead zone to a linear range when a very small time difference is input, and the dead zone problem of a traditional charging and discharging time amplifier under the condition of small time difference input is solved; and two delay paths and two amplification paths are used, so that the gain of the sub-module time amplifier is about two times of that of the sub-module time amplifier, and the sub-module time amplifier has the characteristic of high gain. In addition, the invention further provides an offset calibration circuit for the time amplifier, and the offset, caused by non-ideal factors, of the time amplifier at the output end can be effectively reduced. The method can be widely applied to the fields of clocks, communication, Internet of Things and the like.

Description

Technical Field

[0001] The invention relates to the fields of clocks, communications and the Internet of Things, and in particular to a high-gain time amplifier without a dead zone, a calibration circuit, a chip and an electronic device. Background Art

[0002] With the advancement of semiconductor technology, the power supply voltage of integrated circuits is constantly decreasing. The design and optimization of voltage domain analog circuits under advanced technology are becoming more and more difficult. At the same time, various applications have put forward higher requirements on the accuracy, speed and power consumption of analog-to-digital conversion circuits, thus generating a new type of analog-to-digital conversion technology, that is, turning the signal processing in the voltage domain to the signal processing in the time domain. Time to Digital Convertor (TDC) came into being under this background. TDC can convert time domain signals into digital signals. At present, it has a wide range of applications in fields such as All Digital Phase-Locked Loop (ADPLL). In ADPLL, the performance of TDC determines the performance of ADPLL to a certain extent. Therefore, TDC with high precision and large measurement range is a current research hotspot.

[0003] TDC has many architectures, such as single delay chain TDC, vernier delay chain TDC, ring oscillator TDC, time amplification TDC, etc. These architectures have their own advantages and disadvantages in terms of accuracy, measurement range, power consumption, etc. Time amplification TDC can achieve the effect of using very small power consumption to exchange higher resolution by adding a time amplifier (TA) in front of TDC to amplify the input time difference.

[0004] As a key module of time amplification TDC, TA has two main structures, one is SR latch type TA, and the other is charge-discharge type TA. The advantage of SR latch type TA is that there is no dead zone, but there are problems such as narrow linear range, more limited gain, and large PVT influence; while the charge-discharge type TA has a larger linear range, fewer factors that restrict gain, and less PVT influence, but there is a dead zone problem. Therefore, solving the dead zone problem of charge-discharge type TA is a solution to design high-performance TA. Summary of the invention

[0005] In order to solve at least one of the technical problems existing in the prior art to a certain extent, the object of the present invention is to provide a high-gain time amplifier, a calibration circuit, a chip and an electronic device without a dead zone.

[0006] The first technical solution adopted by the present invention is:

[0007] A high-gain time amplifier without dead zone, comprising a first sub-module time amplifier and a second sub-module time amplifier with the same structure;

[0008] By setting a first delay module at the input end of the first sub-module time amplifier, the first sub-module time amplifier operates in a region far from the dead zone;

[0009] By setting a second delay module at the input end of the second sub-module time amplifier, the second sub-module time amplifier operates in a region far from the dead zone;

[0010] Superimpose the outputs of the first sub-module time amplifier and the second sub-module time amplifier as the output of the high-gain time amplifier to achieve high-gain characteristics.

[0011] Further, the two input ends of the high-gain time amplifier are respectively: a first input end IN1 and a second input end IN2;

[0012] The signal of the first input end IN1 passes through the first delay module to obtain a first input delay signal IN1d; the first input delay signal IN1d is input to the first input end TA1_IN1 of the first sub-module time amplifier TA1; the signal of the second input end IN2 is input to the second input end TA1_IN2 of the first sub-module time amplifier TA1;

[0013] The signal of the second input end IN2 passes through the second delay module to obtain a second input delay signal IN2d; the second input delay signal IN2d is input to the first input end TA1_IN1 of the second sub-module time amplifier TA2; the signal of the first input end IN1 is input to the second input end TA2_IN2 of the second sub-module time amplifier TA2;

[0014] The second output end TA1_OUT2 of the first sub-module time amplifier TA1 serves as the second output end OUT2 of the high-gain time amplifier, and the second output end TA2_OUT2 of the second sub-module time amplifier TA2 serves as the first output end OUT1 of the high-gain time amplifier.

[0015] Further, the sub-module time amplifier includes a control circuit and an amplification circuit;

[0016] The two input ends of the control circuit respectively serve as the two input ends of the sub-module time amplifier, and according to the two input signals, correspondingly output signals for controlling the switching tubes and the reset circuit in the amplification circuit;

[0017] The amplification circuit includes a capacitor CA, a capacitor CB, a first output comparator, a second output comparator, a reset circuit, and four discharge branches A1, A2, B1, B2. Switching tubes are provided on the four discharge branches A1, A2, B1, B2;

[0018] One end of the capacitor CA is connected to the charge and discharge node A, and the other end is grounded; one ends of the discharge branches A1 and A2 are connected to the charge and discharge node A, and the other ends are grounded. By controlling the switches on the branches, the discharge of the capacitor CA is realized; the charge and discharge node A is connected to the power supply voltage through a reset circuit;

[0019] One end of the capacitor CB is connected to the charge and discharge node B, and the other end is grounded; one ends of the discharge branches B1 and B2 are connected to the charge and discharge node B, and the other ends are grounded. By controlling the switches on the branches, the discharge of the capacitor CB is realized; the charge and discharge node B is connected to the power supply voltage through a reset circuit;

[0020] One input terminal of the first output comparator is connected to the charge and discharge node A, and the output terminal serves as the first output terminal OUT1 of the sub-module time amplifier; one input terminal of the second output comparator is connected to the charge and discharge node B, and the output terminal serves as the second output terminal OUT2 of the sub-module time amplifier.

[0021] Further, the control circuit includes 1 OR logic gate, 2 AND logic gates and 2 INOR logic gates;

[0022] The two input terminals of the OR logic gate are respectively connected to the input signals IN1 and IN2, and the OR logic gate outputs a reset signal RST;

[0023] The two input terminals of the first AND logic gate are respectively connected to the input signals IN1 and IN2, and the first AND logic gate outputs a current switch signal SWA2 for the A2 branch;

[0024] The two input terminals of the second AND logic gate are respectively connected to the input signals IN2 and IN1, and the second AND logic gate outputs a current switch signal SWB2 for the B2 branch;

[0025] The inverting input terminal of the first INOR logic gate is connected to the input signal IN1, and the non-inverting input terminal is connected to the input signal IN2. The first INOR logic gate outputs a current switch signal SWA1 for the A1 branch;

[0026] The inverting input terminal of the second INOR logic gate is connected to the input signal IN2, and the non-inverting input terminal is connected to the input signal IN1. The second INOR logic gate outputs a current switch signal SWB1 for the B1 branch.

[0027] Further, both the first output comparator and the second output comparator are implemented by inverters; the input terminal of the inverter is connected to the charge and discharge node, and the output terminal serves as the output terminal OUT of the sub-module time amplifier;

[0028] The reset circuit is implemented using two PMOS transistors MA5 and MB5. The gates of transistors MA5 and MB5 are connected to the RST signal output by the control circuit, the sources are connected to the supply voltage VDD, and the drains are respectively connected to the charge and discharge nodes A and B.

[0029] Further, each discharge branch includes a switching transistor and a current source, and both the switching transistor and the current source are implemented using NMOS transistors;

[0030] In discharge branch A1, transistor MA1 serves as the current source, with its gate connected to the bias voltage Vbias, its source connected to the ground GND, and its drain connected to the source of transistor MA3 which serves as the switching transistor; the gate of transistor MA3 is connected to the control signal SWA1, and its drain is connected to the charge and discharge node A;

[0031] In discharge branch A2, transistor MA2 serves as the current source, with its gate connected to the bias voltage Vbias, its source connected to the ground GND, and its drain connected to the source of transistor MA4 which serves as the switching transistor; the gate of transistor MA4 is connected to the control signal SWA2, and its drain is connected to the charge and discharge node A;

[0032] In discharge branch B1, transistor MB1 serves as the current source, with its gate connected to the bias voltage Vbias, its source connected to the ground GND, and its drain connected to the source of transistor MB3 which serves as the switching transistor; the gate of transistor MB3 is connected to the control signal SWB1, and its drain is connected to the charge and discharge node B;

[0033] In discharge branch B2, transistor MB2 serves as the current source, with its gate connected to the bias voltage Vbias, its source connected to the ground GND, and its drain connected to the source of transistor MB4 which serves as the switching transistor; the gate of transistor MB4 is connected to the control signal SWB2, and its drain is connected to the charge and discharge node B;

[0034] The relationship of the aspect ratios of transistors MA1, MA2, MB1, and MB2 is as follows:

[0035]

[0036] where represents the aspect ratio of transistor MA1, represents the aspect ratio of transistor MB1, represents the aspect ratio of transistor MA2, represents the aspect ratio of transistor MB2; K is the multiple of the aspect ratios of different transistors;

[0037] The final amplification relationship of the high-gain time amplifier is as follows:

[0038] T out =(2K - 1)T in

[0039] Wherein, T out is the output time difference, and T in is the input time difference.

[0040] Furthermore, the magnitude relationship of the current sources needs to satisfy I1A = I1B = K * I2A = K * I2B, and the magnitude relationship of the capacitors needs to satisfy CA = CB; Nodes A and B are connected to the "-" terminal of the comparator, the reference voltage Vref is connected to the "+" terminal of the comparator, and the branch switches control the discharge current of nodes A and B. When the voltage of node A or B drops below Vref, a rising edge is generated at the corresponding output terminal.

[0041] Furthermore, the sub-module time amplifier circuit specifically includes:

[0042] Each current source is implemented by NMOS transistors with specific size ratios. The I1A, I2A, I1B, and I2B current sources are respectively implemented by transistors MA1, MA2, MB1, and MB2. The gates of these transistors are connected together and supplied with power through Vbias to obtain proportional current magnitudes;

[0043] The switches of each current source branch are also implemented by NMOS transistors. The switches of the I1A, I2A, I1B, and I2B branches are respectively implemented by transistors MA3, MA4, MB3, and MB4. The gates are respectively connected to the control signals SWA1, SWA2, SWB1, and SWB2 generated by the control circuit to realize the control of the discharge current of nodes A and B in different time periods;

[0044] The reset circuit is implemented by PMOS transistors. The reset switches of nodes A and B are respectively implemented by transistors MA5 and MB5. The gates are connected to the RST reset signal generated by the control circuit, and the sources are connected to the power supply voltage source VDD to realize recharging the voltages of nodes A and B to the value of the power supply voltage VDD after the RST signal arrives;

[0045] The comparator circuit is implemented by a CMOS inverter. The NMOS transistor MA6 and the PMOS transistor MA7 form a CMOS inverter. Node A is used as the input of the inverter, and the first output terminal OUT1 of the sub-module TA is used as the output of the inverter; Similarly, the NMOS transistor MB6 and the PMOS transistor MB7 form a CMOS inverter. Node B is used as the input, and the second output terminal OUT2 of the sub-module TA is used as the output. The inverter is equivalent to a comparator with the "-" terminal connected to the input and the "+" terminal connected to the switching threshold Vth of the inverter itself.

[0046] The second technical solution adopted by the present invention is:

[0047] An offset calibration circuit is applied to the high-gain time amplifier without dead zone as described above, and is characterized in that the offset output by the high-gain time amplifier is calibrated by adjusting the capacitance difference between the two output terminals of the high-gain time amplifier.

[0048] Further, the capacitance difference between the two output terminals is realized by two sets of adjustable capacitors.

[0049] Further, the offset calibration circuit includes two selectors MUX, two sets of adjustable capacitors, two buffers Buffers, two D flip-flops, a digital calibration logic circuit and an encoder;

[0050] The input terminal of the first selector is connected to the input signal IN1 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL;

[0051] The input terminal of the second selector is connected to the input signal IN2 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL;

[0052] The two sets of adjustable capacitors are respectively connected to the output terminals OUT1 and OUT2 of the high-gain time amplifier. The adjustable capacitors are composed of a series of unit capacitors and are controlled by a temperature code;

[0053] The output signals OUT1 and OUT2 are connected to the input terminals of the two buffers. The output terminal of the first buffer is connected to the data input terminal of the first D flip-flop and the clock input terminal of the second D flip-flop. The output terminal of the second buffer is connected to the data input terminal of the second D flip-flop and the clock input terminal of the first D flip-flop; The data output terminals Q1 and Q2 of the D flip-flops are connected to the digital logic calibration circuit; The binary code signal of the digital logic calibration circuit is used to control the size of the adjustable capacitor after being converted into a temperature code.

[0054] Further, the working mode of the offset calibration circuit is as follows:

[0055] When the calibration mode is turned on, if the output of one path is ahead of the output of the other path, the corresponding binary control code of the ahead path is increased by 1, so as to increase the capacitance of the ahead path; if the output of one path is behind the output of the other path, the corresponding binary control code of the behind path is decreased by 1, so as to decrease the capacitance of the behind path.

[0056] Furthermore, the operation mode of the offset calibration circuit of the time amplifier includes: when the calibration enable EN_CAL is at a high level, the input signals of the TA are switched from the original first input terminal IN1 and second input terminal IN2 to the calibration clock CAL_clk, and at the same time, the digital calibration logic circuit is turned on. The output of the TA passes through a series of buffers Buffers and is connected to the cross-connected DFFs to detect whether the output time difference at this time is within a certain range. If it exceeds this range, it indicates that there is a large offset, then the calibration logic will change the capacitance value at the output terminal by changing the control code, thereby calibrating the offset at the output terminal. The trigger clock of the digital calibration logic is triggered by the signal after the CAL_clk passes through an inverter, that is, triggered at the falling edge of the CAL_clk, ensuring that there is sufficient delay margin in the link from the TA to the digital calibration logic circuit.

[0057] The third technical solution adopted by the present invention is:

[0058] A chip includes a dead-zone-free high-gain time amplifier as described above, and / or an offset calibration circuit as described above.

[0059] The fourth technical solution adopted by the present invention is:

[0060] An electronic device includes the chip as described above.

[0061] The beneficial effects of the present invention include:

[0062] (1) By using a delay module, the present invention enables the working area of the sub-module time amplifier to move from the dead zone to the linear range when the input time difference is very small.

[0063] (2) The present invention simplifies the comparator module in the charge and discharge time amplifier by using an inverter.

[0064] (3) Through two delay paths and two amplification paths, the present invention enables the gain of the top-level time amplifier to reach about twice that of the sub-module time amplifier.

[0065] (4) By using an offset calibration circuit, the present invention can effectively reduce the offset caused by non-ideal factors at the output terminal of the time amplifier TA. Description of the Drawings

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following introduces the accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings below only facilitate the clear expression of some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0067] Figure 1 It is a schematic structural diagram of sub-module TA in Embodiment 1 of the present invention, including a control circuit and an amplification circuit;

[0068] Figure 2 It is a circuit schematic diagram of the control circuit in Embodiment 1 of the present invention;

[0069] Figure 3 It is a circuit schematic diagram of the amplification circuit in Embodiment 1 of the present invention;

[0070] Figure 4 It is a change curve graph of the output time difference and the output time difference slope when the input of a single sub-module TA in Embodiment 1 of the present invention ranges from -200 ps to 200 ps;

[0071] Figure 5 It is a schematic structural diagram of a dead-zone-free high-gain time amplifier provided in Embodiment 2 of the present invention;

[0072] Figure 6 It is a change curve graph of the output time difference and the time amplification gain when the input of the dead-zone-free high-gain time amplifier provided in Embodiment 2 of the present invention ranges from -200 ps to 200 ps;

[0073] Figure 7 It is a circuit schematic diagram of the TA offset calibration circuit provided in Embodiment 3 of the present invention;

[0074] Figure 8 It is a calibration logic flow chart of the TA offset calibration circuit provided in Embodiment 3 of the present invention;

[0075] Figure 9 It is a schematic layout diagram of the TA and the calibration circuit provided in the embodiments of the present invention. Detailed implementation manners

[0076] The following details the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention. For the step numbers in the following embodiments, they are only set for the convenience of explanation and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0077] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0078] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the present number, above, below, within, etc. are understood as including the present number. If the first and second are described, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0079] In the description of the present invention, unless otherwise clearly defined, words such as setting, installing, connecting, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0080] Embodiment 1

[0081] Refer to Figure 1 , Figure 1 It is a schematic diagram of the sub-module TA structure. The sub-module TA specifically includes a control circuit and an amplification circuit; the input end of the control circuit is connected to the input signals IN1 and IN2, and the output end is connected to the amplification circuit. The control circuit controls the charging and discharging of the current source in the amplification circuit according to the input signals to realize the amplification of the time difference.

[0082] (1) Circuit principle description

[0083] When both signals are at low level, both nodes A and B are maintained at the VDD potential, that is, when [IN1, IN2] = [0, 0], the RST switch is closed, and nodes A and B are charged to VDD;

[0084] When the rising edge of one of the signals IN1 (or IN2) arrives, that is, when [IN1, IN2] = [1, 0] (or [IN1, IN2] = [0, 1]), RST is disconnected, and SWA1 (or SWB1) is closed, and the corresponding node A (or B) starts to discharge with a relatively large current I1A (or I1B), and the discharge rate is I1A / CA (or I1B / CB);

[0085] When the rising edge of the signal on the second path also arrives, i.e., [IN1, IN2] = [1, 1], SWA1 and SWB1 are disconnected, and SWA2 and SWB2 are closed. Nodes A and B discharge simultaneously with relatively small currents I2A and I2B, and the discharge rates are I2A / CA and I2B / CB. (Note: I1A = I1B = K * I2A = K * I2B, CA = CB)

[0086] In this way, within the time difference between the rising edges of the two paths of signals, due to the rapid discharge of one node and the non-discharge of the other node, a voltage difference is formed between nodes A and B, and this voltage difference can be expressed as:

[0087] (or )(1)

[0088] In the formula, C A is the capacitance value of capacitor CA, and T in is the input time difference.

[0089] After the rising edges of both paths of signals arrive, the two nodes discharge at the same rate simultaneously. The voltage difference in the previous stage determines the time difference for the two nodes to discharge below the comparator reference voltage Vref. When the nodes discharge below Vref, a rising edge is generated at the corresponding output end. Therefore, the time difference between the two rising edges of the output can be expressed as:

[0090]

[0091] That is, in the ideal case: the output time difference is K times the input time difference, and K is the ratio of the large current to the small current (or the ratio of the rapid discharge rate to the slow discharge rate).

[0092] However, due to the delay in the switches and control circuits, etc., when the input time difference is small, rapid discharge cannot be formed in the first stage, so a voltage difference cannot be formed between the two nodes, ultimately resulting in no amplification effect. The input region without amplification effect is called the dead zone. Therefore, the relationship between Tout and Tin of sub-module TA is corrected as:

[0093]

[0094] where b is the intercept when the curve outside the dead zone of Tin is extended to Tin = 0.

[0095] Refer to Figure 2 , Figure 2 for the specific implementation of the control circuit in sub-module TA. From the previous analysis, the logical relationship between each switch and the input can be obtained:

[0096] When [IN1, IN2] = [0, 0], RST is closed. When RST is implemented by a PMOS, that is, RST is triggered by a low level, then ~RST = ~(IN1|IN2), that is, RST = IN1|IN2, which can be implemented by a 2-input OR gate.

[0097] When [IN1, IN2] = [1, 1], SWA2 and SWB2 are closed. When SWA2 and SWB2 are implemented by NMOS, SWA2 and SWB2 are triggered by a high level, then SWA2 = SWB2 = IN1&IN2, which can be implemented by a 2-input AND gate. To ensure symmetry, it is implemented by two AND gates instead of a single AND gate.

[0098] When [IN1, IN2] = [1, 0], SWA1 is closed. When SWA1 is implemented by NMOS, SWA1 is triggered by a high level, then SWA1 = IN1&(~IN2) = ~[(~IN1)|IN2], which can be implemented by a 2-input INOR gate with a single input inverted.

[0099] When [IN1, IN2] = [0, 1], similarly, SWB1 = ~[IN1|(~IN2)], which is also implemented by INOR.

[0100] See Figure 3 , Figure 3 For the specific implementation of the amplifier circuit in sub-module TA:

[0101] The current sources I1A, I2A, I1B, and I2B are respectively implemented by transistors MA1, MA2, MB1, and MB2. The gates of these transistors are connected together, and a proportional current magnitude is obtained by supplying power to the gates through Vbias;

[0102] The switches of each current source branch are also implemented by NMOS transistors. The switches of the I1A, I2A, I1B, and I2B branches are respectively implemented by transistors MA3, MA4, MB3, and MB4. The gates are respectively connected to the SWA1, SWA2, SWB1, and SWB2 control signals generated by the control circuit to realize the control of the discharge current of nodes A and B in different time periods;

[0103] The reset circuit is implemented by PMOS transistors. The reset switches of nodes A and B are respectively implemented by transistors MA5 and MB5. The gates are connected to the RST reset signal generated by the control circuit, and the sources are connected to the power supply voltage source VDD to realize recharging the voltages of nodes A and B to the value of the power supply voltage VDD after the RST signal arrives;

[0104] The comparator circuit is implemented by a CMOS inverter. The NMOS transistor MA6 and the PMOS transistor MA7 form a CMOS inverter, with the A node as the input of the inverter and the first output terminal OUT1 of the sub-module TA as the output of the inverter. Similarly, the NMOS transistor MB6 and the PMOS transistor MB7 form a CMOS inverter, with the B node as the input and the second output terminal OUT2 of the sub-module TA as the output. The inverter is equivalent to a comparator with its "-" terminal connected to the input and its "+" terminal connected to the switching threshold Vth of the inverter itself.

[0105] (2) Simulation results

[0106] Let the current ratio K of the sub-module TA be 20. The results for an input time difference ranging from -200 ps to 200 ps are as Figure 4 shown. The dead zone range of the sub-module TA is approximately ±20 ps. In the working region far from the dead zone (40 ps to 200 ps), the curve slope is approximately 19.75. Due to non-ideal factors such as non-linearity, there is a deviation from the ideal result.

[0107] Embodiment 2

[0108] Refer to Figure 5 , this embodiment provides a high-gain charge-discharge type time amplifier without dead zone, including a delay circuit and a sub-module time amplifier, and the delay circuit is connected to the sub-module time amplifier. The time amplifier is provided with two delay paths and two amplification paths. The delay circuit realizes the dead-zone-free characteristic of the time amplifier, and the two paths realize the high-gain characteristic of the time amplifier.

[0109] The two delay paths and two amplification paths specifically include a first input terminal IN1, a second input terminal IN2, a first input delay signal IN1d, a second input delay signal IN2d, a first sub-module time amplifier TA1, a second sub-module time amplifier TA2, a first output terminal OUT1, and a second output terminal OUT2; the first input terminal IN1 and the second input terminal IN2 respectively pass through two identical delay paths to obtain a first input delay signal IN1d and a second input delay signal IN2d; the first input delay signal IN1d and the second input terminal signal IN2 are respectively connected to the first input terminal TA1_IN1 and the second input terminal TA2_IN2 of the first sub-module time amplifier TA1; the second input delay signal IN2d and the first input terminal signal IN1 are respectively connected to the first input terminal TA2_IN1 and the second input terminal TA2_IN2 of the second sub-module time amplifier TA2; the second output terminal TA1_OUT2 of the first sub-module time amplifier TA1 serves as the second output terminal OUT2; the second output terminal TA2_OUT2 of the second sub-module time amplifier TA2 serves as the first output terminal OUT1.

[0110] (1) Circuit principle description

[0111] Embodiment 2 aims to solve the dead zone problem of the sub-module TA. To make the sub-module TA work in a region far from the dead zone, a delay module Toff is added, and two sub-module TAs are used for amplification:

[0112] If the input time difference is Tin and the delay time is Toff (Toff > Tin and Toff - Tin is far from the dead zone), then:

[0113] t in1 -t in2 = T in (4)

[0114] t in2,offset -t in2 = t in1,offset -t in1 = T off (5)

[0115] The inputs of the two TAs are respectively:

[0116] TA1 in = t in1,offset -t in2 = T off +T in (6)

[0117] TA2 in = t in2,offset -t in1 = Toff -T in (7)

[0118] From (3), (6), (7):

[0119] TA1 out = K * TA1 in + b = K(T off + T in ) + b = t TA1out1 - t TA1out2 (8)

[0120] TA2 out = K * TA2 in + b = K(T off - T in ) + b = t TA2out1 - t TA2out2 (9)

[0121] Taking TA2out2 as OU1 of the top - level TA and TA1out2 as OUT2 of the top - level TA, then:

[0122] t out1 - t out2 = t TA2out2 - t TA1out2

[0123] =(TA1 out - TA2 out )+(t TA2out1 - t TA1out1 )

[0124] = 2K * T in +(t TA2out1 - t TA1out1 ) (10)

[0125] And the IN1 ends corresponding to the OUT1 ends of the two sub - modules TA are both delayed input signals. Therefore, within the sub - module TA, there is only a process of slow - rate voltage drop. So:

[0126] t TA2out1 - t TA1out1 = t in2,offset - t in1,offset =- T in (11)

[0127] From (10), (11):

[0128] T out = t out2 - t out1 =(2K - 1)T in (12)

[0129] It can be seen from this that in the top-level design, a delay circuit is used to move the working area of the sub-module time amplifier from the dead zone to the linear range when the input has a very small time difference, solving the dead-zone problem of traditional charge-discharge time amplifiers under the condition of small time-difference input. In addition, two delay paths and two amplification paths are used, and the gain is also increased from K to 2K - 1, achieving approximately twice the gain of the sub-module time amplifier and featuring high-gain characteristics.

[0130] (2) Simulation results

[0131] Connect the sub-module TA and the delay module as Figure 5 shown to form the top-level TA. The results with an input time difference of -200 ps to 200 ps are as Figure 6 shown. The linear range of the top-level TA is approximately ±50 ps, and there is no dead zone. Within the linear range, the average gain is approximately 38.5, which also corresponds to the theoretically derived result of 2K - 1 (K = 19.75), thus verifying the dead-zone-free and high-gain characteristics of this embodiment.

[0132] Embodiment 3

[0133] As Figure 7 shown, Embodiment 3 provides an offset calibration circuit applied to the TA provided in Embodiment 2. The offset calibration circuit specifically includes two selectors MUX, two groups of adjustable capacitors, two buffers Buffers, two D flip-flops, a digital calibration logic circuit, and an encoder;

[0134] The input terminal of the first selector is connected to the input signal IN1 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL;

[0135] The input terminal of the second selector is connected to the input signal IN2 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL;

[0136] The two groups of adjustable capacitors are respectively connected to the output terminals OUT1 and OUT2 of the high-gain time amplifier. The adjustable capacitors are composed of a series of unit capacitors and are controlled by temperature codes. Among them, the adjustable capacitor connected to the output terminal OUT1 is controlled by ControlCode1, and the adjustable capacitor connected to the output terminal OUT2 is controlled by Control Code2;

[0137] The output signals OUT1 and OUT2 are connected to the input ends of two buffers. The output end of the first buffer is connected to the data input end of the first D flip-flop and the clock input end of the second D flip-flop. The output end of the second buffer is connected to the data input end of the second D flip-flop and the clock input end of the first D flip-flop. The data output ends Q1 and Q2 of the D flip-flops are connected to the digital logic calibration circuit. After the binary code signal of the digital logic calibration circuit is converted into a temperature code, it is used to control the size of the adjustable capacitor.

[0138] The specific working mode of this offset calibration circuit is as follows: When the calibration enable EN_cal is at a high level, the input signal of TA switches from the original first input end IN1 and second input end IN2 to the calibration clock CAL_clk. This function is implemented by the selector MUX, which is equivalent to the input time difference being 0 at this time, and at the same time, the digital calibration logic circuit is turned on. The two output ends of TA are connected to a variable capacitor controlled by the Control Code. The time difference at the output end can be changed by changing the difference between the two capacitors. The output of TA passes through a series of buffers Buffers and is connected to the cross-connected DFF. If the time difference between the two outputs is very small (less than the setup time of the DFF, about 2 ps), then the DFF outputs [Q1, Q2] = [0, 0], indicating that the offset is small and the Control Code remains unchanged. If the time difference between the two outputs is large, it will cause the DFF outputs [Q1, Q2] = [1, 0] (or [Q1, Q2] = [0, 1]), indicating that there is a large offset, and the rising edge of the first path leads the second path (or the rising edge of the second path leads the first path). At this time, the calibration logic will increase the capacitance of the first path (or the second path) and decrease the capacitance of the second path (or the first path), change the corresponding control code, and repeat this process until [Q1, Q2] = [0, 0], thereby calibrating the offset at the output end. The trigger clock of the digital calibration logic is triggered by the signal after the CAL_clk passes through the inverter, that is, it is triggered at the falling edge of CAL_clk, ensuring that there is sufficient delay margin in the link from TA to the digital calibration logic circuit. The flow chart of the calibration circuit is as Figure 8 shown.

[0139] See Figure 9 , Figure 9 It is a schematic layout diagram of the dead zone-free high-gain time amplifier provided in Embodiment 2 and the offset calibration circuit provided in Embodiment 3.

[0140] An embodiment of the present invention also provides a chip, including the above-mentioned dead zone-free high-gain time amplifier and its offset calibration circuit.

[0141] This embodiment also provides an electronic device, including the above-mentioned chip.

[0142] Specifically, the chip and the electronic device include the above-mentioned time amplifier and calibration circuit, as well as other auxiliary or functional circuits. For example, the chip and the electronic device may also include a power supply circuit or an interface circuit, etc.

[0143] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0144] The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those of ordinary skill in the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the essence of the content of the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-gain time amplifier without dead zone, characterized in that, It includes a first sub-module time amplifier and a second sub-module time amplifier with the same structure; By setting a first delay module at the input end of the first sub-module time amplifier, the first sub-module time amplifier operates in a region far from the dead zone; By setting a second delay module at the input end of the second sub-module time amplifier, the second sub-module time amplifier operates in a region far from the dead zone; The outputs of the first sub-module time amplifier and the second sub-module time amplifier are superimposed as the output of the high-gain time amplifier to achieve high-gain characteristics.

2. The high-gain time amplifier without dead zone according to claim 1, wherein The two input ends of the high-gain time amplifier are respectively: the first input end IN1 and the second input end IN2; The signal at the first input end IN1 passes through the first delay module to obtain a first input delay signal IN1d; the first input delay signal IN1d is input to the first input end TA1_IN1 of the first sub-module time amplifier TA1; the signal at the second input end IN2 is input to the second input end TA1_IN2 of the first sub-module time amplifier TA1; The signal at the second input end IN2 passes through the second delay module to obtain a second input delay signal IN2d; the second input delay signal IN2d is input to the first input end TA1_IN1 of the second sub-module time amplifier TA2; the signal at the first input end IN1 is input to the second input end TA2_IN2 of the second sub-module time amplifier TA2; The second output end TA1_OUT2 of the first sub-module time amplifier TA1 serves as the second output end OUT2 of the high-gain time amplifier, and the second output end TA2_OUT2 of the second sub-module time amplifier TA2 serves as the first output end OUT1 of the high-gain time amplifier.

3. The high-gain time amplifier without dead zone according to claim 1, wherein The sub-module time amplifier includes a control circuit and an amplification circuit; The two input ends of the control circuit respectively serve as the two input ends of the sub-module time amplifier, and according to the two input signals, correspondingly output signals for controlling the switching tubes and the reset circuit in the amplification circuit; The amplification circuit includes a capacitor CA, a capacitor CB, a first output comparator, a second output comparator, a reset circuit, and four discharge branches A1, A2, B1, B2. Switching tubes are provided on the four discharge branches A1, A2, B1, B2; One end of the capacitor CA is connected to the charge-discharge node A, and the other end is grounded; one ends of the discharge branches A1 and A2 are connected to the charge-discharge node A, and the other ends are grounded. By controlling the switches on the branches, the discharge of the capacitor CA is realized; the charge-discharge node A is connected to the power supply voltage through the reset circuit; One end of the capacitor CB is connected to the charge-discharge node B, and the other end is grounded; one ends of the discharge branches B1 and B2 are connected to the charge-discharge node B, and the other ends are grounded. By controlling the switches on the branches, the discharge of the capacitor CB is realized; the charge-discharge node B is connected to the power supply voltage through the reset circuit; The input end of the first output comparator is connected to the charge-discharge node A, and the output end serves as the first output end OUT1 of the sub-module time amplifier; the input end of the second output comparator is connected to the charge-discharge node B, and the output end serves as the second output end OUT2.

4. A high-gain time amplifier without dead zone according to claim 3, characterized in that The control circuit includes one OR logic gate, two AND logic gates, and two INOR logic gates; Two input terminals of the OR logic gate are respectively connected to input signals IN1 and IN2, and the OR logic gate outputs a reset signal RST; Two input terminals of the first AND logic gate are respectively connected to input signals IN1 and IN2, and the first AND logic gate outputs an A2-branch current switch signal SWA2; Two input terminals of the second AND logic gate are respectively connected to input signals IN2 and IN1, and the second AND logic gate outputs a B2-branch current switch signal SWB2; The inverting input terminal of the first INOR logic gate is connected to input signal IN1, and the non-inverting input terminal is connected to input signal IN2. The first INOR logic gate outputs an A1-branch current switch signal SWA1; The inverting input terminal of the second INOR logic gate is connected to input signal IN2, and the non-inverting input terminal is connected to input signal IN1. The second INOR logic gate outputs a B1-branch current switch signal SWB1.

5. A high-gain time amplifier without dead zone according to claim 3, characterized in that, Both the first output comparator and the second output comparator are implemented by inverters; the input terminals of the inverters are connected to the charge-discharge nodes, and the output terminals serve as the output terminal OUT of the sub-module time amplifier; The reset circuit is implemented by two PMOS transistors MA5 and MB5. The gates of transistors MA5 and MB5 are connected to the RST signal output by the control circuit, the sources are connected to the supply voltage VDD, and the drains are respectively connected to charge-discharge node A and charge-discharge node B.

6. The high-gain time amplifier without dead zone according to claim 3, wherein, Each discharge branch includes a switching transistor and a current source, and both the switching transistor and the current source are implemented by NMOS transistors; In discharge branch A1, transistor MA1 serves as the current source, the gate is connected to the bias voltage Vbias, the source is connected to the ground GND, and the drain is connected to the source of transistor MA3 serving as the switching transistor; The gate of transistor MA3 is connected to the control signal SWA1, and the drain is connected to charge-discharge node A; In discharge branch A2, transistor MA2 serves as the current source, the gate is connected to the bias voltage Vbias, the source is connected to the ground GND, and the drain is connected to the source of transistor MA4 serving as the switching transistor; The gate of transistor MA4 is connected to the control signal SWA2, and the drain is connected to charge-discharge node A; In discharge branch B1, transistor MB1 serves as the current source, the gate is connected to the bias voltage Vbias, the source is connected to the ground GND, and the drain is connected to the source of transistor MB3 serving as the switching transistor; The gate of transistor MB3 is connected to the control signal SWB1, and the drain is connected to charge-discharge node B; In discharge branch B2, transistor MB2 serves as the current source, the gate is connected to the bias voltage Vbias, the source is connected to the ground GND, and the drain is connected to the source of transistor MB4 serving as the switching transistor; The gate of transistor MB4 is connected to the control signal SWB2, and the drain is connected to charge-discharge node B; The relationship of the aspect ratios of transistors MA1, MA2, MB1, and MB2 is as follows: In the formula, represents the width-to-length ratio of transistor MA1, represents the width-to-length ratio of transistor MB1, represents the width-to-length ratio of transistor MA2, represents the width-to-length ratio of transistor MB2; K is the multiple of the width-to-length ratios of different transistors; The final amplification relationship of the high-gain time amplifier is as follows: T out =(2K - 1)T in where T out is the output time difference and T in is the input time difference.

7. An offset calibration circuit, applied to the high-gain time amplifier without dead zone as claimed in any one of claims 1 to 6, characterized in that: By adjusting the capacitance difference between the two output terminals of the high-gain time amplifier, the offset of the output of the high-gain time amplifier is calibrated.

8. An offset calibration circuit according to claim 7, characterized in that, The offset calibration circuit includes two selectors (MUX), two groups of adjustable capacitors, two buffers, two D flip-flops, a digital calibration logic circuit, and an encoder; The input terminals of the first selector are connected to the input signal IN1 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL; The input terminals of the second selector are connected to the input signal IN2 and the calibration clock CAL_CLK, and the enable terminal is connected to the calibration enable EN_CAL; The two groups of adjustable capacitors are respectively connected to the output terminals OUT1 and OUT2 of the high-gain time amplifier. The adjustable capacitors are composed of a series of unit capacitors and are controlled by temperature codes; The output signals OUT1 and OUT2 are connected to the input terminals of the two buffers. The output terminal of the first buffer is connected to the data input terminal of the first D flip-flop and the clock input terminal of the second D flip-flop. The output terminal of the second buffer is connected to the data input terminal of the second D flip-flop and the clock input terminal of the first D flip-flop. The data output terminals Q1 and Q2 of the D flip-flops are connected to the digital logic calibration circuit; the binary code signal of the digital logic calibration circuit is used to control the size of the adjustable capacitor after being converted into a temperature code.

9. The offset calibration circuit according to claim 8, wherein The working mode of the offset calibration circuit is as follows: when the calibration mode is enabled, if the output of one path is ahead of the output of the other path, the binary control code corresponding to the ahead path is increased by 1, so as to increase the capacitance of the ahead path; if the output of one path lags behind the output of the other path, the binary control code corresponding to the lagging path is decreased by 1, so as to decrease the capacitance of the lagging path.

10. A chip, characterized in that, It includes a high-gain time amplifier without dead zone as described in any one of claims 1-7, and / or an offset calibration circuit as described in any one of claims 8-10.

11. An electronic device, characterized in that, It includes the chip as described in claim 10.

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