Multistage operational amplifier and integrated chip

Abstract

The invention discloses a multi-stage operational amplifier and an integrated chip, and the multi-stage operational amplifier comprises at least one amplifier branch, and each amplifier branch at least comprises two amplifiers; comprising two amplifier branches, and when each amplifier branch comprises at least two amplifiers, the two amplifier branches at least comprise one common amplifier; the multi-stage operational amplifier further comprises a plurality of Miller capacitors, capacitance values of the Miller capacitors are determined according to a feedback capacitance calculation model, and the feedback capacitance calculation model is determined according to an equivalent multi-stage operational amplifier model corresponding to the multi-stage operational amplifier.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuit technologies, and in particular, to a multi-stage operational amplifier and an integrated chip. Background Art

[0002] In the design of general operational amplifiers, considering factors such as area, power consumption, and accuracy, the DC gain is not very high, generally around 80 dB, and the load capacitance of the operational amplifier is also within 10 pF. However, in some scenarios with higher accuracy requirements, the gain often needs to be above 100 dB. In the existing design methods of operational amplifiers, increasing the gain requires consuming more area and power, and the stability and load-carrying capacity of the operational amplifier have not been substantially improved.

[0003] Based on the above, there is a need for an amplifier circuit and a design method that can optimize the stability and load-carrying capacity of the operational amplifier while increasing the gain of the operational amplifier. Summary of the Invention

[0004] The present invention provides a multi-stage operational amplifier and an integrated chip to achieve the purpose of improving the load-carrying capacity of the multi-stage operational amplifier, improving stability, and reducing the difficulty of selecting Miller capacitors.

[0005] In a first aspect, an embodiment of the present invention provides a multi-stage operational amplifier, including: at least one amplifier branch, and each amplifier branch includes at least two amplifiers;

[0006] When there are two such amplifier branches and each amplifier branch includes at least two amplifiers, the two amplifier branches include at least one common amplifier;

[0007] It further includes a plurality of Miller capacitors, and the capacitance value of the Miller capacitor is determined according to a feedback capacitance calculation model, and the feedback capacitance calculation model is determined according to an equivalent multi-stage operational amplifier model corresponding to the multi-stage operational amplifier.

[0008] Optionally, it includes a first amplifier, a second amplifier, and a third amplifier;

[0009] A signal input terminal is connected to the input terminal of the first amplifier, and the first amplifier is connected to the input terminal of the third amplifier through the second amplifier;

[0010] The output terminal of the third amplifier is connected to a signal output terminal;

[0011] The Miller capacitors include a first capacitor and a second capacitor;

[0012] The first capacitor is connected in parallel between the input terminal and the output terminal of the third amplifier, and the second capacitor is connected in parallel between the input terminal of the second amplifier and the output terminal of the third amplifier;

[0013] The capacitance values of the first capacitor and the second capacitor are determined according to a first feedback capacitor calculation model, and the first feedback capacitor calculation model is determined according to a first equivalent multi-stage operational amplifier model.

[0014] Optionally, it includes a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier;

[0015] The first amplifier, the second amplifier, and the third amplifier form a first amplifier branch, and the fourth amplifier and the third amplifier form a second amplifier branch;

[0016] The signal input terminal is connected to the input terminal of the first amplifier, and the first amplifier is connected to the input terminal of the third amplifier through the second amplifier;

[0017] The signal input terminal is also connected to the input terminal of the fourth amplifier, and the output terminal of the fourth amplifier is connected to the input terminal of the third amplifier;

[0018] The Miller capacitor includes a first Miller capacitor, a second Miller capacitor, and a third Miller capacitor;

[0019] The first Miller capacitor is connected in parallel between the input terminal and the output terminal of the third amplifier, and the second Miller capacitor is connected in parallel between the input terminal of the second amplifier and the output terminal of the third amplifier;

[0020] The third Miller capacitor is connected in parallel between the input terminal of the second amplifier and the output terminal of the third amplifier;

[0021] The capacitance values of the first Miller capacitor, the second Miller capacitor, and the third Miller capacitor are determined according to a second feedback capacitor calculation model, and the second feedback capacitor calculation model is determined according to a second equivalent multi-stage operational amplifier model;

[0022] It further includes a fourth capacitor and a fifth capacitor, and the fourth capacitor and the fifth capacitor are respectively connected to the first input terminal of the second amplifier.

[0023] Optionally, the first amplifier is further configured with a chopping unit.

[0024] Optionally, between the first amplifier and the second amplifier, a filtering unit is further configured after the chopping unit.

[0025] Optionally, the form of the first feedback capacitor calculation model is:

[0026]

[0027] In the formula, g0V′ mdenotes the first equivalent current, g1V1 denotes the second equivalent current, g2V2 denotes the third equivalent current, V1 denotes the first node voltage, V2 denotes the second node voltage, V out denotes the output voltage, R′0 denotes the first equivalent resistance, R′1 the second equivalent resistance, R′2 denotes the third equivalent resistance, C m1 denotes the first capacitor, C m2 denotes the second capacitor, s denotes the Laplace transform.

[0028] Optionally, the form of the second feedback capacitor calculation model is:

[0029]

[0030] C x = C1

[0031] C y = C 2a + C 2b

[0032] In the formula, g0V in denotes the fourth equivalent current, g4V in denotes the fifth equivalent current, g2V1 denotes the sixth equivalent current, g3V2 denotes the seventh equivalent current, R1 denotes the second equivalent resistance, R2 denotes the third equivalent resistance, R3 denotes the fourth equivalent resistance, V1 denotes the first node voltage, V2 denotes the second node voltage, V out denotes the output voltage, C 10 denotes the first Miller capacitor, C 2a denotes the second Miller capacitor, C 2b denotes the third Miller capacitor, C2 denotes the third equivalent capacitor, C3 denotes the fourth equivalent capacitor, C4 denotes the fifth equivalent capacitor, s denotes the Laplace transform.

[0033] Optionally, the filtering unit adopts a notch filter.

[0034] Optionally, the multi-stage operational amplifier is used to adapt to a 100 pF load capacitor.

[0035] In a second aspect, an embodiment of the present invention further provides an integrated chip, including any multi-stage operational amplifier described in the embodiments of the present invention.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a multi-stage operational amplifier, which includes one or more amplifier branches and multiple Miller capacitors. Among them, the Miller capacitors are configured to be directly determined by calculation. Based on the multi-Miller capacitor structure and the capacitance values of the directly determined Miller capacitors, it can be determined through testing that the multi-stage operational amplifier has a high load-carrying capacity, and the load capacitor adapted to the multi-stage operational amplifier can be greater than 10 pF. In addition, by directly determining the capacitance values of the Miller capacitors through calculation, the method of selecting Miller capacitors by simulation can be avoided, and complex simulation condition design can be avoided, thereby reducing the difficulty of selecting Miller capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram of the structure of the multi-stage operational amplifier in the embodiment;

[0038] Figure 2 is a schematic diagram of another structure of the multi-stage operational amplifier in the embodiment;

[0039] Figure 3 is a schematic diagram of yet another structure of the multi-stage operational amplifier in the embodiment;

[0040] Figure 4 is the first equivalent multi-stage operational amplifier model in the embodiment;

[0041] Figure 5 is another first equivalent multi-stage operational amplifier model in the embodiment;

[0042] Figure 6 is a schematic diagram of yet another structure of the multi-stage operational amplifier in the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that only parts related to the present invention are shown in the drawings for the convenience of description, rather than all structures.

[0044] Embodiment 1

[0045] This embodiment provides a multi-stage operational amplifier, including: at least one amplifier branch, and each amplifier branch includes at least two amplifiers;

[0046] When there are two said amplifier branches and each said amplifier branch includes at least two amplifiers, the two said amplifier branches include at least one common amplifier;

[0047] It further includes a plurality of Miller capacitors, the capacitance values of the Miller capacitors are determined according to a feedback capacitance calculation model, and the feedback capacitance calculation model is determined according to an equivalent multi-stage operational amplifier model corresponding to the multi-stage operational amplifier.

[0048] In this embodiment, the specific design method of the multi-stage operational amplifier structure is not limited.

[0049] Figure 1 is a schematic diagram of the multi-stage operational amplifier structure in the embodiment. For example, the multi-stage operational amplifier structure can be as Figure 1 shown;

[0050] Figure 1 In the scheme shown, it includes an amplifier branch formed by connecting amplifier gm0, amplifier gm1, and amplifier gm2 in series. Among them, capacitor Cm1 and capacitor Cm2 are configured as Miller capacitors;

[0051] Figure 2 is another schematic diagram of the multi-stage operational amplifier structure in the embodiment. Or, the multi-stage operational amplifier structure can be as Figure 2 shown;

[0052] Figure 2 In the scheme shown, it includes an amplifier branch formed by amplifier gm1 and amplifier -gm2, and another amplifier branch formed by amplifier -gf. The two amplifier branches are in parallel. Among them, capacitor Cm is configured as a Miller capacitor;

[0053] Figure 3 is yet another schematic diagram of the multi-stage operational amplifier structure in the embodiment. Or, the multi-stage operational amplifier structure can be as Figure 3 shown;

[0054] Figure 3 In the scheme shown, it includes an amplifier branch formed by amplifier gm1, amplifier gm2, and amplifier gm3, and another amplifier branch formed by amplifier gm4 and amplifier gm3. Among them, amplifier gm3 is a shared amplifier, and capacitor C1, capacitor C2a, and capacitor C2b are configured as Miller capacitors.

[0055] In this embodiment, determining the equivalent multi-stage operational amplifier model corresponding to the multi-stage operational amplifier can be to replace the amplifier with an equivalent impedance device. Among them, the equivalent impedance device can include current sources, resistors, capacitors, etc.

[0056] In this embodiment, determining the feedback capacitance calculation model according to the equivalent multi-stage operational amplifier model can be: determining a specified current loop according to the equivalent multi-stage operational amplifier model, and constructing a feedback capacitance calculation model based on the current correspondence relationship of the specified nodes of the current loop;

[0057] Among them, the feedback capacitance calculation model can be a system of equations including multiple equations. According to the actual design situation, one equation can include one or more Miller capacitance parameters.

[0058] In this embodiment, the method for solving the feedback capacitance calculation model is not limited, and the model can be solved by a selected method according to the actual calculation requirements.

[0059] This embodiment provides a multi-stage operational amplifier, which includes one or more amplifier branches and multiple Miller capacitors. Among them, the Miller capacitors are configured to be directly determined by calculation. Based on the multi-Miller capacitor structure and the capacitance values of the directly determined Miller capacitors, it can be determined through testing that the multi-stage operational amplifier has a high load-carrying capacity. The load capacitance adapted to the multi-stage operational amplifier can be greater than 10 pF. In addition, by directly determining the capacitance values of the Miller capacitors through calculation, the method of selecting Miller capacitors by simulation can be avoided, and complex simulation condition design can be avoided, thereby reducing the difficulty of selecting Miller capacitors.

[0060] Reference Figure 1 , in an implementable solution, it is set that the multi-stage operational amplifier includes a first amplifier gm0, a second amplifier gm1, and a third amplifier gm2;

[0061] The signal input terminal Vin is connected to the input terminal of the first amplifier gm0, and the first amplifier gm0 is connected to the input terminal of the third amplifier gm2 through the second amplifier gm1;

[0062] The output terminal of the third amplifier gm2 is connected to the signal output terminal Vout;

[0063] The Miller capacitors include a first capacitor Cm1 and a second capacitor Cm2;

[0064] The first capacitor Cm1 is connected in parallel between the input terminal and the output terminal of the third amplifier gm2, and the second capacitor Cm2 is connected in parallel between the input terminal of the second amplifier gm1 and the output terminal of the third amplifier gm2;

[0065] The capacitance values of the first capacitor Cm1 and the second capacitor Cm2 are determined according to the first feedback capacitance calculation model, and the first feedback capacitance calculation model is determined according to the first equivalent multi-stage operational amplifier model.

[0066] Figure 4 is the first equivalent multi-stage operational amplifier model in the embodiment. Reference Figure 4 , in this solution, the first equivalent multi-stage operational amplifier model includes an equivalent current source and an equivalent impedance;

[0067] Based on this first equivalent multi-stage operational amplifier model, the form of the first feedback capacitance calculation model is:

[0068]

[0069] where g0V′ m represents the first equivalent current, g1V1 represents the second equivalent current, g2V2 represents the third equivalent current, V1 represents the first node voltage, V2 represents the second node voltage, and V out represents the output voltage, R′0 represents the first equivalent impedance, R′1 represents the second equivalent impedance, R′2 represents the third equivalent impedance, and C m1 represents the first capacitor, and C m2 represents the second capacitor, and s represents the Laplace transform.

[0070] Figure 5 is another first equivalent multi-stage operational amplifier model in the embodiment. Refer to Figure 5 , and on the basis of the solution shown in Figure 4 , the first equivalent impedance R′0, the second equivalent impedance R′1, and the third equivalent impedance R′2 are respectively represented by the following formulas:

[0071]

[0072] where R0 represents the first equivalent resistance, R1 represents the second equivalent resistance, R2 represents the third equivalent resistance, C0 represents the first equivalent capacitance, C1 represents the second equivalent capacitance, and C2 represents the third equivalent capacitance.

[0073] In this solution, the capacitance values or capacitance value ranges of the first capacitor Cm1 and the second capacitor Cm2 are determined by solving the first feedback capacitance calculation model. Among them, the values of the aforementioned equivalent resistances and equivalent capacitances are determined according to the design parameters of each amplifier.

[0074] Figure 6 is another structural schematic diagram of a multi-stage operational amplifier in the embodiment. Refer to Figure 6 , and in an implementable solution, the multi-stage operational amplifier includes a first amplifier gm1, a second amplifier gm2, a third amplifier gm3, and a fourth amplifier gm4;

[0075] The first amplifier gm1, the second amplifier gm2, and the third amplifier gm3 form a first amplifier branch, and the fourth amplifier gm4 and the third amplifier gm3 form a second amplifier branch;

[0076] The signal input terminals (VIN, VIP) are connected to the input terminal of the first amplifier gm1, and the first amplifier gm1 is connected to the input terminal of the third amplifier gm3 through the second amplifier gm2;

[0077] The signal input terminals (VIN, VIP) are also connected to the input terminal of the fourth amplifier gm4, and the output terminal of the fourth amplifier gm4 is connected to the input terminal of the third amplifier gm3;

[0078] The Miller capacitors include a first Miller capacitor C10, a second Miller capacitor C2a, and a third Miller capacitor C2b;

[0079] The first Miller capacitor C10 is connected in parallel between the input terminal and the output terminal of the third amplifier, and the second Miller capacitor C2a is connected in parallel between the input terminal of the second amplifier and the output terminal of the third amplifier;

[0080] The third Miller capacitor C2b is connected in parallel between the input terminal of the second amplifier gm2 and the output terminal of the third amplifier gm3;

[0081] The capacitance values of the first Miller capacitor C10, the second Miller capacitor C2a, and the third Miller capacitor C2b are determined according to the second feedback capacitor calculation model, and the second feedback capacitor calculation model is determined according to the second equivalent multi-stage operational amplifier model;

[0082] It further includes a fourth capacitor C3a and a fifth capacitor C3b, and the fourth capacitor C3a and the fifth capacitor C3b are respectively connected to the first input terminal of the second amplifier gm2.

[0083] Exemplarily, in this solution, the determination method of the second equivalent multi-stage operational amplifier model is the same as that of the first equivalent multi-stage operational amplifier model corresponding to the multi-stage operational amplifier shown in Figure 1 and its specific circuit structure will not be elaborated further.

[0084] In this solution, the form of the second feedback capacitor calculation model is:

[0085]

[0086] C x = C 10

[0087] C y = C 2a + C 2b

[0088] In the formula, g0V in represents the fourth equivalent current, g4V in represents the fifth equivalent current, g2V1 represents the sixth equivalent current, g3V2 represents the seventh equivalent current, R1 represents the second equivalent resistance, R2 represents the third equivalent resistance, R3 represents the fourth equivalent resistance, V1 represents the first node voltage, V2 represents the second node voltage, V outVout represents the output voltage, C2 represents the third equivalent capacitance, C3 represents the fourth equivalent capacitance, C4 represents the fifth equivalent capacitance, and s represents the Laplace transform.

[0089] In this solution, based on Figure 6 the configuration of the multi-stage operational amplifier shown, its transfer function can also be determined as:

[0090]

[0091] In the above formula, the parameters b0, b1, b2, a0, a1, a2, and a3 are respectively represented by the following formulas:

[0092] b0 = -g1g2g3R1R2R4

[0093] b1 = R1R2R4(C x g1g2 - C y g3g4)

[0094] b2 = R1R2R4C x C y (g1 + g4)

[0095] a0 = -R2 - R4

[0096] a1 = -g3R2R3R4C y g2R1

[0097] a2 = R1R2R3R4(C x C y g2 - C1C x g3 - C x C y g3)

[0098] a3 = -R1R2R3R4C x C y (C1 + C2 + C3 + C4)

[0099] In the formula, R1 represents the second equivalent resistance, R2 represents the third equivalent resistance, R3 represents the fourth equivalent resistance, R4 represents the fifth equivalent resistance, g1 represents the first amplifier parameter, g2 represents the second amplifier parameter, g3 represents the third amplifier parameter, and g4 represents the fourth amplifier parameter.

[0100] In this solution, according to the transfer function, the zero-point expression of this multi-stage operational amplifier can be determined as:

[0101]

[0102] In this solution, according to the transfer function, the pole expressions of this multi-stage operational amplifier can be determined to include:

[0103]

[0104] In this solution, a second amplifier branch is formed based on the fourth amplifier gm4 and the third amplifier gm3, which can provide an additional zero for the multi-stage operational amplifier (system). Based on the aforementioned zero expression, this branch can provide a left-half plane zero for the system and can provide a +90° phase.

[0105] By adjusting the magnitude of the fourth amplifier gm4, the frequency point of this zero can be correspondingly adjusted, and the zero is adjusted to a frequency point close to the sub-dominant pole of the operational amplifier (system), thereby canceling the -90° phase of the sub-dominant pole, and thus forming compensation.

[0106] In this solution, to ensure the stability of the multi-stage operational amplifier (system), the above poles are set to satisfy the following conditions:

[0107] |W p2 | << |W p3 |

[0108] Based on the above conditions, it can be deduced that to ensure the stability of the multi-stage operational amplifier (system), the relationship between the second amplifier gm2 and the third amplifier gm3 is:

[0109] g2 < g3

[0110] In this solution, by combining the pole expression, the second feedback capacitance calculation model, and the above limiting conditions, when the numerical values of the specified poles W p2 and pole W p3 are given, the numerical values or numerical ranges of the first Miller capacitance C10, the second Miller capacitance C2a, and the third Miller capacitance C2b can be obtained.

[0111] In this solution, the first Miller capacitance C10, the second Miller capacitance C2a, and the third Miller capacitance C2b determined by the above steps can make the multi-stage operational amplifier adapt to a 100 pF load capacitance.

[0112] Referring to Figure 6 , in an implementable solution, the first amplifier gm1 is further configured with a chopper unit 100.

[0113] Exemplarily, in this solution, the chopper unit 100 (chopper) is configured to eliminate the offset voltage from the input end to the output end of the operational amplifier and to eliminate the flicker noise in the multi-stage operational amplifier system.

[0114] Referring to Figure 6 , in an implementable solution, a filter unit 200 is further configured between the first amplifier gm1 and the second amplifier gm2 after the chopper unit 100.

[0115] In this solution, a filtering unit 200 is configured to achieve a certain degree of suppression of the frequency points of the filtering unit 200 and to eliminate the noise jitter of the output signal of a specified operational amplifier.

[0116] Furthermore, in an implementable solution, the filtering unit adopts a notch filter.

[0117] Based on the foregoing solution, referring to Figure 6 , in an implementable solution, the multi-stage operational amplifier includes:

[0118] A first amplifier gm1, a second amplifier gm2, a third amplifier gm3, and a fourth amplifier gm4;

[0119] The first amplifier gm1, the second amplifier gm2, and the third amplifier gm3 form a first amplifier branch, and the fourth amplifier gm4 and the third amplifier gm3 form a second amplifier branch;

[0120] The signal input terminals (VIN, VIP) are connected to the input terminal of the first amplifier gm1, and the first amplifier gm1 is connected to the input terminal of the third amplifier gm3 through the second amplifier gm2;

[0121] The signal input terminals (VIN, VIP) are also connected to the input terminal of the fourth amplifier gm4, and the output terminal of the fourth amplifier gm4 is connected to the input terminal of the third amplifier gm3;

[0122] The Miller capacitors include a first Miller capacitor C10, a second Miller capacitor C2a, and a third Miller capacitor C2b;

[0123] The first Miller capacitor C10 is connected in parallel between the input terminal and the output terminal of the third amplifier, and the second Miller capacitor C2a is connected in parallel between the input terminal of the second amplifier and the output terminal of the third amplifier;

[0124] The third Miller capacitor C2b is connected in parallel between the input terminal of the second amplifier gm2 and the output terminal of the third amplifier gm3;

[0125] It further includes a fourth capacitor C3a and a fifth capacitor C3b, and the fourth capacitor C3a and the fifth capacitor C3b are respectively connected to the first input terminal of the second amplifier gm2;

[0126] The first amplifier gm1 is also configured with a chopping unit 100, and a filtering unit 200 is also configured after the chopping unit 100 between the first amplifier gm1 and the second amplifier gm2.

[0127] In this solution, the capacitance value ranges of the first Miller capacitor C10, the second Miller capacitor C2a, and the third Miller capacitor C2b are determined based on the second feedback capacitance calculation model and the transfer function of the operational amplifier.

[0128] In this solution, based on the structure of the multi-stage operational amplifier and the selected Miller capacitors, the static power consumption of the multi-stage operational amplifier can be 400 μA, the DC gain can be 180 dB, and it can adapt to a load capacitance of 100 pF. The multi-stage budget amplifier proposed in this solution has low power consumption, high gain, strong stability, and high load-carrying capacity.

[0129] Embodiment 2

[0130] This embodiment provides an integrated chip, including any one of the multi-stage operational amplifiers described in Embodiment 1. The implementation manners and beneficial effects of the multi-stage operational amplifier are the same as the corresponding contents described in Embodiment 1, and the specific contents will not be elaborated here.

[0131] Note that the above is only the preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-stage operational amplifier, characterized in that, Comprising: At least one amplifier branch, each amplifier branch including at least two amplifiers; When there are two of the amplifier branches and each of the amplifier branches includes at least two amplifiers, the two amplifier branches include at least one common amplifier; Further comprising a plurality of Miller capacitors, the capacitance values of the Miller capacitors being determined according to a feedback capacitance calculation model, the feedback capacitance calculation model being determined according to an equivalent multi-stage operational amplifier model corresponding to a multi-stage operational amplifier.

2. The multi-stage operational amplifier according to claim 1, wherein Including a first amplifier, a second amplifier, and a third amplifier; A signal input terminal is connected to an input terminal of the first amplifier, and the first amplifier is connected to an input terminal of the third amplifier through the second amplifier; An output terminal of the third amplifier is connected to a signal output terminal; The Miller capacitors include a first capacitor and a second capacitor; The first capacitor is connected in parallel between an input terminal and an output terminal of the third amplifier, and the second capacitor is connected in parallel between an input terminal of the second amplifier and an output terminal of the third amplifier; The capacitance values of the first capacitor and the second capacitor are determined according to a first feedback capacitance calculation model, the first feedback capacitance calculation model being determined according to a first equivalent multi-stage operational amplifier model.

3. The multi-stage operational amplifier according to claim 1, wherein Including a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier; The first amplifier, the second amplifier, and the third amplifier form a first amplifier branch, and the fourth amplifier and the third amplifier form a second amplifier branch; A signal input terminal is connected to an input terminal of the first amplifier, and the first amplifier is connected to an input terminal of the third amplifier through the second amplifier; The signal input terminal is further connected to an input terminal of the fourth amplifier, and an output terminal of the fourth amplifier is connected to an input terminal of the third amplifier; The Miller capacitors include a first Miller capacitor, a second Miller capacitor, and a third Miller capacitor; The first Miller capacitor is connected in parallel between an input terminal and an output terminal of the third amplifier, and the second Miller capacitor is connected in parallel between an input terminal of the second amplifier and an output terminal of the third amplifier; The third Miller capacitor is connected in parallel between an input terminal of the second amplifier and an output terminal of the third amplifier; The capacitance values of the first Miller capacitor, the second Miller capacitor, and the third Miller capacitor are determined according to a second feedback capacitance calculation model, the second feedback capacitance calculation model being determined according to a second equivalent multi-stage operational amplifier model; Further comprising a fourth capacitor and a fifth capacitor, the fourth capacitor and the fifth capacitor are respectively connected to a first input terminal of the second amplifier.

4. The multi-stage operational amplifier according to claim 3, wherein, The first amplifier is further configured with a chopping unit.

5. The multi-stage operational amplifier according to claim 4, wherein Between the first amplifier and the second amplifier, a filtering unit is further configured after the chopping unit.

6. The multi-stage operational amplifier according to claim 2, wherein The form of the first feedback capacitance calculation model is: where, g0V′ m represents the first equivalent current, g1V1 represents the second equivalent current, g2V2 represents the third equivalent current, V1 represents the first node voltage, V2 represents the second node voltage, V out represents the output voltage, R′0 represents the first equivalent impedance, R′1 represents the second equivalent impedance, R′2 represents the third equivalent impedance, C m1 represents the first capacitor, C m2 represents the second capacitor, and s represents the Laplace transform.

7. The multi-stage operational amplifier according to claim 3, wherein The form of the second feedback capacitance calculation model is: C x = C 10 C y = C 2a + C 2b where, g0V in represents the fourth equivalent current, g4V in represents the fifth equivalent current, g2V1 represents the sixth equivalent current, g3V2 represents the seventh equivalent current, R1 represents the second equivalent resistance, R2 represents the third equivalent resistance, R3 represents the fourth equivalent resistance, V1 represents the first node voltage, V2 represents the second node voltage, V out represents the output voltage, C 10 represents the first Miller capacitance, C 2a represents the second Miller capacitance, C 2b represents the third Miller capacitance, C2 represents the third equivalent capacitance, C3 represents the fourth equivalent capacitance, C4 represents the fifth equivalent capacitance, s represents the Laplace transform.

8. The multi-stage operational amplifier according to claim 5, characterized in that, The filtering unit uses a notch filter.

9. The multi-stage operational amplifier according to claim 3, wherein, The multi-stage operational amplifier is used to adapt to a 100 pF load capacitance.

10. An integrated chip, characterized in that, Including the multi-stage operational amplifier according to any one of claims 1 to 9.

Images