Automatic power calibration device based on FPGA

Abstract

The invention provides automatic power calibration equipment based on an FPGA (Field Programmable Gate Array), and relates to the technical field of automatic power calibration. Comprising a power amplifier module and an output antenna, the power detection module is in signal connection with the output end of the power amplification module and is used for acquiring a digital signal corresponding to the actual output power of the power amplification module; the calibration control module is electrically connected with the power amplification module and the power detection module and is used for receiving the digital signal corresponding to the actual output power output by the power detection module, obtaining the actual output power of the power amplification module according to the digital signal, comparing according to a preset reference value of the output power of the power amplification module in a built-in current environment, and outputting the actual output power of the power amplification module. When the comparison result has deviation, an adjusting instruction is generated; and the adjusting module is electrically connected with the power amplifier module and the calibration control module and is used for receiving the adjusting instruction output by the calibration control module and adjusting the working state of the power amplifier module.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic power calibration, and particularly to an automatic power calibration device based on FPGA. Background Art

[0002] Power amplifiers are key components in wireless communication devices, audio systems, and other electronic devices, and their performance directly affects the signal quality of device operation. In practical applications, the power amplifier module is affected by factors such as the input power of the front end, load, and supply voltage, and is prone to deviation, resulting in a decline in system performance.

[0003] Traditional power amplifier modules rely on manual adjustment or simple automatic gain control (AGC) to calibrate the output power, but these methods often cannot respond to environmental changes in real time, or require complex manual operations and are difficult to meet the requirements of high precision and high reliability. Existing means are difficult to ensure reliable transmission of power amplifiers in different environments and during fast frequency modulation.

[0004] Therefore, it is very necessary to develop an automatic power calibration device based on FPGA, which can automatically obtain the output power situation of the current power amplifier according to environmental changes and perform targeted adjustment to meet the reliability use requirements of the power amplifier in a changing environment. Summary of the Invention

[0005] In view of this, the present invention proposes an automatic power calibration device based on FPGA, which realizes output power correction by sampling the output power of the power amplifier, calculating the deviation degree between the theoretical value and the actual value of the output power of the power amplifier module through a preset algorithm, and adjusting the output gain.

[0006] The present invention provides an automatic power calibration device based on FPGA, including a power amplifier module and an output antenna arranged in sequence; further including:

[0007] A power detection module, signal-connected to the output end of the power amplifier module, for obtaining a digital signal corresponding to the actual output power of the power amplifier module;

[0008] A calibration control module, electrically connected to the power amplifier module and the power detection module respectively, for receiving the digital signal corresponding to the actual output power output by the power detection module, obtaining the actual output power of the power amplifier module according to the digital signal, comparing it with a preset reference value of the output power of the power amplifier module in the current environment built in, and generating an adjustment instruction when there is a deviation in the comparison result;

[0009] An adjustment module, electrically connected to the power amplifier module and the calibration control module respectively, for receiving the adjustment instruction output by the calibration control module and adjusting the working state of the power amplifier module.

[0010] Based on the above technical solutions, preferably, the power detection module includes a directional coupler, a detector, and an analog-to-digital converter arranged in sequence; the input end of the directional coupler serves as the input end of the power detection module and is electrically connected to the output end of the power amplifier module, and the output end of the directional coupler is electrically connected to the input end of the output antenna; the coupling end of the directional coupler is electrically connected to the input end of the detector, the output end of the detector is electrically connected to the input end of the analog-to-digital converter, and the output end of the mode converter serves as the output end of the power detection module and is electrically connected to the input end of the calibration control module; the directional coupler is used to couple and output the time-domain waveform output by the power amplifier module, the detector converts the input time-domain waveform into an analog voltage signal and sends the analog signal into the analog-to-digital converter; the analog-to-digital converter converts the input analog voltage signal into a digital level and inputs it into the calibration control module.

[0011] Preferably, the calibration control module includes an FPGA and a memory, and the FPGA is communicatively connected to the memory; on the one hand, the FPGA obtains the preset reference value of the output power of the power amplifier module in the current environment, and on the other hand, the FPGA estimates the actual output power of the power amplifier module in the current environment according to the average value of the digital levels input by the analog-to-digital converter, and compares the preset reference value of the output power of the power amplifier module in the current environment with the actual output power of the power amplifier module; according to the difference between the preset reference value of the output power and the actual output power, different adjustment instructions are output to the adjustment module; the memory is used to store the preset reference value of the output power of the power amplifier module in the current environment and the record of the corresponding historical adjustment instructions; the FPGA also provides a drive voltage signal to the power amplifier module.

[0012] Further preferably, when the FPGA obtains the preset reference value of the output power of the power amplifier module in the current environment, it respectively obtains that the gain of the power amplifier module corresponding to the current environment is G, the drive voltage signal supplied by the FPGA to the power amplifier module is V in , the load impedance is R L , the output efficiency η of the power amplifier module, the designed frequency f0 and the actual output frequency f of the power amplifier module, the temperature influence coefficient α, the frequency attenuation coefficient β, and the operating temperature T, and constructs a calculation model for the preset reference value PS of the output power of the power amplifier module in the current environment: where T0 is the reference temperature.

[0013] Even more preferably, the value range of the temperature influence coefficient α is [10 -5 , 10 -2 , and the value range of the frequency attenuation coefficient β is [-1, +1].

[0014] More preferably, the FPGA estimates the actual output power of the power amplifier module in the current environment according to the average value of the digital levels input by the analog-to-digital converter, by setting the average value of the digital levels input by the analog-to-digital converter as V coup , and the coupling coefficient of the directional coupler is C coup , then the output voltage V out1 of the power amplifier module in the current environment is estimated as Then the actual output power P1 of the power amplifier module in the current environment is estimated as The average value V of the digital levels coup is obtained by averaging the digital levels obtained in several odd-numbered consecutive sampling periods.

[0015] Even more preferably, according to the difference between the preset reference value of the output power and the deviation of the actual output power, different adjustment instructions are output to the adjustment module, by comparing the magnitude relationship between the preset reference value PS of the output power of the power amplifier module and the actual output power P1 of the power amplifier module in the current environment:

[0016] 1) When at least three consecutive sampling periods all satisfy P1 < PS - h, where h is the preset power redundancy value, the FPGA makes the adjustment module maintain the current adjustment parameters unchanged, and reports an alarm signal to prompt the maintenance personnel to conduct a check;

[0017] 2) When at least three consecutive sampling periods all satisfy P1 > PS + h, the FPGA cuts off the voltage signal provided to the power amplifier module, the FPGA makes the adjustment module maintain the current adjustment parameters unchanged, and reports an alarm signal to prompt the maintenance personnel to conduct a check;

[0018] 3) When at least three consecutive sampling periods all satisfy PS - h ≤ P1 ≤ PS + h, one or more gain calibrations are performed according to the degree of deviation. The maximum adjustment step for each gain calibration is np, where p is the minimum step gain per time and n is the maximum step size for each gain calibration, and np < h. When performing each gain calibration, first determine whether the relational expression PS - p ≤ P1 ≤ PS + p is satisfied. If it is satisfied, the FPGA control adjustment module adjusts the power according to the minimum step gain p. If it is not satisfied, add a minimum step gain and determine whether the relational expression PS - 2p ≤ P1 ≤ PS + 2p is satisfied. If it is satisfied, the FPGA control adjustment module adjusts the power according to the step gain 2p. If it is not satisfied, add a minimum step gain and determine whether the relational expression PS - 3p ≤ P1 ≤ PS + 3p is satisfied, and so on, until the maximum step np for a single gain calibration is reached. At this time, regardless of whether PS - np ≤ P1 ≤ PS + np is satisfied, the FPGA controls the adjustment module to adjust the power according to the maximum adjustment step np to complete one gain calibration. Then the power detection module re - obtains the actual output power P1 of the current power amplifier module and performs the second - round gain calibration again, and re - determines whether the relational expression PS - p ≤ P1 ≤ PS + p is satisfied, repeating the content of 3) until the gain calibration is completed.

[0019] Further preferably, the value of the minimum step gain p per time is 0.1 - 0.25 dB.

[0020] Further preferably, the maximum step size n for each gain calibration is n ≤ 20.

[0021] Further preferably, the adjustment module is a digital - controlled attenuator, and the value of the minimum step gain p per time is the minimum resolution of the digital - controlled attenuator.

[0022] An FPGA - based automatic power calibration device provided by the present invention has the following beneficial effects compared with the prior art:

[0023] (1) Through the power detection module, the present invention obtains a coupled signal proportional to the output power, which is fed back to the FPGA through waveform conversion and analog - to - digital conversion. The FPGA calculates the preset reference value and the actual power of the output power of the power amplifier module through the built - in comparison and calculation method, compares the magnitudes of the two, and executes different adjustment instructions accordingly, prompting the maintenance personnel to troubleshoot faults, or performing gain calibration in a loop according to the preset step size to correct the output power, ensuring that the power amplifier module operates stably with as little influence from environmental changes as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 It is a structural block diagram of an automatic power calibration device based on FPGA of the present invention;

[0026] Figure 2 It is a flowchart of power calibration for an automatic power calibration device based on FPGA of the present invention;

[0027] Figure 3 It is a flowchart of power calibration for an embodiment of an automatic power calibration device based on FPGA of the present invention. Specific embodiments

[0028] The following will describe the technical solutions in the embodiments of the present invention clearly and completely in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0029] Traditional power amplifier modules rely on manual adjustment or simple automatic gain control (AGC) to calibrate the output power. However, these methods often cannot respond to environmental changes in real time, or require complex manual operations and are difficult to meet the requirements of high precision and high reliability. In view of this, in order to ensure the long-term stable operation of the power module, the present invention provides an automatic power calibration device based on FPGA, including a power amplifier module and an output antenna arranged in sequence; further including:

[0030] A power detection module, signal-connected to the output end of the power amplifier module, for obtaining a digital signal corresponding to the actual output power of the power amplifier module;

[0031] A calibration control module, electrically connected to the power amplifier module and the power detection module respectively, for receiving the digital signal corresponding to the actual output power output by the power detection module, obtaining the actual output power of the power amplifier module according to the digital signal, comparing it with a preset reference value of the output power of the power amplifier module in the current environment built in, and generating an adjustment instruction when there is a deviation in the comparison result;

[0032] An adjustment module, electrically connected to the power amplifier module and the calibration control module respectively, for receiving the adjustment instruction output by the calibration control module and adjusting the working state of the power amplifier module.

[0033] First, the power detection module obtains the output sampling signal of the power amplifier module. By processing the radio frequency signal to obtain the corresponding DC signal through amplification and analog-to-digital conversion processing, it can be used for subsequent calculations.

[0034] As Figure 1 shown, the power detection module includes a directional coupler, a detector, and an analog-to-digital converter arranged in sequence; the input end of the directional coupler serves as the input end of the power detection module and is electrically connected to the output end of the power amplifier module, and the output end of the directional coupler is electrically connected to the input end of the output antenna; the coupling end of the directional coupler is electrically connected to the input end of the detector, the output end of the detector is electrically connected to the input end of the analog-to-digital converter, and the output end of the mode converter serves as the output end of the power detection module and is electrically connected to the input end of the calibration control module; the directional coupler is used to couple and output the time-domain waveform output by the power amplifier module, the detector converts the input time-domain waveform into an analog voltage signal and sends the analog signal into the analog-to-digital converter; the analog-to-digital converter converts the input analog voltage signal into a digital level and inputs it into the calibration control module.

[0035] The coupling end of the directional coupler couples and outputs a certain proportion of the output power, such as 1%, and after the detector converts the radio frequency signal into a DC signal, it amplifies the DC signal to increase the amplitude and energy of the signal to meet the input requirements of the analog-to-digital converter. The analog-to-digital converter converts the input DC signal into the corresponding digital level for further processing by the calibration control module.

[0036] As Figure 2 shown, the calibration control module includes an FPGA and a memory, and the FPGA is communicatively connected to the memory; on the one hand, the FPGA obtains the preset reference value of the output power of the power amplifier module in the current environment, and on the other hand, the FPGA estimates the actual output power of the power amplifier module in the current environment according to the average value of the digital levels input by the analog-to-digital converter, and compares the preset reference value of the output power of the power amplifier module in the current environment with the actual output power of the power amplifier module; according to the difference between the preset reference value of the output power and the actual output power, it outputs different adjustment instructions to the adjustment module; the memory is used to store the preset reference value of the output power of the power amplifier module in the current environment and the record of the corresponding historical adjustment instructions; the FPGA also provides a drive voltage signal to the power amplifier module.

[0037] As Figure 1It can be seen that on the one hand, the FPGA drives the power amplifier module to work properly. On the other hand, it drives the digital controlled attenuator to adjust the output gain of the power amplifier module. On the third hand, it receives the feedback signal input by the power detection module, and combines the parameters of the external environment where the current power amplifier module is located to calculate the preset reference value of the output power of the power amplifier module and the actual output power of the power amplifier module in the current environment respectively, providing a numerical reference for the decision-making of subsequent adjustment instructions.

[0038] Among them, when the FPGA obtains the preset reference value of the output power of the power amplifier module in the current environment, it respectively obtains that the gain of the power amplifier module corresponding to the current environment is G, the driving voltage signal supplied by the FPGA to the power amplifier module is V in , the load impedance is R L , the output efficiency η of the power amplifier module, the designed frequency f0 and the actual output frequency f of the power amplifier module, the temperature influence coefficient α, the frequency attenuation coefficient β and the working temperature T, and constructs a calculation model for the preset reference value PS of the output power of the power amplifier module in the current environment: Among them, T0 is the reference temperature. The value range of the temperature influence coefficient α is [10 -5 , 10 -2 , and the value range of the frequency attenuation coefficient β is [-1, +1]. The calculation model of the preset reference value PS of the output power of the power amplifier module in the current environment takes into account the current temperature, reference temperature, output frequency, load impedance, driving voltage signal, and the gain of the current power amplifier module, etc., and obtains the theoretical value of the preset reference value PS under the influence of the current environmental parameters.

[0039] Among them, when the FPGA estimates the actual output power of the power amplifier module in the current environment according to the average value of the digital levels input by the analog-to-digital converter, it makes the average value of the digital levels input by the analog-to-digital converter be V coup , the coupling coefficient of the directional coupler is C coup , then the output voltage V out1 of the power amplifier module in the current environment is estimated to be Then the actual output power P1 of the power amplifier module in the current environment is estimated to be The average value V of the digital levels coup is obtained by averaging the digital levels obtained in a number of odd consecutive sampling periods. The actual output power is obtained by back-calculating the output voltage of the power amplifier module from the input level of the analog-to-digital converter and the load impedance.

[0040] Then, according to the difference between the preset reference value of the output power and the actual output power, the FPGA outputs different adjustment instructions to the adjustment module, which is to compare the magnitude relationship between the preset reference value PS of the output power of the power amplifier module and the actual output power P1 of the power amplifier module in the current environment:

[0041] 1) When at least three consecutive sampling periods all satisfy P1 < PS - h, where h is the preset power redundancy value, the FPGA causes the adjustment module to maintain the current adjustment parameters unchanged and reports an alarm signal to prompt the maintenance personnel to conduct a check; this situation indicates that the power amplifier module has not entered the normal working area for a long time and there may be a fault.

[0042] 2) When at least three consecutive sampling periods all satisfy P1 > PS + h, the FPGA cuts off the voltage signal provided to the power amplifier module, causes the adjustment module to maintain the current adjustment parameters unchanged, and reports an alarm signal to prompt the maintenance personnel to conduct a check; this situation indicates that the power amplifier module has been in the saturation area for a long time. At this time, it is necessary to combine the real-time working temperature T of the power amplifier module to confirm whether it is in the saturation area. If so, it means that the heat of the power amplifier module will continue to accumulate, which may cause the device to burn out. The working state of the power amplifier module should be stopped, and the maintenance personnel should confirm whether the preset reference value PS of the output power is reasonable.

[0043] 3), as Figure 2 shown, when at least three consecutive sampling periods all satisfy PS - h ≤ P1 ≤ PS + h, one or more gain calibrations are performed according to the degree of deviation. The maximum adjustment step of each gain calibration is np, where p is the single minimum step gain and n is the maximum step size of each gain calibration, and np < h; when performing each gain calibration, first judge whether the relationship PS - p ≤ P1 ≤ PS + p is satisfied. If it is satisfied, the FPGA controls the adjustment module to perform power adjustment according to the minimum step gain p. If it is not satisfied, add a minimum step gain and judge whether the relationship PS - 2p ≤ P1 ≤ PS + 2p is satisfied. If it is satisfied, the FPGA controls the adjustment module to perform power adjustment according to the step gain 2p. If it is not satisfied, add a minimum step gain and judge whether the relationship PS - 3p ≤ P1 ≤ PS + 3p is satisfied, and so on, until the maximum step np of a single gain calibration is reached. At this time, regardless of whether PS - np ≤ P1 ≤ PS + np is satisfied, the FPGA controls the adjustment module to perform power adjustment according to the maximum adjustment step np to complete a gain calibration; then the power detection module re-obtains the actual output power P1 of the current power amplifier module and conducts a second-round gain calibration again, and re-judges whether the relationship PS - p ≤ P1 ≤ PS + p is satisfied, repeating the content of 3) until the gain calibration is completed.

[0044] When the external environment changes, the power detection module does not immediately perform the coupling detection of the actual output power, but waits until the environmental change is stable, such as after more than ten sampling periods, and then starts the processes of coupling output, waveform transformation, and analog-to-digital conversion to avoid large fluctuations in sampling data, resulting in excessive sampling deviation.

[0045] The value of the single - time minimum step - by - step gain p is 0.1 - 0.25 dB. The maximum step size n for each gain calibration is ≤ 20. The adjustment module is a digital - controlled attenuator, and the value of the single - time minimum step - by - step gain p is the minimum resolution of the digital - controlled attenuator. During actual operation, if after the step - by - step gain adjustment, the current output power and the preset reference value PS of the output power cannot be exactly equal, but the current power is within the smaller neighborhood range of the preset reference value PS, then the two are regarded as consistent, that is Figure 2 PS ± H in Figure 2 , where H is the smaller neighborhood range of the preset reference value PS.

[0046] Junction attachment Figure 3 , the embodiments of the present invention will be described in detail. Let the value of the single - time minimum step - by - step gain p be 0.25 dB, and the value of H be 0.5 dB. The maximum step size n for each gain calibration is 8; then the maximum adjustment step - by - step np for each gain calibration is 2 dB. Through the current power detection, it is judged whether the initial actual output power P1 meets the range requirement of PS ± 0.5 dB. If it does not meet, then the first step - size adjustment of this round of gain calibration is started, so that the actual output power P1 deviates by ± 0.25 dB, and it is checked whether it meets the situation of PS ± 0.5 dB. If so, the digital - controlled attenuator is adjusted according to 0.25 dB for power adjustment. If not, the second step - size adjustment of this round of gain calibration is continued, so that the actual output power P1 deviates by ± 0.5 dB, and it is checked again whether it meets the situation of PS ± 0.5 dB. If so, the digital - controlled attenuator is adjusted according to 0.5 dB for power adjustment. If not, the third step - size adjustment of this round of gain calibration is continued, and so on, until the maximum step size of this round of gain calibration is reached. If it still does not meet after reaching the maximum step size, the digital - controlled attenuator is adjusted according to the maximum adjustment step - by - step 2 dB for single - time gain calibration for power adjustment, and then jumps to Figure 3 the top of the dashed - line box in Figure 3 . After power detection again, the step - size adjustment and comparison process of a new round of gain calibration are re - executed. Until the actual output power P1 is stabilized within the range of PS ± 0.5 dB, at this time, the adjustment module will pause working, but the power detection module and the control and adjustment module will still continue to work until the environmental parameters of the power amplifier module change and cause a deviation between the preset reference value PS of the output power of the power amplifier module and the actual output power P1 of the power amplifier module in the current environment, and then the adjustment module works again.

[0047] The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An automatic power calibration device based on FPGA, comprising a power amplifier module and an output antenna arranged in sequence; characterized in that, Further included are: a power detection module, signal-connected to the output end of the power amplifier module, for obtaining a digital signal corresponding to the actual output power of the power amplifier module; a calibration control module, electrically connected to the power amplifier module and the power detection module respectively, for receiving the digital signal corresponding to the actual output power output by the power detection module, obtaining the actual output power of the power amplifier module according to the digital signal, comparing it with a preset reference value of the output power of the power amplifier module under the current environment built-in, and generating an adjustment instruction when there is a deviation in the comparison result; an adjustment module, electrically connected to the power amplifier module and the calibration control module respectively, for receiving the adjustment instruction output by the calibration control module and adjusting the working state of the power amplifier module.

2. The automatic power calibration device based on FPGA according to claim 1, wherein The power detection module includes a directional coupler, a detector and an analog-to-digital converter arranged in sequence; the input end of the directional coupler is used as the input end of the power detection module and is electrically connected to the output end of the power amplifier module, the output end of the directional coupler is electrically connected to the input end of the output antenna; the coupling end of the directional coupler is electrically connected to the input end of the detector, the output end of the detector is electrically connected to the input end of the analog-to-digital converter, and the output end of the mode converter is used as the output end of the power detection module and is electrically connected to the input end of the calibration control module; the directional coupler is used for coupling and outputting the time-domain waveform output by the power amplifier module, the detector converts the input time-domain waveform into an analog voltage signal and sends the analog signal into the analog-to-digital converter; The analog-to-digital converter converts the input analog voltage signal into a digital level and inputs it into the calibration control module.

3. The automatic power calibration device based on FPGA according to claim 2, wherein, The calibration control module includes an FPGA and a memory, and the FPGA is communicatively connected to the memory; on the one hand, the FPGA obtains the preset reference value of the output power of the power amplifier module under the current environment, on the other hand, the FPGA estimates the actual output power of the power amplifier module under the current environment according to the average value of the digital levels input by the analog-to-digital converter, and compares the preset reference value of the output power of the power amplifier module under the current environment with the actual output power of the power amplifier module; according to the difference in the deviation between the preset reference value of the output power and the actual output power, different adjustment instructions are output to the adjustment module; the memory is used for storing the preset reference value of the output power of the power amplifier module under the current environment and the record of the corresponding historical adjustment instructions; the FPGA also provides a drive voltage signal to the power amplifier module.

4. An automatic power calibration device based on FPGA according to claim 3, characterized in that The FPGA obtains the preset reference value of the output power of the power amplifier module in the current environment by separately obtaining the gain of the power amplifier module corresponding to the current environment as G, the drive voltage signal supplied by the FPGA to the power amplifier module as V in , the load impedance as R L , the output efficiency η of the power amplifier module, the designed frequency f0 and the actual output frequency f of the power amplifier module, the temperature influence coefficient α, the frequency attenuation coefficient β, and the working temperature T, and constructs a calculation model for the preset reference value PS of the output power of the power amplifier module in the current environment: where T0 is the reference temperature.

5. An automatic power calibration device based on FPGA according to claim 4, characterized in that, The value range of the temperature influence coefficient α is [10 -5 , 10 -2 , and the value range of the frequency attenuation coefficient β is [-1, +1].

6. The automatic power calibration device based on FPGA according to claim 4, characterized in that, The FPGA estimates the actual output power of the power amplifier module in the current environment based on the average value of the digital levels input by the analog-to-digital converter, by setting the average value of the digital levels input by the analog-to-digital converter to V coup , the coupling coefficient of the directional coupler is C coup , then the output voltage V out1 of the power amplifier module in the current environment is estimated to be Then the actual output power P1 of the power amplifier module in the current environment is estimated to be The average value V coup of the digital levels is obtained by averaging the digital levels obtained in a number of consecutive odd sampling periods.

7. An automatic power calibration device based on FPGA according to claim 6, characterized in that, According to the difference in the deviation between the preset reference value of the output power and the actual output power, different adjustment instructions are output to the adjustment module, which is to compare the size relationship between the preset reference value PS of the output power of the power amplifier module and the actual output power P1 of the power amplifier module under the current environment: 1) When at least three consecutive sampling periods all satisfy P1 < PS - h, where h is a preset power redundancy value, the FPGA makes the adjustment module maintain the current adjustment parameters unchanged and reports an alarm signal to prompt the maintenance personnel to conduct a check; 2) When at least three consecutive sampling periods all satisfy P1 > PS + h, the FPGA cuts off the voltage signal provided to the power amplifier module, the FPGA makes the adjustment module maintain the current adjustment parameters unchanged and reports an alarm signal to prompt the maintenance personnel to conduct a check; 3) When at least three consecutive sampling periods all satisfy PS - h ≤ P1 ≤ PS + h, one or more gain calibrations are performed according to the degree of deviation. The maximum adjustment step for each gain calibration is np, where p is the minimum step gain per time and n is the maximum step size for each gain calibration, and np < h. For each gain calibration, first determine whether the relation PS - p ≤ P1 ≤ PS + p is satisfied. If it is satisfied, the FPGA control adjustment module adjusts the power according to the minimum step gain p. If it is not satisfied, add a minimum step gain and determine whether the relation PS - 2p ≤ P1 ≤ PS + 2p is satisfied. If it is satisfied, the FPGA control adjustment module adjusts the power according to the step gain 2p. If it is not satisfied, add a minimum step gain and determine whether the relation PS - 3p ≤ P1 ≤ PS + 3p is satisfied, and so on until the maximum step np for a single gain calibration is reached. At this time, regardless of whether PS - np ≤ P1 ≤ PS + np is satisfied, the FPGA controls the adjustment module to adjust the power according to the maximum adjustment step np to complete one gain calibration. Then the power detection module re - obtains the actual output power P1 of the current power amplifier module and performs the second - round gain calibration again, and re - determines whether the relation PS - p ≤ P1 ≤ PS + p is satisfied, repeating the content of 3) until the gain calibration is completed.

8. An automatic power calibration device based on FPGA according to claim 7, characterized in that The value of the minimum step gain p per time is 0.1 - 0.25 dB.

9. An automatic power calibration device based on FPGA according to claim 7, characterized in that, The maximum step size n for each gain calibration is n ≤ 20.

10. An automatic power calibration device based on FPGA according to claim 7, characterized in that, The adjustment module is a digital - controlled attenuator, and the value of the minimum step gain p per time is the minimum resolution of the digital - controlled attenuator.

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